This dissertation presents analog circuit analysis and design from a nonlinear dynamics perspective. An introduction to fundamental concepts of nonlinear dynamical systems theory is given. The procedure of nondimensionalization is used in order to derive the state space representation of circuits. Geometric tools are used to analyze nonlinear phenomena in circuits, and also to develop intuition about how to evoke certain desired behavior in the circuits. To predict and quantify non-ideal behavior, bifurcation analysis, stability analysis and perturbation methods are applied to the circuits. Experimental results from a reconfigurable analog integrated circuit chip are presented to illustrate the nonlinear dynamical systems theory concepts. Tools from nonlinear dynamical systems theory are used to develop a systematic method for designing a particular class of integrated circuit sinusoidal oscillators. This class of sinusoidal oscillators is power- and area-efficient, as it uses the inherent nonlinearity of circuit components to limit the oscillators' output signal amplitude. The novel design method that is presented is based on nonlinear systems analysis, which results in high-spectral purity oscillators. This design methodology is useful for applications that require integrated sinusoidal oscillators that have oscillation frequencies in the mid- to high- MHz range. A second circuit design example is presented, namely a bandpass filter for front end auditory processing. The bandpass filter mimics the nonlinear gain compression that the healthy cochlea performs on input sounds. The cochlea's gain compression is analyzed from a nonlinear dynamics perspective and the theoretical characteristics of the dynamical system that would yield such behavior are identified. The appropriate circuit for achieving the desired nonlinear characteristics are designed, and it is incorporated into a bandpass filter. The resulting nonlinear bandpass filter performs the gain compression as desired, while minimizing the amount of harmonic distortion. It is a practical component of an advanced auditory processor.

In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.

The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.

The notion of designing circuits based on charge sensing, charge adaptation, and charge programming is explored in this research. This design concept leads to a low-power capacitive sensing interface circuit that has been designed and tested with a MEMS microphone and a capacitive micromachined ultrasonic transducer. Moreover, by using the charge programming technique, a designed floating-gate based large-scale field-programmable analog array (FPAA) containing a universal sensor interface sets the stage for reconfigurable smart sensory systems. Based on the same charge programming technique, a compact programmable analog radial-basis-function (RBF) based classifier and a resultant analog vector quantizer have been developed and tested. Measurement results have shown that the analog RBF-based classifier is at least two orders of magnitude more power-efficient than an equivalent digital processor. Furthermore, an adaptive bump circuit that can facilitate unsupervised learning in the analog domain has also been proposed. A projection neural network for a support vector machine, a powerful and more complicated binary classification algorithm, has also been proposed. This neural network is suitable for analog VLSI implementation and has been simulated and verified on the transistor level. These analog classifiers can be integrated at the interface to build smart sensory systems.

Indiana University-Purdue University Indianapolis (IUPUI) / Neural signal processing to decode neural activity has been an active research area in the last few decades. The next generation of advanced multi-electrode neuroprosthetic devices aim to detect a multiplicity of channels from multiple electrodes, making the relatively time-critical processing problem massively parallel and pushing the computational demands beyond the limits of current embedded digital signal processing (DSP) techniques. To overcome these limitations, a new hybrid computational technique was explored, the Extended Analog Computer (EAC). The EAC is a digitally confgurable analog computer that takes advantage of the intrinsic ability of manifolds to solve partial diferential equations (PDEs). They are extremely fast, require little power, and have great potential for mobile computing applications. In this thesis, the EAC architecture and the mechanism of the formation of potential/current manifolds was derived and analyzed to capture its theoretical mode of operation. A new mode of operation, resistance mode, was developed and a method was devised to sample temporal data and allow their use on the EAC. The method was validated by demonstration of the device solving linear diferential equations and linear functions, and implementing arbitrary finite impulse response (FIR) and infinite impulse response (IIR) linear flters. These results were compared to conventional DSP results. A practical application to the neural computing task was further demonstrated by implementing a matched filter with the EAC simulator and the physical prototype to detect single fiber action potential from multiunit data streams derived from recorded raw electroneurograms. Exclusion error (type 1 error) and inclusion error (type 2 error) were calculated to evaluate the detection rate of the matched filter implemented on the EAC. The detection rates were found to be statistically equivalent to that from DSP simulations with exclusion and inclusion errors at 0% and 1%, respectively.