With the popularity of Smart Handset devices, much more discussion of the design and development of embedded systems, some of embedded system problems such as the stability and efficiency of the device, the easy-operating interface design and a variety of application design are more and more important. Application development in the embedded systems is often limited by the system resource such as memory. Compared with common computer systems, embedded system got very limited memory. Therefore, program development in the embedded systems often need to consider the problem of insufficient memory, and program design must also avoid using too large number of memory allocation to cause the program take up a lot of system memory, affecting the system operation, causing the system hazard. Java is one of the common programming languages using in the embedded system development. Based on the high portability, Java programs can easily port to another system environment by using the Java virtual machine. However, the Java programming is also restricted, such as Java programming is not allowed to access memory space direct, and the memory allocation and release are all controlled by the system, rather than users. The purpose of the research is to design a set of Java programming tools. It can be applied to Android Dalvik virtual machine, which is responsible for operating the memory allocation and release, to allow users to control memory so as to ensure that memory can be reused to avoid the system hazard caused by the system memory leak problem.

Because of the shortage of domestic energy resources in Taiwan, more than 97% of the energy has to be imported. The energy price has been increased dramatically during recent years due to the limited supply of conventional primary fossil energy resources. With the economic development and upgrade of people living standard, the electricity power consumption is increased significantly. To solve the problem, different strategies of energy conservation and CO2 emission reduction have been promoted by government to reduce that the peak loading growth and achieve better usage of electricity with more effective load management. This thesis proposes a digital smart meter which integrates the energy metering IC, microprocessor and hybrid communication schemes (Power Line Carrier/ZigBee/RS-485). The load control module and communication module are included in the smart meter to support various application functions. The embedded power management system (PMS) is also proposed to integrate with the smart meter to perform the demand response according to the real-time pricing and load management for residential and commercial customers. The master station can supervise the real-time power consumption of various load components to analyze the power consumption model of customers served and execute the demand load control. The actual demonstration system of embedded PMS has been set up to verify the function of energy management so that the customers have better understanding of power consumption by each appliance. In the future, the implementation of intelligent load control with an emergency load shedding of capability can help utility companies to achieve virtual power generation to enhance the power systems reliability. The customers may also reduce the electricity charge by executing demand response function, which disconnects the electricity service for non essential loads for either system emergency or high electricity peak pricing

Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging and testing mechanisms, such as: single-step debugging, breakpoints setting and detection, monitoring, and modification of internal resources. However, the shortcoming of the conventional embedded in circuit emulator (EICE) is that the operation of the processor has to be suspended during debugging, which is categorized as static debugging (Static Debug) and is infeasible for real-time debugging. Therefore, this paper proposes a design alternative to support the real-time system debugging without suspending the microprocessor via the debug hardware Coprocessor14 (the Debug Coprocessor). In this paper, the embedded in circuit emulator is combined with Coprocessor 14 to provide both the static debugging and Run-time system debugging. After incorporating CP14 with the debugging mechanism, the control of the debug hardware is no longer limited to use the IEEE 1149.1 test port during debugging. On the other hand, the set of debugging constraints and the observation of the internal state of the microprocessor can be achieved by inserting the Coprocessor instruction at the program level.

Positioning and navigation systems play an important role in our daily life, but now most of positioning systems were confined in outdoor environments, most of which were used on transportation. Therefore, the goal of this thesis is to develop a Pedestrian Dead Reckoning System (PDRS), which can not only be used to solve a problem of GPS out-of-lock, but also be used in the field of indoor positioning. In dangerous environments, such as the scene of a fire, when the rescue personnel have an accident on himself or discover a wounded who need to be salvaged, if the rescue personnel who has configured the PDRS, then the other rescue personnel can assist them immediately. In the part of hardware system, we used embedded system to be the primary part of the entire system, the embedded system has the characters of low power consumption and portability. Therefore, we chose the TI OMAP35x EVM platform to be our primary system of PDRS. In order to get the information of pedestrian, we also need the Inertial Measurement Unit (IMU) and Compass to provide the information of acceleration and heading for PDRS. To achieve the function of remote monitoring, we used wireless transmission module to send data of sensors to OMAP35x EVM. Finally, the most important function that we must accomplish in this thesis is to use OMAP35x EVM to build a real-time PDRS. In the part of software system, we use Linux OS and Qt SDK to build the software system of PDRS in this thesis. In the part of algorithm, we use step detection, step length estimation and dead reckoning method to construct the algorithm of PDRS in this thesis.

This dissertation studies and implements highly miniaturized bandpass filter designs for wireless System-in-Package (SiP) applications. Based on the coupling matrix synthesis method, the external quality factors and coupling coefficients can be extracted by selecting the proper tapped-line feeding position and coupling spacing in geometrical configuration. Despite their high performance, most conventional microstrip bandpass filter designs require a bulky area for achieving, making them difficult to implement SiP applications. This dissertation first develops a stacked LC resonator and a stacked spiral resonator (SSR) in an embedded passive substrate (EPS) for realizing miniature single- and multi-band bandpass filters. Moreover, multiple transmission zeros created on both sides of each passband provide high stopband roll-off rates. The designed performance and size are comparable to those of low-temperature co-fired ceramic (LTCC) bandpass filters. As another conventional means of implementing RF passive components, the integrated passive device (IPD) process can produce large-value inductors and high-density capacitors, simultaneously. This dissertation fully utilizes the advantages of IPD technology to implement very compact bandpass filter designs with multiple transmission-zero frequencies at stopband by using a high-density wiring planar transformer configuration. Furthermore, due to the fully symmetric geometry, the transformer-coupled bandpass filter can be easily converted into a balun bandpass filter, capable of providing a superior balance performance with a significantly higher common mode rejection ratio (CMRR) level. The electromagnetic (EM) simulation results, as obtained by using Ansys-Ansoft HFSS, agree with the measurement results for all of the proposed designs in this dissertation.

Taipower Company has already completed the installation of the Outage Management System (OMS) in all service districts. The attributes of all distribution equipments and customers have been included in the computerized mapping system. However, the phasing attributes of distribution transformers are not very accurate in the database because they are very difficult to be identified for the distribution systems. The phase information of transformers in the OMS database is often inconsistent with the actual service phase, which deteriorates the performance of distribution system analysis, planning, and operation of Taipower distribution systems. The objective of this thesis is to develop an innovative Phasor Measurement Unit (PMU) to support the phasing identification of distribution transformers in a very effective way. The proposed PMU is used to measure the low voltage signal at the secondary side of transformers to prevent the survey personnel from safety problem. With the measured phases information of distribution transformers stored in the embedded system, the attributes of transformer phases in OMS can be updated to improve the accuracy of database. For the underground distribution systems, it is very difficult to receive the 1PPS signal of GPS system for timing synchronous to support the proposed transformer phasing measurement because all transformers are located at the building basement. This thesis proposes a timing synchronous module by using the Temperature Compensated Crystal Oscillator, TCXO to maintain the timing accuracy with high precision. Before executing the phasing measurement, this module is calibrated using the GPS 1PPS signal with fuzzy control calibration algorithm. It is found that the proposed PMU module can maintain the timing synchronous with 6˚, during two hours time period which will support the transformer phasing measurement by providing the reference timing synchronous even without the GPS 1PPS signal.

In this thesis, we propose a high density non-classical unipolar CMOS width two embedded oxide (2EO) NMOS load. The words ¡§unipolar CMOS¡¨ refer to the fact that the conventional NMOS driver and the proposed 2EO NMOS load are presented in which the electron is the only carrier used. Among them, the 2EO scheme is used to isolate the inversion current. And the dominant current in the 2EO NMOS load is the punch through current which is not a destructive current mechanism. Our proposed CMOS, due to the same carrier used, does not have to compensate the layout width in load design. In addition, the shared terminal of output contacts and the elimination of N-well technique are also presented in our proposed CMOS. Therefore, the layout area can be reduced 72%, in comparison with conventional CMOS. Furthermore, the packing density can be increased and the fabrication cost can be reduced, respectively. We also find out that the delay time can be improved 39% to increase the operating frequency, as compared with the convention CMOS.

Along with the development of localization and navigation technologies, the Global Positioning System (GPS) plays an important role in our daily life, but it is confined in outdoor environments. The technology of human localization has been developed in recent years. This technology utilizes sensors to determine the movement of human and measure the distance of walking, which is not only used to solve the problem of GPS out-of-lock, but also used for the indoor localization. This thesis describes a human step-length recognition and real-time localization base on an embedded system. The goal of this system is to develop a gait pattern classification and pedestrian dead reckoning (PDR) method for human localization. Through the information of an Inertial Measurement Unit (IMU) and two force sensors mounted on a shoe, the wireless transmission module is used to send data of sensors to an embedded platform. Then the functions of step detection, step length estimation and gait pattern recognition can be achieved. According to coordinate transformation and the ZUPT algorithm, the accumulated error of velocity can be corrected. The dead reckoning method is used to obtain the information of location. Finally, the information of human location and gait patterns is sent to the Android system for remote monitoring.

In this study, a novel assembled-type tool was used to weld SS400 low-carbon steel plate using the friction stir spot welding. The welding tool was made of tungsten carbide embedded a circular rod made of the low-carbon steel. The superiority of this embedded material not only could effectively promote the interface temperature of the joint, but also the thickness of stir zone. Compared to previous studies, this novel tool can significantly improve the manufacturing cost and the trimming time. The welding apparatus composed of a vertical milling machine and a welding platform. The operating conditions of welding were as followings: the diameter of embedded material, the welding speed, and the vertical load. During the welding process, the interface temperature of the joint, the tool plunge depth, and the vertical load were simultaneously measured by the K-type thermocouple, a displacement sensor, and a load cell. Experimental results revealed that the interface temperature, the thickness of the stir zone, and the tensile strength of the welding joint was proportional to the diameter of the embedded material. The best welding condition is the embedded material diameter of 10mm, the vertical load of 8kN, the welding speed of 1200rpm, and the welding time of 100 seconds.

Application-specific optimization of embedded systems becomes inevitable to satisfy the market demand for designers to meet tighter constraints on cost, performance and power. On the other hand, the flexibility of a system is also important to accommodate the short time-to-market requirements for embedded systems. To compromise these incompatible demands, coarse-grained reconfigurable architecture (CGRA) has emerged as a suitable solution. A typical CGRA requires many processing elements (PEs) and a configuration cache for reconfiguration of its PE array. However, such a structure consumes significant area and power. Therefore, designing cost-effective CGRA has been a serious concern for reliability of CGRA-based embedded systems. As an effort to provide such cost-effective design, the first half of this work focuses on reducing power in the configuration cache. For power saving in the configuration cache, a low power reconfiguration technique is presented based on reusable context pipelining achieved by merging the concept of context reuse into context pipelining. In addition, we propose dynamic context compression capable of supporting only required bits of the context words set to enable and the redundant bits set to disable. Finally, we provide dynamic context management capable of reducing reduce power consumption in configuration cache by controlling a read/write operation of the redundant context words In the second part of this dissertation, we focus on designing a cost-effective PE array to reduce area and power. For area and power saving in a PE array, we devise a costeffective array fabric addresses novel rearrangement of processing elements and their interconnection designs to reduce area and power consumption. In addition, hierarchical reconfigurable computing arrays are proposed consisting of two reconfigurable computing blocks with two types of communication structure together. The two computing blocks have shared critical resources and such a sharing structure provides efficient communication interface between them with reducing overall area. Based on the proposed design approaches, a CGRA combining the multiple design schemes is shown to verify the synergy effect of the integrated approach. Experimental results show that the integrated approach reduces area by 23.07% and power by up to 72% when compared with the conventional CGRA.