<p>The development of advanced embedded systems requires a systematic approach as well as advanced tool support in dealing with their increasing complexity. This complexity is due to the increasing functionality that is implemented in embedded systems and stringent (and conflicting) requirements placed upon such systems from various stakeholders. The corresponding system development involves several specialists employing different modeling languages and tools. Integrating their work and the results thereof then becomes a challenge. In order to facilitate system architecting and design integration of different models, an approach that provides dedicated workspaces/views supported by structured information management and information exchange between domain models and tools is required.</p><p>This work is delimited to the context of embedded systems design and taking a model based approach. The goal of the work is to study possible technical solutions for integrating different models and tools, and to develop knowledge, support methods and a prototype tool platform.</p><p>To this end, this thesis examines a number of approaches that focus on the integration of multiple models and tools. Selected approaches are compared and characterized, and the basic mechanisms for integration are identified. Several scenarios are identified and further investigated in case studies. Two case studies have been performed with model transformations as focus. In the first one, integration of Matlab/Simulink® and UML2 are discussed with respect to the motivations, technical possibilities, and challenges. A preliminary mapping strategy, connecting a subset of concepts and constructs of Matlab/Simulink® and UML2, is presented together with a prototype implementation in the Eclipse environment. The second case study aims to enable safety analysis based on system design models in a UML description. A safety analysis tool, HiP-HOPS (Hierarchically Performed Hazard Origin and Propagation Studies), is partially integrated with a UML tool where an EAST-ADL2 based architecture model is developed. The experience and lessons learned from the experiments are reported in this thesis.</p><p>Multiple specific views are involved in the development of embedded systems. This thesis has studied the integration between system architecture design, function development and safety analysis through using UML tools, Matlab/Simulink, and HiP-HOPS. The results indicate that model transformations provide a feasible and promising solution for integrating multiple models and tools. The contributions are believed to be valid for a large class of advanced embedded systems. However, the developed transformations so far are not really scalable. A systematic approach for efficient development of model transformations is desired to standardize the design process and reuse developed transformations. To this end, future studies will be carried out to develop guidelines for model and tool integration and to provide support for structured information at both meta level and instance level.</p>

<p>The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. These SOCs usually contain a microprocessor, several DSP cores (Digital-Signal-Processors), other hardware blocks, on-chip memories and peripherals.</p><p>As new IC process technologies are deployed, with decreasing geometrical dimensions, the probabilities of hardware faults to occur during operation are increasing. Testing SOCs is becoming a very complex issue due to the increasing complexity of the design and the increasing need of a test mechanism that is able to achieve acceptable fault coverage in a short test application time with low power consumption without the use of external logic testers.</p><p>As a part of the overall test strategy for a SOC, functional self-testing of a DSP core is considered in this project to be applied in the field. This test is used to verify whether fault indications in systems are caused by permanent hardware faults in the DSP. If so, the DSP where the fault is located needs to be taken out of operation, and the board it sits on will be later replaced. If not, the operational state can be restored, and the system will become fully functional again.</p><p>The main purpose of this project is to develop a functional self-test of a DSP core, and to evaluate the characteristics of the test. This project also involves proposing a scheme on how to apply a functional test on a DSP core in an embedded environment, and how to retrieve results from the test. The test program shall run at system speed.</p><p>To develop and measure the quality of the test program, two different coverage metrics were used. The first is the code coverage metric achieved by simulating the test program on the RTL representation of the DSP. The second metric used was the fault coverage achieved. The fault coverage of the test was calculated using a commercial Fault Simulator working on a gate-level representation of the DSP. The results achieved in this report show that this proposed approach can achieve acceptable levels of fault coverage in short execution time without the need for external testers which makes it possible to perform the self-test in the field. This approach has the unique property of not requiring any hardware modifications in the DSP design, and the ability of testing several DSPs in parallel.</p>

<p>The recent increase in performance of embedded processors has enabled the use of computationally heavy asymmetric cryptography in small and power efficient embedded systems. The goal of this thesis is to analyze whether it is possible to use this type of cryptography to enhance the security in access systems.</p><p>This report contains a literature study of the complications related to access systems and their functionality. Also a basic introduction to cryptography is included.</p><p>Several cryptographic algorithms were implemented using the public library LibTomCrypt and benchmarked on an ARM7-processor platform. The asymmetric coding schemes were ECC and RSA. The tested symmetric algorithms included AES, 3DES and Twofish among others. The benchmark considered both codesize and speed of the algorithms.</p><p>The two asymmetric algorithms, ECC and RSA, are possible to be used in an ARM7 based access system. Although, both technologies can be configured to finish the calculations within a reasonable time-frame of 10 Sec, ECC archives a higher security level for the same execution time. Therefore, an implementation of ECC would be preferable since it is faster and requires less resources. Some further suggestions of improvements to the implementation is discussed in the final chapters.</p>

<p>The paper deals with the development of a remote management solution for embedded audio devices. The creation of a development environment for the embedded ARM target is discussed as well as several available solutions for remote system management. The creation of a service for stream and system management using SNMP is discussed as well as several changes to the SNMP standard to improve performance using multicast. The implementation of a proof-of-concept cross-platform user interface for the client side is described as well.</p>

<p>Alstom Power i Växjö arbetar med utveckling och försäljning av bland annat elektrofilter till</p><p>rökgasreningssystem vid olika typer av miljövårdsanläggningar för t.ex. kraftverksindustrin.</p><p>Dessa elektrofilter kontrolleras och regleras med hjälp av styrutrustning uppbyggd av ett</p><p>antal styrenheter som idag kommunicerar via en egentillverkad standard kallad ”Fläktbuss”. För</p><p>att övervaka detta system vill man använda handburna PDA och kommunicera med Fläktbussen</p><p>via USB. För att få kommunikationen mellan USB och Fläktbuss att fungera krävs någon form av</p><p>aktiv konvertering.</p><p>Detta examensarbete kommer att ta upp så väl problematik och lösningar kring det</p><p>problem som finns i samband med denna konvertering.</p> / <p>Alstom Power in Växjö develop and sell equipment like electro filters for enviromental purposes</p><p>for the power industry.</p><p>Those filters are controlled and regulated by controlunits, communicating via an Alstoms</p><p>own standrad called “Fläktbuss”. To supervise and maintain this system, a solution of PDA and</p><p>USB communication is intresting. To make this USB – Fläktbuss adaption an active conversion</p><p>of data is required.</p><p>This diplomawork will contain and discuss problems and solutions about this conversion.</p>

Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 81-85). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph. D.)--University of Washington, 2003. / Vita. Includes bibliographical references (p. 118-130).

SRAM is a significant component in high speed computer design, which serves mainly as high speed storage elements like register files in microprocessors, or the interface like multiple-level caches between high speed processing elements and low speed peripherals. One method to design the SRAM is to use commercial memory compiler. Such compiler can generate different density/speed SRAM designs with single/dual/multiple ports to fulfill design purpose. There are discrepancy of the SRAM timing parameters between extracted layout netlist SPICE simulation vs. equation-based Liberty file (.lib) by a commercial memory compiler. This compiler takes spec values as its input and uses them as the starting points to generate the timing tables/matrices in the .lib. Originally large spec values are given to guarantee design correctness. While such spec values are usually too pessimistic when comparing with the results from extracted layout SPICE simulation, which serves as the “golden” rule. Besides, there is no margin information built-in such .lib generated by this compiler. A new methodology is proposed to get accurate spec values for the input of this compiler to generate more realistic matrices in .lib, which will benefit during the integration of the SRAM IP and timing analysis.

This dissertation presents findings from two disparate research projects relating to the cathodic protection (CP) of piles supporting bridge elements. The first was a proof of concept study for developing a new hybrid pile repair system incorporating embedded sacrificial zinc anodes within a fiber reinforced polymer (FRP) wrap. The second was to develop and remotely monitor the performance of magnesium anodes protecting steel H-piles supporting two bridges in Florida. The hybrid FRP-CP system involved a proof-of-concept laboratory study to refine pressure / vacuum bagging systems for pile repair and to quantify the improvement in the FRP concrete bond. Two different FRP systems, one epoxy based and the other urethane based, were evaluated. Improvement in bond was determined through destructive pullout tests conducted on full-size pile specimens that were wrapped while partially submerged in a fresh water tank. The results showed that pressure led to significant improvement in FRP-concrete bond. Pressure was optimal for the epoxy-based system, while vacuum proved better for the urethane-based system. The pressure system was subsequently used to install FRP over embedded anodes in a field demonstration project where four corroding piles were repaired using the hybrid FRP-CP system. Cathodic protection was provided by embedding eight zinc anodes in each concrete pile. Protection below the water line was provided by bulk anodes. Reference electrodes were installed to monitor the performance of the CP system and data loggers were used to monitor the anodic current. Results from over 12 months of monitoring showed that the hybrid FRP-CP system worked and the current demand of the steel was lower in the FRP wrapped piles compared to the unwrapped control. Numerical simulations were carried out to determine how the hybrid FRP-CP system could be improved. Initially the investigation focused on determining if bulk anodes alone could be used to provide the required protection. Results showed that while bulk anodes were more effective in FRP wrapped piles, they could not provide adequate protection over the entire splash-zone. In view of this, a preliminary three dimensional finite element analysis was carried out using commercially available software. The analysis showed that anode strips embedded in the pile just beneath the surface may provide adequate protection. Such anodes would be easier to install and are an improvement over the system investigated. The second project involved the development of a remote monitoring system to assess the performance of a sacrificial anode cathodic protection system used for steel piles on two bridges along I-75 in Florida. The problem was the inexplicable consumption rate of the magnesium anodes. Commercially available systems and sensors were used to successfully monitor the environment and the anodic current of the CP system for over 12 months. A solution for the excess magnesium consumption was proposed through the incorporation of an in-circuit variable resistor that could regulate the current draw from the anode. The system was implemented but its performance will be monitored by the Florida Department of Transportation who assumed responsibility for the equipment. Initial results were promising.