Dans le domaine de l'aéronautique, les systèmes embarqués ont fait leur apparition durant les années 60, lorsque les équipements analogiques ont commencé à être remplacés par leurs équivalents numériques. Dès lors, l'engouement suscité par les progrès de l'informatique fut tel que de plus en plus de fonctionnali- tés ont été numérisées. L'accroissement permanent de la complexité des systèmes a conduit à la définition d'une architecture appelée Avionique Modulaire Intégrée (IMA pour Integrated Modular Avionics). Cette architecture se distingue des architectures antérieures, car elle est fondée sur des standards (ARINC 653 et ARINC 664 partie 7) permettant le partage des ressources de calcul et de communication entre les différentes fonctions avioniques. Ce type d'architecture est appliqué aussi bien dans le domaine civil avec le Boeing B777 et l'Airbus A380, que dans le domaine militaire avec le Rafale ou encore l'A400M. Pour des raisons de sûreté, le comportement temporel d'un système s'appuyant sur une architecture IMA doit être prévisible. Ce besoin se traduit par un ensemble d'exigences temps réel que doit satisfaire le système. Le problème exploré dans cette thèse concerne la vérification d'exigences temps réel dans les systèmes IMA. Ces exigences s'articulent autour de chaînes fonctionnelles, qui sont des séquences de fonctions. Une exigence spécifie alors une borne acceptable (minimale ou maximale) pour une propriété temporelle d'une ou plusieurs chaînes fonctionnelles. Nous avons identifié trois catégories d'exigences temps réel, que nous considérons pertinentes vis-à-vis des systèmes étudiés. Il s'agit des exigences de latence, de fraîcheur et de cohérence. Nous proposons une modélisation des systèmes IMA, et des exigences qu'ils doivent satisfaire, dans le formalisme du tagged signal model. Nous montrons alors comment, à partir de ce modèle, nous pouvons générer pour chaque exigence un programme linéaire mixte, c'est-à-dire contenant à la fois des variables entières et réelles, dont la solution optimale permet de vérifier la satisfaction de l'exigence.

In this report we investigate whether an embedded system can be used to determine materials quality by analysing the acoustic resonance frequencies. Through experiments the necessary specifications are established and suitable circuits constructed. Signal analysis is performed by a FFT-based algorithm. We have verified that the system is succesful in detecting the five strongest resonance frequencies and list these in order of amplitude. By using embedded devices, it's possible to lower the cost of purchase as well as power consumption dramatically compared to alternative solutions. / I denna rapport undersöker vi hurvida ett inbyggt system kan användas för att bestämma materialkvalité genom analys av akustiska resonansfrekvenser. Genom experiment fastställs de specifikationer systemet måste ha, varefter lämpliga kretsar konstrueras. Med hjälp av en FFT-baserad algoritm utförs viss signalanalys. Vi har verifierat att systemet framgångsrikt kan detektera de fem starkaste resonansfrekvenserna och lista dessa efter amplitud. Genom användandet av inbyggda system kan energiförbrukningen och inköpskostnaden bli mycket lägre än alternativa lösningar.

Cette thèse présente Lion, un système de navigation utilisant des informations visuelles et inertielles pour l'atterrissage planétaire de précision. Lion est conçu pour voler au-dessus de n'importe quel type de terrain, plat ou accidenté, et ne fait pas d'hypothèse sur sa topographie. Faire un atterrir un véhicule d'exploration planétaire autonome à moins de 100 mètres d'un objectif cartographié est un défi pour la navigation. Les approches basées vision tentent d'apparrier des détails 2D détectés dans une image avec des amers 3D cartographiés pour atteindre la précision requise. Lion utilise de façon serrée des mesures venant d'un nouvel algorithme d'appariement imagecarte afin de mettre à jour l'état d'un filtre de Kalman étendu intégrant des données inertielles. Le traitement d'image utilise les prédictions d'état et de covariance du filtre dans le but de déterminer les régions et échelles d'extraction dans l'image où trouver des amers non-ambigus. Le traitement local par amer de l'échelle image permet d'améliorer de façon significative la répétabilité de leur détection entre l'image de descente et l'image orbitale de référence. Nous avons également conçu un banc d'essai matériel appelé Visilab pour évaluer Lion dans des conditions représentatives d'une mission lunaire. L'observabilité des performances de navigation absolue dans Visilab est évaluée à l'aide d'un nouveau modèle d'erreur. Les performances du systèmes sont évaluées aux altitudes clés de la descente, en terme de précision de navigation et robustesse au changement de capteurs ou d'illumination, inclinaison de la caméra de descente, et sur différents types de relief. Lion converge jusqu'à une erreur de 4 mètres de moyenne et 47 mètres de dispersion 3 RMS à 3 kilomètres d'altitude à l'échelle.

Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit can always recover from such errors as the underlying semiconductor material is not damaged and hence, they are called soft errors. In nanometer technologies, the reduced node capacitance and supply voltage coupled with high packing density and lack of masking mechanisms are primarily responsible for the increased susceptibility of SRAMs towards soft errors. Coupled with these are the process variations (effective length, width, and threshold voltage), which are prominent in scaled-down technologies. Typically, SRAM constitutes up to 90% of the die in microprocessors and SoCs (System-on-Chip). Hence, the soft errors in SRAMs pose a potential threat to the reliable operation of the system. In this work, a soft-error-robust eight-transistor SRAM cell (8T) is proposed to establish a balance between low power consumption and soft error robustness. Using metrics like access time, leakage power, and sensitivity to single event transients (SET), the proposed approach is evaluated. For the purpose of analysis and comparisons the results of 8T cell are compared with a standard 6T SRAM cell and the state-of-the-art soft-error-robust SRAM cells. Based on simulation results in a 65-nm commercial CMOS process, the 8T cell demonstrates higher immunity to SETs along with smaller area and comparable leakage power. A 32-kb array of 8T cells was fabricated in silicon. After functional verification of the test chip, a radiation test was conducted to evaluate the soft error robustness. As SRAM cells are scaled aggressively to increase the overall packing density, the smaller transistors exhibit higher degrees of process variation and mismatch, leading to larger offset voltages. For SRAM sense amplifiers, higher offset voltages lead to an increased likelihood of an incorrect decision. To address this issue, a sense amplifier capable of cancelling the input offset voltage is presented. The simulated and measured results in 180-nm technology show that the sense amplifier is capable of detecting a 4 mV differential input signal under dc and transient conditions. The proposed sense amplifier, when compared with a conventional sense amplifier, has a similar die area and a greatly reduced offset voltage. Additionally, a dual-input sense amplifier architecture is proposed with corroborating silicon results to show that it requires smaller differential input to evaluate correctly.

As demand for real-time image processing increases, the need to improve the efficiency of image processing systems is growing. The process of image segmentation is often used in preprocessing stages of computer vision systems to reduce image data and increase processing efficiency. This dissertation introduces a novel image segmentation approach known as leap segmentation, which applies a flexible definition of adjacency to allow groupings of pixels into segments which need not be spatially contiguous and thus can more accurately correspond to large surfaces in the scene. Experiments show that leap segmentation correctly preserves an average of 20% more original scene pixels than traditional approaches, while using the same number of segments, and significantly improves execution performance (executing 10x - 15x faster than leading approaches). Further, leap segmentation is shown to improve the efficiency of a high-level vision application for scene layout analysis within 3D scene reconstruction. The benefits of applying image segmentation in preprocessing are not limited to single-frame image processing. Segmentation is also often applied in the preprocessing stages of video analysis applications. In the second contribution of this dissertation, the fast, single-frame leap segmentation approach is extended into the temporal domain to develop a highly-efficient method for multiple-frame segmentation, called video leap segmentation. This approach is evaluated for use on mobile platforms where processing speed is critical using moving-camera traffic sequences captured on busy, multi-lane highways. Video leap segmentation accurately tracks segments across temporal bounds, maintaining temporal coherence between the input sequence frames. It is shown that video leap segmentation can be applied with high accuracy to the task of salient segment transformation detection for alerting drivers to important scene changes that may affect future steering decisions. Finally, while research efforts in the field of image segmentation have often recognized the need for efficient implementations for real-time processing, many of today’s leading image segmentation approaches exhibit processing times which exceed their camera frame periods, making them infeasible for use in real-time applications. The third research contribution of this dissertation focuses on developing fast implementations of the single-frame leap segmentation approach for use on both single-core and multi-core platforms as well as on both high-performance and resource-constrained systems. While the design of leap segmentation lends itself to efficient implementations, the efficiency achieved by this algorithm, as in any algorithm, is can be improved with careful implementation optimizations. The leap segmentation approach is analyzed in detail and highly optimized implementations of the approach are presented with in-depth studies, ranging from storage considerations to realizing parallel processing potential. The final implementations of leap segmentation for both serial and parallel platforms are shown to achieve real-time frame rates even when processing very high resolution input images. Leap segmentation’s accuracy and speed make it a highly competitive alternative to today’s leading segmentation approaches for modern, real-time computer vision systems.

The complexity among embedded systems has increased dramatically in recent years. During the same time has the capacity of the hardware grown to astonishing levels. These factors have contributed to that software has taken a leading role and time-consuming role in embedded system development.Compared with regular software development, embedded development is often more restrained by factors such as hardware performance and testing capability. A solution to some of these problem has been proposed and that is a concept called virtual platforms. By emulating the hardware in a software environment, it is possible to avoid some of the problems associated with embedded software development. For example is it possible to execute a system faster than in reality and to provide a more controllable testing environment. This thesis presents a case study of an application specific virtual platform. The platform is based on already existing embedded system that is located in an industrial control system.  The virtual platform is able to execute unmodified application code at a speed twice of the real system, without causing any software faults. The simulation can also be simulated at even higher speed if some accuracy losses are regarded as acceptable.The thesis presents some tools and methods that can be used to model hardware on a functional level in an software environment. The thesis also investigates the accuracy of the virtual platform by comparing it with measurements from the physical system. In this case are the measurements mainly focused of the data transactions in a controller area network bus (CAN).

Unified Extensible Firmware Interface (UEFI) is an industry standard for implementing the basic firmware in the computers. This standard replaces BIOS. A huge amount of C code has been written for the implementation of UEFI. Yet there has been a very little focus on testing UEFI code. The thesis shows how the industry can perform a meaningful testing of UEFI. Spanning the test coverage with the help of test tools over all UEFI phases is a key objective. Moreover, techniques such as Test Driven Development and source code analysis are explained in terms of UEFI to make sure the bugs are minimized in the first place. The results show that the usage of test and analysis tools point to a large number of issues. Some of these issues can be fixed at a very early stage in the Software Development Life Cycle. For this reason the developers and testers should be convinced that they need to focus on testing UEFI from a software perspective.

We first propose a reconfigurable processor, which consists of a MicroBlaze processor augmented with a Field-Programmable Gate Array (FPGA) to mitigate the computing time for public-key cryptography algorithms. We first consider Virtex-II Pro from Xilinx to analyze the potential solution of a Field-Programmable Custom Computing Machine (FCCM), which is composed of MicroBlaze augmented with a Virtex-II FPGA. We then propose a cryptography-oriented reconfigurable array, called CryptoRA, that efficiently supports long-word integer addition, subtraction and comparison. As a result, RISC processor can potentially be augmented with the CryptoRA rather than Virtex-II. The three main features that CryptoRA has are: (i) an increased granularity of the logic tile, (ii) the extension of the dedicated carry chain over the horizontal direction, and (iii) the incremental splitting Look-Up Table. According to our simulations, the CryptoRA-based FCCM provides a significant performance improvement over an optimized pure-software solution at an acceptable cost.

A reprogrammable hardware platform is used for the Co-design and implementation of a computationally intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)). The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software Co-design methodologies and techniques, and it is designed, implemented and evaluated on two distinct platforms, not simply by simulations. FPGAs are used as part of the reconfigurable hardware in both a PCI-based environment and in a more successful System-on-Chip (SOC) platform, which takes advantage of the closely-coupled interconnection between the hardware and software, thus minimizing the communication overhead. The case study, findings and general analysis lead to a possible ideal architecture for future approaches. Moreover, a more general detailed strategy can be seen for the transformation from software to a Co-design paradigm, maximizing parallelism.

This thesis explores how question FORCE (Rizzi 1997) is represented and licensed in Korean polar alternative questions (Korean PAQs). The syntactic properties of polar alternative questions have not been fully discussed in the literature; this work seeks to address that gap. The thesis has two main components. First, I provide an initial detailed investigation into the syntactic structure of Korean polar alternative questions (Korean PAQs), also called A-not-A questions, such as ciwu-nun ca-ni an ca-ni? ‘Is Jiwoo sleeping or not?’ I argue that Korean PAQs consist syntactically of a single clause. In this respect, Korean PAQs are distinct from both alternative questions and polar questions. The second goal of this thesis is to account for the asymmetric behaviour of complementizers in main clauses and embedded clauses. Variant complementizers occur in main clauses in Korean PAQs, while neutralized ci is the only complementizer which is licensed to appear in embedded clauses. Furthermore, Korean PAQs are incompatible with constituent questions in main clauses, but compatible with them in embedded clauses. This asymmetry is explained by appealing to the notion of a unique illocutionary question force in main clauses. In main clauses, the syntactic constituent ForceP cannot carry more than one kind of illocutionary question force: it bears either constituent question force or polar alternative question force, but not both. In contrast, since embedded clauses contain non-question (non-answer-requiring) complementizers, separate question forms do not conflict with each other in this location. Based on a wide range of empirical data from Korean, this thesis proposes to distinguish Force (‘question’) complementizers in the main clauses from Type (‘interrogative’) complementizers in embedded clauses. The novel data from Korean polar alternative questions require a major rethinking of the received view on the analysis of complementizers as expressed in Rizzi (1997). My analysis shows that the pragmatic categories of illocutionary force are highly significant for syntactic analysis in ways that have not been treated consistently in theoretical discussions of questions, in particular as regards the very distinct roles of main and embedded ‘questions’. / Graduate