Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-04T08:51:13Z (GMT). No. of bitstreams: 1 Billo_EduardoAfonso_M.pdf: 759147 bytes, checksum: bacd2eb22dce28eed515a407e9f0a0e2 (MD5) Previous issue date: 2005 / Resumo: E cada vez mais comum encontrar implementacões de complexos sistemas dedicados em um único chip (telefones celulares, PDA's, etc.). Quanto mais complexos, maiores as dificuldades para atingir requisitos como área de silício ocupada, desempenho e consumo de energia. A compressão de código, inicialmente concebida para diminuir a memória ocupada, através da compactação do software, atualmente traz vantagens também no desempenho e consumo de energia do sistema, através do aumento da taxa de acertos à cache do processador. Este trabalho propõe o projeto de um descompressor de código, baseado na técnica PDC-ComPacket, implementado de forma integrada ao pipeline do Leon2 (SPARC V8). Chegou-se a uma implementação prototipada em FPGA, com razões de compressão (tamanho final do programa comprimido e do descompressor em relação ao programa original) variando entre 72% e 88%, melhora no desempenho de até 45% e redução de energia de até 35%, validado através de dois benchmarks: MediaBench e MiBench. Além disso, são apresentados uma série de experimentos que exploram os tradeoffs envolvendo compressão, desempenho e consumo de energia / Abstract: Implementations of Complex Dedicated Systems on a single chip has become very common (cell-phones, PDA's, etc.). As complexity grows, also grows the required effort to reach constraints such as the silicon area, performance and energy consumption. The code compression, initially conceived to decrease the memory size, today also brings advantages in the performance and energy consumption of the system, due to an increase in the processor's cache hit ratio. This document proposes the design of a code decompressor, based on the PDC-ComPacket technique, embedding it into the Leon2 (SPARC V8) pipeline. We have achieved a functional implementation on a FPGA, with compression ratios (compressed program plus decompressor size related to the original program) ranging from 72% to 88%, performance speed-up of up to 45% and a reduction on energy consumption of up to 35%, validated through two benchmarks: MediaBench e MiBench. In addiction, we present a bunch of experiments, exploiting the tradeoffs related to compression, performance and energy consumption / Mestrado / Arquitetura de Computadores / Mestre em Ciência da Computação

Le contexte incertain dans lequel évoluent les applications embarquées influencefortement ces dernières. L'objectif de disponibilité induit généralement une forteredondance matérielle et fonctionnelle. A l'inverse, le paramètre de consommation prôneun nombre et un fonctionnement à minima des ressources. Avec la réduction de latechnologie, la variabilité des procédés de fabrication induit la possibilité accrue dedéfaillances. De façon à garantir une qualité de service acceptable par l'utilisateur, et cesur la totalité de la durée de vie du circuit, il convient de mener des études associant dèsles phases amont les deux paramètres sûreté de fonctionnement et consommation. Cettethèse a pour objectif de proposer une nouvelle conception pour les réseaux de capteurssans fil, afin de réduire consommation d'énergie et d'augmenter la fiabilité du réseau. / The uncertain contexts in which recent WSN embedded applications evolve have bigimpact on these applications. Traditionally, the objective of availability generally doubleshardware and functional redundancy; it means that the overhead is doubled in term ofenergy and cost. Besides, wireless node system is powered by limited battery; hencepower consumption parameter is only set to a number of components and functionalitiesat minimum resources. However, due to the technology reduction, process variabilityconducts to increase the possibility of failures. In order to guarantee an acceptablequality of service for the users, and on the operating lifetime of the system, it should carrystudies at the upper phases involving both dependability and consumption constraints.This thesis aims to propose novel design for wireless sensor networks, in order to reduceenergy consumption and to increase network dependability.

Orientadores: Rangel Arthur, Jaime Frejlich / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Tecnologia / Made available in DSpace on 2018-08-27T09:07:10Z (GMT). No. of bitstreams: 1 Araujo_WilliamRobertode_M.pdf: 5397089 bytes, checksum: d2eae9ba62023ba097143f2d74e0fd24 (MD5) Previous issue date: 2015 / Resumo: Neste trabalho foi desenvolvido um instrumento capaz de realizar medidas em materiais fotossensíveis. Para estudar materiais fotossensíveis, por exemplo, o Bi12TO20, que em geral geram correntes muito baixas da ordem de dezenas de picoamperes, fez-se necessário obter um instrumento capaz de medir nessa ordem de grandeza e com baixo ruído. Para identificar estados localizados dentro do band gap de um semicondutor, que são gerados por defeitos estruturais, é necessário ter uma intensidade de luz com energia acima do nível de Fermi que consiga penetrar no semicondutor, e pelos testes realizados não foram facilmente detectados pela técnica convencional, fonte de luz branca seguida de um monocromador. O uso de LED (Light Emitting Diode) se mostrou promissor por ser barato e ter uma intensidade de luz muito maior que a luz monocromática produzida pelo monocromador. O instrumento possui um computador embarcado (Raspberry PI) que realiza o controle do hardware e possui uma interface Ethernet para conexão remota. O hardware é composto de: uma fonte de alimentação para controle da intensidade e modulação para os LEDs, um controle do posicionamento dos LEDs na amostra, um controle da fonte de alta tensão e um sistema de detecção síncrona para melhor coleta dos dados. Os testes realizados com amostra Bi12TO20 se mostrou compatível com resultados já apresentados pela literatura / Abstract: This work aims to an instrument to perform measurements in photosensitive materials. To study photosensitive materials, for example, Bi12TO20, it was necessary to obtain an instrument capable of measuring the scale and with low noise, which generally lead to very low currents on the order of tens of picoamperes. To identify located states within the band gap of a semiconductor, which structural defects are generated, it is necessary to have a light intensity with energy above the Fermi level can penetrate into the semiconductor, and the tests were not easily detected by the technique conventional white light source followed by a monochromator. The use of LED (Light Emitting Diode) has shown promise for being cheap and having a much higher light intensity that monochromatic light produced by the monochromator. The instrument has an embedded computer (Raspberry-PI) that performs hardware the control and an Ethernet interface for remote connection. The hardware is comprised of: a power supply for the control of intensity and modulation for the LED, a control of the positioning of LEDs on the sample, a high voltage supply control and a synchronous detection system for improved data acquisition. The results of performed tests with sample Bi12TO20 were compatible with results have been presented in the literature / Mestrado / Tecnologia e Inovação / Mestre em Tecnologia

Day by day, we are witnessing a considerable increase in number and range of applications which entail the use of embedded computer systems. This increase is closely followed by the growth in complexity of applications controlled by embedded systems, often involving strict timing requirements, like in the case of safety-critical applications. Efficient design of such complex systems requires powerful and accurate tools that support the designer from the early phases of the design process. This thesis focuses on the study of real-time distributed embedded systems and, in particular, we concentrate on a certain aspect of their real-time behavior and implementation: the time-triggered (TT) and event-triggered (ET) nature of the applications and of the communication protocols. Over the years, TT and ET systems have been usually considered independently, assuming that an application was entirely ET or TT. However, nowadays, the growing complexity of current applications has generated the need for intermixing TT and ET functionality. Such a development has led us to the identification of several interesting problems that are approached in this thesis. First, we focus on the elaboration of a holistic schedulability analysis for heterogeneous TT/ET task sets which interact according to a communication protocol based on both static and dynamic messages. Second, we use the holistic schedulability analysis in order to guide decisions during the design process. We propose a design optimisation heuristic that partitions the task-set and the messages into the TT and ET domains, maps and schedules the partitioned functionality, and optimises the communication protocol parameters. Experiments have been carried out in order to measure the efficiency of the proposed techniques.

The Transmission Control Protocol (TCP) is one of the core protocols of the Internet protocol suite. In the wired network, TCP performs remarkably well due to its scalability and distributed end-to-end congestion control algorithms. However, many studies have shown that the unmodified standard TCP performs poorly in networks with large bandwidth-delay products and/or lossy wireless links. In this thesis, we analyze the problems TCP exhibits in the wireless communication and develop TCP congestion control algorithm for mobile applications. We show that the optimal TCP congestion control and link scheduling scheme amounts to window-control oriented implicit primaldual solvers for underlying network utility maximization. Based on this idea, we used a scalable congestion control algorithm called QUeueIng-Control (QUIC) TCP where it utilizes queueing-delay based MaxWeight-type scheduler for wireless links developed in [34]. Simulation and test results are provided to evaluate the proposed schemes in practical networks. / by Gee Won Han. / Thesis (M.S.C.S.)--Florida Atlantic University, 2013. / Includes bibliography. / Mode of access: World Wide Web. / System requirements: Adobe Reader.

Cache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the success of real-time embedded systems. Various cache optimization schemes have been proposed to address the performance, power consumption, and predictability issues. However, currently available solutions are not adequate for real-time embedded systems as they do not address the performance, power consumption, and execution time predictability issues at the same time. Moreover, existing solutions are not suitable for dealing with multi-core architecture issues. In this dissertation, we develop a methodology through cache optimization for real-time embedded systems that can be used to analyze and improve execution time predictability and performance/power ratio at the same time. This methodology is effective for both single-core and multi-core systems. First, we develop a cache modeling and optimization technique for single-core systems to improve performance. Then, we develop a cache modeling and optimization technique for multi-core systems to improve performance/power ratio. We develop a cache locking scheme to improve execution time predictability for real-time systems. We introduce Miss Table (MT) based cache locking scheme with victim cache (VC) to improve predictability and performance/power ratio. MT holds information about memory blocks, which may cause more misses if not locked, to improve cache locking performance. / VC temporarily stores the victim blocks from level-1 cache to improve cache hits. In addition, MT is used to improve cache replacement performance and VC is used to improve cache hits by supporting stream buffering. We also develop strategies to generate realistic workload by characterizing applications to simulate cache optimization and cache locking schemes. Popular MPEG4, H.264/AVC, FFT, MI, and DFT applications are used to run the simulation programs. Simulation results show that newly introduced Miss Table based cache locking scheme with victim cache significantly improves the predictability and performance/power ratio. In this work, a reduction of 33% in mean delay per task and a reduction of 41% in total power consumption are achieved by using MT and VCs while locking 25% of level-2 cache size in an 4-core system. It is also observed that execution time predictability can be improved by avoiding more than 50% cache misses while locking one-fourth of the cache size. / by Abu Asaduzzaman. / Vita. / Thesis (Ph.D.)--Florida Atlantic University, 2009. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2009. Mode of access: World Wide Web.

Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring the available parallelism in the program. Designing of multiple parallel execution paths for parallel execution of the processor naturally incurs additional cost. The methodology presented in this dissertation has addressed the problem of improving performance in ASIPs, at minimal additional cost. The devised methodology explores the available parallelism of an application to generate a multi-pipeline heterogeneous ASIP. The processor design is application specific. No pre-defined IPs are used in the design. The generated processor contains multiple standalone pipelined data paths, which are not necessarily identical, and are connected by the necessary bypass paths and control signals. Control unit are separate for each pipeline (though with the same clock) resulting in a simple and cost effective design. By using separate instruction and data memories (Harvard architecture) and by allowing memory access by two separate pipes, the complexity of the controller and buses are reduced. The impact of higher memory latencies is nullified by utilizing parallel pipes during memory access. Efficient bypass network selection and encoding techniques provide a better implementation. The initial design approach with only two pipelines without bypass paths show speed improvements of up to 36% and switching activity reductions of up to 11%. The additional area costs around 16%. An improved design with different number of pipelines (more than two) based on applications show on average of 77% performance improvement with overheads of: 49% on area; 51% on leakage power; 17% on switching activity; and 69% on code size. The design was further trimmed, with bypass path selection and encoding techniques, which show a saving of up to 32% of area and 34% of leakage power with 6% performance improvement and 69% of code size reduction compared to the design approach without these techniques in the multi pipeline design.

Downloading software from a server usually takes a noticeable amount of time, that is, noticeable to the user who wants to run the program. However, this issue can be mitigated by the use of streaming software. Software steaming is a means by which software can begin execution even while transmission of the full software program may still be in progress. Therefore, the application load time (i.e., the amount of time from when an application is selected for download to when the application can be executed) observed by the user can be significantly reduced. Moreover, unneeded software components might not be downloaded to the device, lowering memory and bandwidth usages. As a result, resource utilization such as memory and bandwidth usage may also be more efficient. Using our streaming method, an embedded device can support a wide range of applications which can be run on demand. Software streaming also enables small memory footprint devices to run applications larger than the physical memory by using our memory management technique. In this dissertation, we present a streaming method we call block streaming to transmit stream-enabled applications, including stream-enabled file I/O. We implemented a tool to partition software into blocks which can be transmitted (streamed) to the embedded device. Our streaming method was implemented and simulated on an MBX860 board and on a hardware/software co-simulation platform in which we used the PowerPC architecture. We show a robotics application that, with our software streaming method, is able to meet its deadline. The application load time for this application also improves by a factor of more than 10X when compared to downloading the entire application before running it. The experimental results also show that our implementation improves file I/O operation latency; in our examples, the performance improves up to 55.83X when compared with direct download. Finally, we show a stream-enabled game application combined with stream-enabled file I/O for which the user can start playing the game 3.18X more quickly than using only the stream-enabled game program file alone.

In this dissertation, we implement efficient lock-based synchronization by a novel, high performance, simple and scalable hardware technique and associated software for a target shared-memory multiprocessor System-on-a-Chip (SoC). The custom hardware part of our solution is provided in the form of an intellectual property (IP) hardware unit which we call the SoC Lock Cache (SoCLC). SoCLC provides effective lock hand-off by reducing on-chip memory traffic and improving performance in terms of lock latency, lock delay and bandwidth consumption. The proposed solution is independent from the memory hierarchy, cache protocol and the processor architectures used in the SoC, which enables easily applicable implementations of the SoCLC (e.g., as a reconfigurable or partially/fully custom logic), and which distinguishes SoCLC from previous approaches. Furthermore, the SoCLC mechanism has been extended to support priority inheritance with an immediate priority ceiling protocol (IPCP) implemented in hardware, which enhances the hard real-time performance of the system. Our experimental results in a four-processor SoC indicate that SoCLC can achieve up to 37% overall speedup over spin-lock and up to 48% overall speedup over MCS for a microbenchmark with false sharing. The priority inheritance implemented as part of the SoCLC hardware, on the other hand, achieves 1.43X speedup in overall execution time of a robot application when compared to the priority inheritance implementation under the Atalanta real-time operating system. Furthermore, it has been shown that with the IPCP mechanism integrated into the SoCLC, all of the tasks of the robot application could meet their deadlines (e.g., a high priority task with 250us worst case response time could complete its execution in 93us with SoCLC, however the same task missed its deadline by completing its execution in 283us without SoCLC). Therefore, with IPCP support, our solution can provide better real-time guarantees for real-time systems. To automate SoCLC design, we have also developed an SoCLC-generator tool, PARLAK, that generates user specified configurations of a custom SoCLC. We used PARLAK to generate SoCLCs from a version for two processors with 32 lock variables occupying 2,520 gates up to a version for fourteen processors with 256 lock variables occupying 78,240 gates.

Recent years have witnessed the emergence of microprocessors that are embedded within a plethora of devices used in everyday life. Embedded architectures are customized through a meticulous and time consuming design process to satisfy stringent constraints with respect to performance, area, power, and cost. In embedded systems, the cost of the memory hierarchy limits its ability to play as central a role. This is due to stringent constraints that fundamentally limit the physical size and complexity of the memory system. Ultimately, application developers and system engineers are charged with the heavy burden of reducing the memory requirements of an application. This thesis offers the intriguing possibility that compilers can play a significant role in the automatic design space exploration and optimization of embedded memory systems. This insight is founded upon a new analytical model and novel compiler optimizations that are specifically designed to increase the synergy between the processor and the memory system. The analytical models serve to characterize intrinsic program properties, quantify the impact of compiler optimizations on the memory systems, and provide deep insight into the trade-offs that affect memory system design.