Τα ενσωματωμένα υπολογιστικά συστήματα έχουν αρχίσει να χρησιμοποιούνται ολοένα και περισσότερο τα τελευταία χρόνια, όχι μόνο σε βιομηχανικές ή άλλες εξεζητημένες εφαρμογές αλλά και στην καθημερινότητα μας. Αυτό οφείλεται στο γεγονός ότι η συγκεκριμένη τεχνολογία είναι φτηνότερη, ευέλικτη και λιγότερο ενεργοβόρος σε σχέση με τα αντίστοιχα ηλεκτρονικά κυκλώματα που χρησιμοποιούνταν παλιότερα. Η παρούσα διπλωματική εργασία περιγράφει αναλυτικά τη διαδικασία για τη σωστή ρύθμιση του συστήματος μας και την μεταγλώττιση (compilation) του πυρήνα του Linux προκειμένου να τρέχει χωρίς προβλήματα πάνω στην FPGA πλακέτα της Xilinx, Virtex 5. Σαν επεξεργαστή επιλέξαμε να χρησιμοποιήσουμε τον soft - core επεξεργαστή της Xilinx microblaze,προσθέτοντας σαν επιπλέον περιφερειακά την οθόνη TFT καθώς και την θύρα PS/2. Στη συνέχεια προκειμένου να καταδείξουμε τις δυνατότητες που έχει το σύστημα που “χτίσαμε”, εγκαταστήσαμε γραφικό περιβάλλον με ορισμένες εφαρμογές και εκτελούμε κρυπτογραφικές συναρτήσεις από το terminal του λειτουργικού μας. / The embedded computer systems have recently started to be present in a number of implementations, not only in the industrial setting but also in normal life applications. This is due to the fact that this particular technology is cheaper, more efficient and less power - consuming than its dedicated electronic counterparts. In this diploma thesis we will study the process for the proper configuration of our system and the compilation of Linux Kernel in order to have a completely functional embedded system on the Xilinx' s FPGA board, Virtex 5. We used the Microblaze soft - core processor and we added the TFT monitor and the PS/2 port as extra components to our system. Furthermore in order to present the capabilities of our system, we added the Nano - X graphical user interface and we run cryptographic algorithms through the terminal of the operating system.

Microcontroller platforms are heavily used in embedded solutions adopted in nearly every industry covering a wide range of applications and use cases. In the paper and pulp industry the change prompted by the rising popularity of data decentralisation, big data analysis and machine learning, forces companies to upgrade or renew old platforms used to collect and analyse data. This thesis will evaluate a generation change for a communication platform that collects data from a sensor, its capabilities regarding secure communication over TCP/IP with the possibility to implement an efficient machine-to-machine communication protocol. The main focus of the evaluation is development, implementation and integration of software for the embedded system with a real time operating system using the ARM Cortex M7. Using small open source tools and the powerful ARM core we were able to build a small, flexible, real time system that publishes sensor data over MQTT securely using TCP/IP and TLS.

L’objet de cette thèse porte sur la modélisation mathématique des générateurs physiques de nombres aléatoires, tout particulièrement dans le contexte des systèmes embarqués. Les axes principaux sont les modèles stochastiques des sources d'entropie, l’établissement de tests statistiques adaptés et l’exploitation des défauts détectés / The purpose of this thesis focuses on the mathematical modeling of physical random number generators, especially in the context of embedded systems. The main axes are the stochastic modeling of entropy sources, the establishment of appropriate statistical tests and the exploitation of detected weaknesses.

Nesse trabalho é apresentada uma arquitetura que habilita a geração de MPSoCs (Multiprocessors Systems-on-Chip) heterogêneos escaláveis, baseados em barramento, suportando ainda o uso de diferentes organizações de memória. A comunicação entre as tarefas é especificada por meio de uma estrutura de memória compartilhada, que evita colisões e promove ganhos energéticos através do disparo dinâmico de clock gating. Também é introduzida a técnica DCF (Dynamic Core Freezing), que incrementa a eficiência energética do MPSoC tirando proveito dos ciclos ociosos dos processadores durante os acessos à memória. Mais, a combinação das organizações de memória propostas habilita a exploração de migração de tarefas na arquitetura proposta, por meio da troca de contexto das tarefas na memória compartilhada. Além disso, é mostrado o simulador de alto-nível, baseado na arquitetura proposta, criado com o propósito de extrair os ganhos energéticos propiciados com o uso do clock gating e da técnica DCF. O simulador aceita como entrada arquivos de trace de execução de aplicações Java, com os quais ele gera um novo arquivo contendo o mapeamento das instruções encontradas nos arquivos de trace para diferentes classes de instrução. Dessa forma, podem ser modeladas diferentes arquiteturas de processadores, usando o arquivo com o mapeamento para simular o MPSoC. Mais, o simulador habilita ainda a exploração das diferentes organizações de memória da arquitetura proposta, de maneira que se pode estimar o seu impacto no número de instruções executadas, contenções no barramento, e consumo energético. Experimentos baseados em uma aplicação sintética, executando em um MPSoC composto por diferentes versões de um processador Java mostram um grande aumento na eficiência energética com um custo mínimo em área. Além disso, também são apresentados experimentos baseados em aplicações do benchmark SPECjvm98, que mostram o impacto causado na eficiência energética quando o tipo de aplicação é alterado. Mais, os experimentos mostram drásticos ganhos energéticos obtidos com a aplicação da técnica DCF sobre as memórias do MPSoC. / In this work we present an architecture that enables the generation of bus-based, scalable heterogeneous Multiprocessor Systems-on-Chip (MPSoCs), supporting different memory organizations. Intertask communication is specified by means of a shared memory structure that assures collision avoidance and promotes energy savings through a dynamic clock gating triggering. We also introduce a Dynamic Core Freezing (DCF) technique, which boosts energy savings taking advantage of processor idle cycles during memory accesses. Moreover, the combination of the memory organizations enables the architecture to exploit easy task migration by means of the task context saving in the shared data memory. Moreover, we show the high-level simulator, based on the proposed architecture, created in order to extract the energy savings enabled with the clock gating and the DCF techniques. The simulator accepts as input execution trace files of Java applications, from which it generates a new file that contains the mapping of the instructions found in the trace file for different instruction classes. This way, we can model different processor architectures, using the mapping file to simulate the MPSoC. Also, the simulator enables us to experiment with different memory organizations to estimate their impact on the executed instructions, bus contention, and energy consumption. As case study we have modeled different versions of a Java processor in order to experiment with different execution patterns over different memory organizations. Experiments based on a synthetic application running on an MPSoC containing different versions of a Java processor show a large improvement in energy efficiency with a minimal area cost. Besides that, we also present experiments based on applications of the SPECjvm98 benchmark, which show the impact on the energy efficiency when we change the application type. Moreover, the experiments show a huge improvement in the energy efficiency when applying the DCF technique to the MPSoC memories.

Este trabalho apresenta o projeto e arquitetura de uma plataforma para execução de Agentes com funções implementadas em hardware, tomando vantagem do uso de hardware reconfigurável. Os Agentes em hardware são implementados utilizando dispositivos FPGA (Field-programmable Gate Array). O trabalho estende trabalhos anteriores semelhantes na área, com o diferencial de adicionar suporte às funcionalidades de reconfiguração parcial do hardware, suportar aplicações que demandam alto desempenho em hardware – como processamento de sinais e imagens – e redução de recursos de hardware necessários para execução da interface em software. A plataforma proposta utiliza o framework JADE (Java Agent Development Framework), que é um dos frameworks mais populares no estado da arte de desenvolvimento de Agentes e compatível com outros frameworks de Agentes através da conformidade aos padrões FIPA (Foundation for Intelligent Physical Agents). Com o uso do JADE, a plataforma possibilita a comunicação entre Agentes com funções implementadas em hardware e Agentes puramente implementados em software dentro de um mesmo SMA (Sistema Multi-Agente). Uma funcionalidade notável do JADE é a possibilidade de migração de Agentes entre plataformas de um mesmo SMA. Através do uso da reconfiguração parcial de hardware em conjunto com o JADE, a plataforma permite a migração de Agentes de software para hardware e vice-versa, além de suportar reconfiguração de múltiplos Agentes em hardware com um único FPGA. A plataforma faz uso de um único chip através do uso de um processador soft core implementado na lógica programável. O uso deste processador é um diferencial neste trabalho, e mostra que é possível utilizar o JADE em sistemas embarcados com recursos de processamento limitados. Ou seja, em um Agente cuja principal função é implementada em hardware, basta um processador bastante simples para atuar como uma interface entre o hardware e o framework de Agentes. O uso do processador dentro do FPGA tem também o benefício de oferecer formas de acesso mais integrado ao hardware, permitindo maior desempenho na transmissão de dados ao hardware. A plataforma foi validada através de estudos de caso de Agentes com implementações em hardware e em software, incluindo um estudo de caso aplicado de processamento de imagem embarcado utilizando VANTs (Veículos Aéreos Não-Tripulados). O estudo também apresenta comparações de desempenho entre a execução dos Agentes em hardware e em outras plataformas embarcadas de prateleira. Os experimentos realizados mostram um ganho significativo de desempenho nas implementações em FPGA, especialmente considerando processamento de imagens de alta resolução, mesmo considerando que o FPGA executa em frequências consideravelmente reduzidas em comparação às outras plataformas testadas. / This work described the design and architecture of a platform for execution of Agents whose functions are implemented in hardware, by leveraging the use of reconfigurable hardware. The hardware Agents are implemented using FPGA (Field-programmable Gate Array) devices. This work extends previous similar work in this field, while adding the features of hardware partial reconfiguration, supporting applications which require high performance in hardware – such as image or signal processing – and reducing the hardware resource for the software interface execution. The proposed platform makes use of the JADE (Java Agent Development Framework) framework, which is one of the most popular frameworks in state-of-the-art Agent development, and is also compatible with other Agent development frameworks due to compliance with FIPA (Foundation for Intelligent Physical Agents) standards. With the use of JADE, the platform enables communication among Agents which are implemented in hardware and Agents purely implemented in software, inside the same MAS (Multi-Agent System). One notable feature of JADE is the possibility of migrating Agents among platforms inside a single MAS. Through the use of hardware partial reconfiguration along with JADE, the platform enables the migration of Agents from software to hardware and viceversa, in addition to supporting múltiple hardware Agents in a single FPGA. The platform makes use of a single chip, by using a MicroBlaze soft core processor implemented in programmable logic. The use of this processor is a distinction on this work, and it shows that it is possible to use JADE on embedded systems with limited processing power. That is, in an Agent whose main function is implemented in hardware, a very simple processor to act as an interface between hardware and the Agent framework is enough. The use of the soft core processor inside the FPGA also has the benefit of offering more integrated ways of accessing hardware, enabling higher performance for transferring data to hardware. The platform was validated through case studies of hardware and software Agent implementation, including a case study applied to image processing using UAVs (Unmanned Aerial Vehicles). The study also shows performance comparisons between the Agent execution in hardware and in other off-the-shelf embedded platforms. The performed experiments report a significative performance increase in the FPGA implementations, particularly in high resolution image processing, even considering that the FPGA runs in considerably lower clock frequency than the other tested platforms.

Radio Frequency Identification, RFID, is a wireless identification method which uses electromagnetic fields in order to communicate with electronic tags in the vicinity. In recent years, in conjunction with the digitalization of society, RFID has become a popular method for digital identification. RFID, as a method for digital identification, is often used for credit card payments in store, access control to locked rooms and renting books at libraries. As a result of RFID growing rapidly, different frequencies have emerged. In order to benefit from different frequencies, a multi frequency RFID-reader was designed. The purpose of this study was to examine which difficulties arise in the development of a small multi frequency RFID-reader. This study shows that a small multi frequency RFID-reader lacks the conditions that are required to reach the read distance specified in available research. Furthermore, the study shows it is difficult to read different tags simultaneously without the use of a RTOS or a multicore processor.

Dans cette thèse, nous proposons d'étudier le débogage interactif d'applications pour les systèmes embarqués MPSoC (Multi-Processor System on Chip). Une étude de l'état de l'art a montrée que la conception et le développement de ces applications reposent de plus en plus souvent sur des modèles de programmation et des frameworks de développement. Ces environnements définissent les bonnes pratiques, tant au niveau algorithmique qu'au niveau des techniques de programmation. Ils améliorent ainsi le cycle de développement des applications destinées aux processeurs MPSoC. L'utilisation de modèles de programmation ne garantit cependant pas que les codes pourront être exécutés sans erreur, en particulier dans le cas de la programmation dynamique, où ils offrent très peu d'aide a la vérification. Notre contribution pour résoudre ces challenges consiste en une nouvelle approche pour le débogage interactif, appelée Programming Model-Centric Debugging, ainsi qu'une implémentation d'un prototype de débogueur. Le débogage centré sur les modèles rapproche le débogage interactif du niveau d'abstraction fourni par les modèles de programmation, en capturant et interprétant les évènements générés pendant l'exécution de l'application. Nous avons appliqué cette approche sur trois modèles de programmation, basés sur les composants logiciels, le dataflow et la programmation d'accélérateur par kernels. Ensuite, nous détaillons comment nous avons développé notre prototype de débogueur, basé sur GDB, pour la programmation de la plate-forme STHORM de STMicroelectronics. Nous montrons aussi comment aborder le débogage basé sur les modèles avec quatre études de cas : un code de réalité augmentée construit à l'aide de composants, une implémentation dataflow d'un décodeur vidéo H.264 et deux applications de calcul scientifique. / In this thesis, we propose to study interactive debugging of applications running on embedded systems Multi-Processor System on Chip (MPSoC). A literature study showed that nowadays, the design and development of these applications rely more and more on programming models and development frameworks. These environments gather established algorithmic and programming good-practices, and hence speed up the development process of applications running on MPSoC processors. However, sound programming models are not always sufficient to reach or approach error-free codes, especially in the case of dynamic programming, where they offer little to no help. Our contribution to lighten these challenges consists in a novel approach for interac- tive debugging, named Programming Model-Centric Debugging, as well as a prototype debugger implementation. Model-centric debugging raises interactive debugging to the level of programming models, by capturing and interpreting events generated during the application execution (e.g. through breakpointed API function calls). We illustrate how we applied this approach to three different programming models, software components, dataflow and kernel-based programming. Then, we detail how we developed a debugger prototype based on GDB, for STMicroelectronics's STHORM programming environment. STHORM development toolkit provides supportive environments for component, dataflow and kernel-based programming. We also demonstrate how to tackle software debugging with our debugger prototype through four case studies: an augmented reality feature tacker built with components, a dataflow implementation of the H.264 video decoding standard and two scientific HPC computing applications.

Le développement des systèmes embarqués est complexe. Cette complexité a plusieurs origines.D’une part, elle provient des caractéristiques propres des systèmes embarqués (mesureet contrôle du monde physique, exécution sur une plate-forme physique limitée en ressources,autonomie, fiabilité, réactivité, . . . ) qui les distinguent des systèmes purement logiciels. D’autrepart, elle est due aux fortes contraintes industrielles auxquelles ces systèmes sont soumis : coûtset délais de développement et de fabrication, équipes pluri-disciplinaires, certification et documentationdes systèmes. Afin de maitriser cette complexité, un certain nombre de méthodeset de langages furent proposés. Ils mettent l’accent sur une modélisation de l’application etde la plate-forme constituant le système embarqué. Cependant, les notions de méthode et deprocessus de développement qui abordent le problème de description des activités à réaliserne sont pas bien connues dans le domaine de l’ingénierie des systèmes embarqués et les méthodesactuelles tirent peu parti de l’expérience capitalisée dans d’autres domaines d’ingénierietels que les systèmes d’information. L’enjeu de cette thèse est la définition, la formalisation etl’outillage d’une méthode couvrant le développement des systèmes embarqués. Pour ce faire,ces travaux ont été axés autour de quatre contributions majeures : (1) la formalisation d’unprocessus guidé et d’un langage permettant une modélisation homogène d’une application et desa plate-forme, (2) la composition de plates-formes complexes permettant une implémentationprogressive d’une application sur sa plate-forme réelle, (3) l’intégration de la gestion de projetet de la traçabilité couplées aux produits offrant au chef de projet un moyen de mesurer etde piloter l’avancement de progression, d’organiser son équipe et de paralléliser les développements,et (4) le développement d’un outil dédié aux supports du processus, du langage et de lagestion de projet. / Embedded system development is complex. This complexity has several sources. A firstone is embedded system own specificities (physical world measurement and control, executionon a physical resource-constrained platform, reliability, responsiveness, . . . ) that distinguishthemselves from software systems. Another one comes from industrial concerns about whomthese systems are subject to : product and development costs and delays, multidisciplinaryteams, system documentation and certification. To handle this complexity, few methods andlanguages have been proposed. They focus on a modeling of both application and platform partincluded in an embedded system. However, the notions of method and process model are barelyknown from the embedded system community and current methods do not capitalize on theknowledge acquired by other engineering domains like information systems. The goal of thisthesis is the definition, the formalization and the tooling of an embedded system developmentmethod. To do that, this work focuses on four main contributions : (1) the formalization ofa guided process and a language to ensure a consistent modeling of both the application andthe platform, (2) the composition of complex platforms to permit a progressive implementationof an application on its concrete platform, (3) the integration of a project management anda product traceability allowing the project manager to measure and monitor the developmentprogress, to organize his team and to parallelize the development, and (4) the development ofa tool designed to support the process, the language and the project management

New methods for monitoring the condition of roller element bearings in rotating machinery offer possibilities to reduce repair- and maintenance costs, and reduced use of environmentally harmful lubricants. One such method is sparse representation of vibration signals using matching pursuit with dictionary learning, which so far has been tested on PCs with data from controlled tests. Further testing requires a platform capable of signal processing and control in more realistic experiments. This thesis focuses on the integration of a hybrid CPU-FPGA hardware system with a 16-bit analog-to-digital converter and an oil pump, granting the possibility of collecting real-time data, executing the algorithm in closed loop and supplying lubrication to the machine under test, if need be. The aforementioned algorithm is implemented in a Zynq-7000 System-on-Chip and the analog-to-digital converter as well as the pump motor controller are integrated. This platform enables portable operation of the matching pursuit with dictionary learning in the field under a larger variety of environmental and operational conditions, conditions which might prove difficult to reproduce in a laboratory setup. The platform developed throughout this project can collect data using the analog-to-digital converter and operations can be performed on that data in both the CPU and the FPGA. A test of the system function at a sampling rate of 5 kHz is presented and the input and output are verified to function correctly.

Sigfox is one of the newly-emerging LPWAN (Low Power Wide Area Network) technologies aiming to provide power-efficient solutions to the world of IoT. This study presents a comparison between Sigfox Geolocation and GPS (Global Positioning System) in terms of power consumption and performance which includes three metrics: accuracy and precision, response rate and response time. This study includes for the first part a series of lab tests where Sigfox Geolocation and GPS were studied in a single Sleep, Wake up, Idle, Tx/Rx cycle. For the second part, field tests with different geographical parameters (altitude, population, mobility) were conducted. Results of lab tests show that power consumption difference between Sigfox and GPS is a linear function of Idle time. In field tests, GPS presents a far superior performance than Sigfox in all metrics and marginally better power efficiency for relatively short Idle interval. For both GPS and Sigfox, a correlation between power efficiency and performance was observed. Results show that GPS operates best in rural environments while Sigfox stands out in urban ones. Payload size was observed to affect Sigfox in both power consumption and performance while different transmission rates only affect power consumption but do not seem to impact the other metrics. A solution based on the outcome of this study is suggested for a freight-monitoring system where geolocation is handled by GPS and the coordinates transmitted via Sigfox. As an emerging technology under constant development, Sigfox Geolocation is expected to have improved performance in the near future.