In recent years Ethernet has cought the attention of the real-time community. the main reason for this is that it has a high data troughput, 10Mbit/s and higher, and good EMI characteristics. As a protocol that might be used in real-time anvironments such as control systems for cars etc, it seems to fulfil the rquirements. TTEthernet is a TDMA extention to normal Ethnernet, designed to meet the hard deadlines required by real-time networks. This thesis describes how TTEthernet handles frames and the mathematical formulas to calculate shuffle delay of frames in such a network. Open problems related to TTEthernet are also discussed.

This diploma work aims to invent an algorithm for use of serial interface SGMII (serial gigabit multimedia independent interface) in adaptive embedded data splitter for Gigabit Ethernet standard 1000Base-T interface and also to aplicate these algorithms to FPGA circuit.

Automotive Ethernet is a newly introduced in-vehicle bus that allows unicast communication between ECUs. It is based on the OSI model of Ethernet, with a few modifications on the physical layer and newly introduced application protocols. AUTOSAR, a consortium of automotive OEMs, Tier-1 suppliers and tool vendors has defined a standard software architecture that simplifies the ECU software development with its well defined software specifications and APIs. The Automotive Ethernet stack is now an integral part of the latest AUTOSAR specification release 4.2. Infineon Aurix TriCore TC27x microcontroller is a popular board used in ADAS applications. The board has support for Fast Ethernet. This thesis investigates the setting up of an Ethernet communication on the TriCore board running under AUTOSAR software architecture. The various modules of the AUTOSAR Ethernet stack are familiarized and configured. This is followed up by validating the implementation on the Ethernet physical layer. The validation is based on a real Ethernet communication between the TriCore board and the Vector VN5610 network interface card. TCP and UDP based connections between the AUTOSAR compliant board and the VN5610 are tested and validated. A test suite for evaluating the protocol conformance of the AUTOSAR Ethernet stack exists at Bertrandt. The final step of this thesis involved the execution strategies for this test suite.

Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur Rechnernetze und verteilte Systeme der Fakultaet fuer Informatik der TU Chemnitz. Technologieentwicklungen bei 10 Gigabit Ethernet (10GE) Erweiterung des Ethernet-Schichtenmodells bei 10 Gigabit Ethernet Uebertragungsverfahren auf verschiedenen Glasfasertypen bei verschiedenen Wellenlaengen

The Metro Ethernet network (MEN) expands the advantages of Ethernet to cover areas wider than LAN. MENs running Ethernet Services as specified by the Metro Ethernet Forum (MEF) are known as Carrier Ethernet Networks (CENs). CENs can cover not only metro areas, but it can expand to cover global areas by connecting multiple MENs. Next-generation CENs are expected to support 100 GbE. With arising technologies for Ultra Long-haul (ULH) networks the bandwidth bottleneck of CENs is shifting to other areas like the transport layer protocol (such as the Transport Control Protocol or TCP) and the chip-to-chip channel capacity found at the network edge, which in general has an electrical backplane. Traditional TCP is well known to have difficulties reaching the full available bandwidth, due to its inefficient AIMD mechanisms under a high-delay-bandwidth-product environment. At the network edge, network equipment with electrical backplanes poses many problems including inductive-capacitive effects that limit its bandwidth. These are the two main issues addressed in this work. To resolve the transport layer issue, this work proposes a transport protocol that fully utilizes the available bandwidth while preserving TCP-friendliness and providing QoS support that is compatible with Ethernet Services. It can guarantee throughputs above the Committed Information Rate (CIR), which is specified in the Service Level Agreement (SLA). To resolve the physical layer limitations, a novel optical coupling technique is examined to encourage the use of optical backplanes for network-edge and core technology. The proposed technique consists of aligning the normal of the laser emission plane, waveguide plane and the normal of the photodetector active region plane with the purpose of reducing optical power loss caused by common methods of light manipulation. By addressing the shortcomings of both Traditional TCP and electrical backplane technology the overall throughput can be significantly increased.

Na atualidade, as redes públicas de comunicação de dados representam uma nova oportunidade para a aplicação das tecnologias IEEE 802 (baseadas na tecnologia Ethernet). Tanto nas redes de acesso, como nas redes metropolitanas e de núcleo, existe uma crescente demanda pela instalação de equipamentos com grande número de interfaces Ethernet. Em alguns casos, opta-se por equipamentos capazes de emular os serviços das tecnologias legadas ATM/SDH sobre Ethernet e viceversa. Nesse sentido, novos protocolos e novas formas de transmissão de dados utilizando a tecnologia Ethernet estão surgindo para consolidar a convergência das redes de comutação de circuitos (infraestrutúra legada) e as redes de comutação de pacotes; com a ideia de constituir uma rede mais homogênea, flexível e de baixo custo. Um claro exemplo é a adessão dos protocolos de Operação, Administração e Manuntenção (OAM) nas redes Ethernet, os quais permitem um nível de controle semelhante ao de tecnologias como ATM e SDH. OAM possibilita a monitoração de falhas na rede, a configuração e o acompanhamento dos eventos de segurança, assim como também a contabilização de tráfego por assinante; permitindo desta forma o atendimento de diferentes SLAs (Service-Level Agreements) de clientes. Para que isto seja uma realidade, é muito importante reforçar o controle da borda que delimita a rede do cliente final da rede pública. Com esse fim, estão surgindo normas como a IEEE P802.1aj, que define um dispositivo de demarcação de rede que serve como entidade controladora de serviços entre o provedor e o cliente final; sendo sua principal característica o suporte OAM no enlace com o provedor de serviços. Este dispositivo - conhecido comercialmente como Ethernet Demarcation Device (EDD)- é o foco do presente trabalho. Este trabalho tem como objetivo principal desenvolver arquiteturas System-on-a-Programable Chip (SoPC) para um EDD de duas portas, partindo do desenvolvimento de módulos de propriedade intelectual (IP). Foram projetadas duas arquiteturas de EDD, as quais permitem o encaminhamento de pacotes entre duas portas Ethernet e incorporam um processador MicroBlaze para implementação Software do protocolo OAM, segundo a norma IEEE 802.3ah. Como resultado, foram elaborados 7 módulos IP: Módulo Fast Ethernet MAC (FEMAC), Módulo Gigabit Ethernet MAC (GEMAC), Módulo Packet FIFO, Módulo OAM Ethernet, Módulo MII Managment (MIIM), Módulo PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) e Módulo Bit-Error Rate Tester (BERT). Todos os módulos foram descritos em VHDL e logo sintetizados para um dispositivo FPGA da família Virtex-II Pro da Xilinx, quanto para standard-cells utilizando a tecnologia CMOS AMS 0.35μm únicamente nos Módulos FEMAC e GEMAC. Os resultados de síntese mostram que o Módulo MIIM e o Módulo PHY1000X possuim um melhor aproveitamento de recursos de área que seus equivalentes disponíveis no OpenCores e no CoreGen da Xilinx, respectivamente. As arquiteturas SoPC foram prototipadas sobre a placa de desenvolvimento AVNET Virtex-II Pro, a qual permite comunicação com dispositivos de rede através de interfaces elétricas e ópticas. Finalmente, é proposta uma metodologia de validação física das arquiteturas alvo para estas atenderem o regime de vazão máxima (1Gbit/s ou 100Mbit/s), assim como também testes de conformidade como os definidos pela norma IEEE 802.3. / Nowadays, public networks represent a new opportunity for the application of IEEE 802 technologies, which have their basis on Ethernet Technology. In both Access and Metropolitan and Core networks there is a growing demand for the installation of equipments with a large number of Ethernet interfaces. In some cases, equipments capable of emulating the services of the ATM/SDH legacy technologies over Ethernet (and vice versa) are chosen. In this manner, new protocols and data transmission forms using Ethernet technology are emerging in order to consolidate the convergence of circuit switching networks (traditional infrastructure) and packet switching networks; with the common objetive of constituting a more uniform, flexible, low-cost network. A good example is the incorporation of Operation, Administration and Maintenance (OAM) protocols in Ethernet networks, which allow a control level similar to that one of technologies such as ATM and SDH. OAM allows the monitoring of network fails, the configuration and tracking the security events, as well as the counting of traffic per client in a way that permits to attend several SLAs (Service-Level Agreements). In order to bring this to reality, it is critical to reinforce the control of the edge which limits the client network from the public networks. With this aim, standards such as IEEE P802.1aj are emerging; this standard defines a network demarcation device, which is used as a service controlling entity between the provider and the end customer, having as main feature the OAM support in the link with the service provider. This work is focused on this device, commercially known as Ethernet Demarcation Device (EDD). The principal objective of this work is to develop SoPC (System-on-a-Programable chip) architectures for an EDD, starting from the development of Intellectual Property Cores (IP). Two EDD architectures were designed, which allow the packet forwarding between two Ethernet interfaces and incorporate a Soft processor Microblaze for the SW implementation of the OAM protocol according to the standard IEEE802.3ah. As a result, eight IP cores were elaborated: Soft IP Core Fast Ethernet MAC (FEMAC), Soft IP Core Gigabit Ethernet MAC (GEMAC), Soft IP Core Packet FIFO, Soft IP Core OAM Ethernet, Soft IP Core MII Managment (MIIM), Soft IP Core PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) and the Soft IP Core Bit-Error Rate Tester (BERT). All IP modules were described in VHDL and then synthesized for the FPGA Xilinx Virtex-II Pro device, as well as for standard-cells using the CMOS AMS 0.35um technology for the modules FEMAC and GEMAC. The synthesis results show that the module MIIM and module PHY1000X have a better use of the area resources than the ones available in OpenCores and CoreGen of Xilinx respectively. The SoPC architectures were prototyped on AVNET Virtex-II Pro Development kit Board, which allows communication with network devices through electrical and optical interfaces. Finally, we propose a validation methodology of both architecture so these are able to attend a maximum throughput regimen (1Gbit/s ou 100Mbit/s), as well as appropriate levels of approval with what standard IEEE 802.3 defines.

Na atualidade, as redes públicas de comunicação de dados representam uma nova oportunidade para a aplicação das tecnologias IEEE 802 (baseadas na tecnologia Ethernet). Tanto nas redes de acesso, como nas redes metropolitanas e de núcleo, existe uma crescente demanda pela instalação de equipamentos com grande número de interfaces Ethernet. Em alguns casos, opta-se por equipamentos capazes de emular os serviços das tecnologias legadas ATM/SDH sobre Ethernet e viceversa. Nesse sentido, novos protocolos e novas formas de transmissão de dados utilizando a tecnologia Ethernet estão surgindo para consolidar a convergência das redes de comutação de circuitos (infraestrutúra legada) e as redes de comutação de pacotes; com a ideia de constituir uma rede mais homogênea, flexível e de baixo custo. Um claro exemplo é a adessão dos protocolos de Operação, Administração e Manuntenção (OAM) nas redes Ethernet, os quais permitem um nível de controle semelhante ao de tecnologias como ATM e SDH. OAM possibilita a monitoração de falhas na rede, a configuração e o acompanhamento dos eventos de segurança, assim como também a contabilização de tráfego por assinante; permitindo desta forma o atendimento de diferentes SLAs (Service-Level Agreements) de clientes. Para que isto seja uma realidade, é muito importante reforçar o controle da borda que delimita a rede do cliente final da rede pública. Com esse fim, estão surgindo normas como a IEEE P802.1aj, que define um dispositivo de demarcação de rede que serve como entidade controladora de serviços entre o provedor e o cliente final; sendo sua principal característica o suporte OAM no enlace com o provedor de serviços. Este dispositivo - conhecido comercialmente como Ethernet Demarcation Device (EDD)- é o foco do presente trabalho. Este trabalho tem como objetivo principal desenvolver arquiteturas System-on-a-Programable Chip (SoPC) para um EDD de duas portas, partindo do desenvolvimento de módulos de propriedade intelectual (IP). Foram projetadas duas arquiteturas de EDD, as quais permitem o encaminhamento de pacotes entre duas portas Ethernet e incorporam um processador MicroBlaze para implementação Software do protocolo OAM, segundo a norma IEEE 802.3ah. Como resultado, foram elaborados 7 módulos IP: Módulo Fast Ethernet MAC (FEMAC), Módulo Gigabit Ethernet MAC (GEMAC), Módulo Packet FIFO, Módulo OAM Ethernet, Módulo MII Managment (MIIM), Módulo PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) e Módulo Bit-Error Rate Tester (BERT). Todos os módulos foram descritos em VHDL e logo sintetizados para um dispositivo FPGA da família Virtex-II Pro da Xilinx, quanto para standard-cells utilizando a tecnologia CMOS AMS 0.35μm únicamente nos Módulos FEMAC e GEMAC. Os resultados de síntese mostram que o Módulo MIIM e o Módulo PHY1000X possuim um melhor aproveitamento de recursos de área que seus equivalentes disponíveis no OpenCores e no CoreGen da Xilinx, respectivamente. As arquiteturas SoPC foram prototipadas sobre a placa de desenvolvimento AVNET Virtex-II Pro, a qual permite comunicação com dispositivos de rede através de interfaces elétricas e ópticas. Finalmente, é proposta uma metodologia de validação física das arquiteturas alvo para estas atenderem o regime de vazão máxima (1Gbit/s ou 100Mbit/s), assim como também testes de conformidade como os definidos pela norma IEEE 802.3. / Nowadays, public networks represent a new opportunity for the application of IEEE 802 technologies, which have their basis on Ethernet Technology. In both Access and Metropolitan and Core networks there is a growing demand for the installation of equipments with a large number of Ethernet interfaces. In some cases, equipments capable of emulating the services of the ATM/SDH legacy technologies over Ethernet (and vice versa) are chosen. In this manner, new protocols and data transmission forms using Ethernet technology are emerging in order to consolidate the convergence of circuit switching networks (traditional infrastructure) and packet switching networks; with the common objetive of constituting a more uniform, flexible, low-cost network. A good example is the incorporation of Operation, Administration and Maintenance (OAM) protocols in Ethernet networks, which allow a control level similar to that one of technologies such as ATM and SDH. OAM allows the monitoring of network fails, the configuration and tracking the security events, as well as the counting of traffic per client in a way that permits to attend several SLAs (Service-Level Agreements). In order to bring this to reality, it is critical to reinforce the control of the edge which limits the client network from the public networks. With this aim, standards such as IEEE P802.1aj are emerging; this standard defines a network demarcation device, which is used as a service controlling entity between the provider and the end customer, having as main feature the OAM support in the link with the service provider. This work is focused on this device, commercially known as Ethernet Demarcation Device (EDD). The principal objective of this work is to develop SoPC (System-on-a-Programable chip) architectures for an EDD, starting from the development of Intellectual Property Cores (IP). Two EDD architectures were designed, which allow the packet forwarding between two Ethernet interfaces and incorporate a Soft processor Microblaze for the SW implementation of the OAM protocol according to the standard IEEE802.3ah. As a result, eight IP cores were elaborated: Soft IP Core Fast Ethernet MAC (FEMAC), Soft IP Core Gigabit Ethernet MAC (GEMAC), Soft IP Core Packet FIFO, Soft IP Core OAM Ethernet, Soft IP Core MII Managment (MIIM), Soft IP Core PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) and the Soft IP Core Bit-Error Rate Tester (BERT). All IP modules were described in VHDL and then synthesized for the FPGA Xilinx Virtex-II Pro device, as well as for standard-cells using the CMOS AMS 0.35um technology for the modules FEMAC and GEMAC. The synthesis results show that the module MIIM and module PHY1000X have a better use of the area resources than the ones available in OpenCores and CoreGen of Xilinx respectively. The SoPC architectures were prototyped on AVNET Virtex-II Pro Development kit Board, which allows communication with network devices through electrical and optical interfaces. Finally, we propose a validation methodology of both architecture so these are able to attend a maximum throughput regimen (1Gbit/s ou 100Mbit/s), as well as appropriate levels of approval with what standard IEEE 802.3 defines.

Na atualidade, as redes públicas de comunicação de dados representam uma nova oportunidade para a aplicação das tecnologias IEEE 802 (baseadas na tecnologia Ethernet). Tanto nas redes de acesso, como nas redes metropolitanas e de núcleo, existe uma crescente demanda pela instalação de equipamentos com grande número de interfaces Ethernet. Em alguns casos, opta-se por equipamentos capazes de emular os serviços das tecnologias legadas ATM/SDH sobre Ethernet e viceversa. Nesse sentido, novos protocolos e novas formas de transmissão de dados utilizando a tecnologia Ethernet estão surgindo para consolidar a convergência das redes de comutação de circuitos (infraestrutúra legada) e as redes de comutação de pacotes; com a ideia de constituir uma rede mais homogênea, flexível e de baixo custo. Um claro exemplo é a adessão dos protocolos de Operação, Administração e Manuntenção (OAM) nas redes Ethernet, os quais permitem um nível de controle semelhante ao de tecnologias como ATM e SDH. OAM possibilita a monitoração de falhas na rede, a configuração e o acompanhamento dos eventos de segurança, assim como também a contabilização de tráfego por assinante; permitindo desta forma o atendimento de diferentes SLAs (Service-Level Agreements) de clientes. Para que isto seja uma realidade, é muito importante reforçar o controle da borda que delimita a rede do cliente final da rede pública. Com esse fim, estão surgindo normas como a IEEE P802.1aj, que define um dispositivo de demarcação de rede que serve como entidade controladora de serviços entre o provedor e o cliente final; sendo sua principal característica o suporte OAM no enlace com o provedor de serviços. Este dispositivo - conhecido comercialmente como Ethernet Demarcation Device (EDD)- é o foco do presente trabalho. Este trabalho tem como objetivo principal desenvolver arquiteturas System-on-a-Programable Chip (SoPC) para um EDD de duas portas, partindo do desenvolvimento de módulos de propriedade intelectual (IP). Foram projetadas duas arquiteturas de EDD, as quais permitem o encaminhamento de pacotes entre duas portas Ethernet e incorporam um processador MicroBlaze para implementação Software do protocolo OAM, segundo a norma IEEE 802.3ah. Como resultado, foram elaborados 7 módulos IP: Módulo Fast Ethernet MAC (FEMAC), Módulo Gigabit Ethernet MAC (GEMAC), Módulo Packet FIFO, Módulo OAM Ethernet, Módulo MII Managment (MIIM), Módulo PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) e Módulo Bit-Error Rate Tester (BERT). Todos os módulos foram descritos em VHDL e logo sintetizados para um dispositivo FPGA da família Virtex-II Pro da Xilinx, quanto para standard-cells utilizando a tecnologia CMOS AMS 0.35μm únicamente nos Módulos FEMAC e GEMAC. Os resultados de síntese mostram que o Módulo MIIM e o Módulo PHY1000X possuim um melhor aproveitamento de recursos de área que seus equivalentes disponíveis no OpenCores e no CoreGen da Xilinx, respectivamente. As arquiteturas SoPC foram prototipadas sobre a placa de desenvolvimento AVNET Virtex-II Pro, a qual permite comunicação com dispositivos de rede através de interfaces elétricas e ópticas. Finalmente, é proposta uma metodologia de validação física das arquiteturas alvo para estas atenderem o regime de vazão máxima (1Gbit/s ou 100Mbit/s), assim como também testes de conformidade como os definidos pela norma IEEE 802.3. / Nowadays, public networks represent a new opportunity for the application of IEEE 802 technologies, which have their basis on Ethernet Technology. In both Access and Metropolitan and Core networks there is a growing demand for the installation of equipments with a large number of Ethernet interfaces. In some cases, equipments capable of emulating the services of the ATM/SDH legacy technologies over Ethernet (and vice versa) are chosen. In this manner, new protocols and data transmission forms using Ethernet technology are emerging in order to consolidate the convergence of circuit switching networks (traditional infrastructure) and packet switching networks; with the common objetive of constituting a more uniform, flexible, low-cost network. A good example is the incorporation of Operation, Administration and Maintenance (OAM) protocols in Ethernet networks, which allow a control level similar to that one of technologies such as ATM and SDH. OAM allows the monitoring of network fails, the configuration and tracking the security events, as well as the counting of traffic per client in a way that permits to attend several SLAs (Service-Level Agreements). In order to bring this to reality, it is critical to reinforce the control of the edge which limits the client network from the public networks. With this aim, standards such as IEEE P802.1aj are emerging; this standard defines a network demarcation device, which is used as a service controlling entity between the provider and the end customer, having as main feature the OAM support in the link with the service provider. This work is focused on this device, commercially known as Ethernet Demarcation Device (EDD). The principal objective of this work is to develop SoPC (System-on-a-Programable chip) architectures for an EDD, starting from the development of Intellectual Property Cores (IP). Two EDD architectures were designed, which allow the packet forwarding between two Ethernet interfaces and incorporate a Soft processor Microblaze for the SW implementation of the OAM protocol according to the standard IEEE802.3ah. As a result, eight IP cores were elaborated: Soft IP Core Fast Ethernet MAC (FEMAC), Soft IP Core Gigabit Ethernet MAC (GEMAC), Soft IP Core Packet FIFO, Soft IP Core OAM Ethernet, Soft IP Core MII Managment (MIIM), Soft IP Core PHY Ethernet PCS/PMA 1000Base-X (PHY1000X) and the Soft IP Core Bit-Error Rate Tester (BERT). All IP modules were described in VHDL and then synthesized for the FPGA Xilinx Virtex-II Pro device, as well as for standard-cells using the CMOS AMS 0.35um technology for the modules FEMAC and GEMAC. The synthesis results show that the module MIIM and module PHY1000X have a better use of the area resources than the ones available in OpenCores and CoreGen of Xilinx respectively. The SoPC architectures were prototyped on AVNET Virtex-II Pro Development kit Board, which allows communication with network devices through electrical and optical interfaces. Finally, we propose a validation methodology of both architecture so these are able to attend a maximum throughput regimen (1Gbit/s ou 100Mbit/s), as well as appropriate levels of approval with what standard IEEE 802.3 defines.

Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur Rechnernetze und verteilte Systeme der Fakultaet fuer Informatik der TU Chemnitz. Technologieentwicklungen bei 10 Gigabit Ethernet (10GE) Erweiterung des Ethernet-Schichtenmodells bei 10 Gigabit Ethernet Uebertragungsverfahren auf verschiedenen Glasfasertypen bei verschiedenen Wellenlaengen

Automotive Ethernet is a newly introduced in-vehicle bus that allows unicast communication between ECUs. It is based on the OSI model of Ethernet, with a few modifications on the physical layer and newly introduced application protocols. AUTOSAR, a consortium of automotive OEMs, Tier-1 suppliers and tool vendors has defined a standard software architecture that simplifies the ECU software development with its well defined software specifications and APIs. The Automotive Ethernet stack is now an integral part of the latest AUTOSAR specification release 4.2. Infineon Aurix TriCore TC27x microcontroller is a popular board used in ADAS applications. The board has support for Fast Ethernet. This thesis investigates the setting up of an Ethernet communication on the TriCore board running under AUTOSAR software architecture. The various modules of the AUTOSAR Ethernet stack are familiarized and configured. This is followed up by validating the implementation on the Ethernet physical layer. The validation is based on a real Ethernet communication between the TriCore board and the Vector VN5610 network interface card. TCP and UDP based connections between the AUTOSAR compliant board and the VN5610 are tested and validated. A test suite for evaluating the protocol conformance of the AUTOSAR Ethernet stack exists at Bertrandt. The final step of this thesis involved the execution strategies for this test suite.