Ce sujet de thèse a pour objectif principal la conception de protection contre les décharges électrostatiques (ESD) en technologie silicium avancée sur isolant film mince (FDSOI) avec la compatibilité substrat massif. Ceci suppose une caractérisation ESD des dispositifs élémentaires déjà existants et une conception complète de nouveaux dispositifs sur technologie FDSOI. Ces caractérisations se feront, soit en collaboration avec les équipes de caractérisation ESD présents à STMicroelectronics-Crolles, soit directement par le doctorant grâce au banc de test ESD présent dans le laboratoire pour les développements plus en amont si besoin. La caractérisation fine des mécanismes physiques et des performances des composants sera menée à IMEP qui dispose des équipements adéquats (bancs de mesures en basse et haute température, bruit, pompage de charge, etc) et d’une compétence scientifique incontournable. Il sera ensuite nécessaire d’effectuer des choix de stratégies de protection ESD en fonction des applications et des circuits visés par les équipes de STMicroelectronics. On gardera à l’esprit la notion de fiabilité dès la conception de la protection. Une des stratégies envisagée pour la réalisation de protections ESD compatibles avec des films ultra-minces est l’intégration de ces dispositifs sur substrats hybrides. En effet, il a été démontré chez STMicroelectronics en partenariat avec le LETI qu’il était possible de co-intégrer à partir d’un substrat SOI des dispositifs FDSOI ainsi que des dispositifs bulk. Ceci est rendu possible au moyen d’un réticule supplémentaire qui permet de venir retirer le film de silicium et l’oxyde enterré aux endroits voulus. Ainsi la protection ESD est similaire à celle réalisée sur silicium massif mais avec des implantations compatibles avec des dispositifs à film mince. Les dispositifs sont donc sensiblement différents de ceux réalisés sur bulk et nécessitent une caractérisation approfondie afin de les optimiser au mieux. Une approche ambitieuse vise à concevoir des composants SOI inédits, utilisables pour la protection ESD. Ce volet du travail sera en autre effectué sous la responsabilité de l’IMEP qui a récemment inventé et publié plusieurs types de transistors révolutionnaires : Z2-FET, TFET et BET-FET [12-14].Les études se feront sur des dispositifs silicium sur isolant issus des technologies de fabrication STMicroelectronics. Pour ce faire, il sera nécessaire d’appréhender les techniques de fabrication. Dans ce cadre, une simulation des processus de fabrication est envisagée sous la chaîne d’outil ISE-TCAD en C20nm et technologies futures. Tout d’abord ceci permettra d’embrasser l’ensemble des possibilités inhérentes à la création de nouveaux composants dans la technologie considérée et ensuite cette étude préliminaire fournira des structures de simulation pour les configurations ESD. Parallèlement, les outils TCAD de simulation physique du semi-conducteur à gap indirect type silicium seront mis à profit pour étudier plus précisément le comportement du composant élémentaire de protection ESD. Ces éléments peuvent être par exemple de type : diode, ggNMOS, Tr BIMOS, SCR ou SCR, T2, Beta-matrice, PPP… La synergie avec l’IMEP est essentielle pour l’identification et l’analyse des mécanismes physiques gouvernant le fonctionnement des dispositifs. Notamment, l’objectif principal est d’intégrer la protection ESD dans son application finale et d’évaluer son efficacité et son dimensionnement par l’intermédiaire de paramètres géométriques par exemple. Il sera également possible de réaliser des simulations mixtes afin de mieux tenir compte des effets 3D de la structure (effet de coins, dépolarisation de substrat) et de connaître l’influence des circuits de déclenchement associés à cette protection. L’optimisation de l’implantation de la protection ESD sera alors envisageable au regard des résultats de simulation. On se place ici dans le cadre d’une démarche de Co-Design de protection ESD. / "The thesis main objective is the design of protection againstelectrostatic discharge (ESD), for deep submicron (DSM)state-of-the-art fully depleted silicon-on-insulator technology (FDSOI).This requires the ESD characterization of existing elementary devicesand design of new FDSOI devices. The detailed characterization of thephysical mechanisms and device performance will be conducted at IMEPwhich has adequate facilities and scientific competence in this field.It will then be necessary to make choices for ESD protectionstrategies based on circuit applications by STMicroelectronics. Anambitious approach aims to develop novel SOI components used for ESDprotection. This part of the work will be performed under theresponsibility of IMEP as it has has recently invented and publishedseveral types of revolutionary transistors Z 2-FET, TFET andBET-FET. It will be necessary to understand the fabrication processtechnology of STMicroelectronics. In this framework, 3D simulation ofthe technology will be performed on TCAD software for 28nm FDSOI andfuture technologies. Physical simulation, with TCAD tools of thesemiconductor will be used to study more precisely the behavior of theelementary devices of ESD protection. Collaboration with the IMEP isessential for the identification and analysis of the physicalmechanisms governing device operation.In particular, the main objective is to integrate ESD protection andevaluate its effectiveness and design. It will also be possible toperform mixed-mode simulation to better analyse the effects of the 3Dstructure (corner effects, depolarization of substrate) and evaluatethe influence of trigger circuits associated with this protection.Optimizing the implementation of ESD protection will then be possible.Having studied from a theoretical point of view and numericalsimulation, ESD protection cells and trigger circuits associated withthe ESD protection strategy, qualification on silicon will be applied.This will be done by a test vehicle in the chosen SOI technology, andelectrical characterization of the structures and protection networkswill follow. Finally, the ESD performance will be analyzed to provideoptimization of the design and the choice of ESD protection strategybased on targeted applications."

O projeto de dispositivos ópticos integrados é de fundamental importância no desenvolvimento de sistemas de comunicações ópticas. Por esse motivo, várias técnicas de modelamento para estes dispositivos tem surgido na literatura. Esta corrida em direção à sofisticação das ferramentas de modelamento decorre da evolução natural dos processos de fabricação, que tem permitido a construção de estruturas com geometrias bastante complexas. Dentre as várias técnicas utilizadas atualmente nas simulações de dispositivos fotônicos destaca-se o método da propagação do feixe (BPM). Este método apresenta como grande atrativo o fato de ser de fácil implementação e de apresentar baixa carga computacional. Inicialmente, a técnica BPM foi empregada utilizando a equação de onda escalar de Helmholtz. Esta abordagem é eficiente desde que a diferença entre os índices de refração dos materiais utilizados no guia de onda seja pequena e que a geometria da estrutura não apresente variações na direção de propagação. Entretanto, a luz é uma onda eletromagnética que possui propriedades intrinsecamente vetoriais. As propriedades vetoriais (efeitos de polarização) tornam-se importantes quando estruturas que apresentam elevado contraste de índices de refração precisam ser investigadas. Neste trabalho o fenômeno da polarização é avaliado através da utilização da equação de onda semivetorial de Helmholtz em três dimensões, a qual é desenvolvida em termos das componentes transversais de campo magnético (Formulação H). A solução da equação de onda semivetorial de Helmholtz é obtida pelo método BPM expandido em diferenças finitas (FD). Os aproximantes de Padé de ordem (1,0), equivalentes à propagação no limite paraxial, e de ordem (1,1), equivalentes à propagação em ângulo largo, são implementados e seus resultados discutidos ) A propagação do campo no FD-BPM tridimensional proposto aqui se dá através da utilização da técnica implícita das direções alternadas (ADI), a qual proporciona uma ótima estabilidade com baixo esforço computacional. A validação deste método é feita através da simulação de guias de onda tipo rib, avaliando parâmetros numéricos como: passo de propagação longitudinal, largura da gaussiana de excitação inicial, passo de discretização transversal, número de iterações e índice de referência. Adicionalmente, também é investigada uma fibra óptica com geometria tipo D. Estes resultados serão comparados com os resultados existentes na literatura para estas estruturas a fim de garantir a eficácia do método. / It is well known that finite difference beam propagation methods have been a valuable tool for the simulation of a large variety of optical waveguides structures such as: Mach-Zehnder, Y junctions, directional couplers, switches, etc. The increasing complexity of these structures, either in terms of geometry or material composition, requires more accurate modeling techniques. Among the several techniques available nowadays the beam propagation method (BPM) is maybe the most celebrated one. This method has attracted a great deal of attention by virtue of its ease of implementation and low computational effort. Initially, the BPM was applied to solve the scalar Helmholtz equation. This approach can be quite efficient for waveguides exhibiting low refractive index contrast and no variation along the longitudinal direction. Light, by its turn, is an electromagnetic wave with intrinsically vectorial properties. The vectorial properties (polarization effects) become very important when high contrast and longitudinally varying structures are involved. In this work the polarization phenomenon is evaluated by means of the three-dimensional semivectorial Helmholtz equation, which is solved in terms of its transverse magnetic field components (H formulation). The solution of this semivectorial equation is obtained via the finite difference BPM method expanded in terms of the following Padé approximants: Padé(1,0), equivalent to the semivectorial equation in the paraxial limit, and Padé (1,1), the wide angle solution. The field propagation dynamics in both cases is performed via alternate direction implicit method (ADI), which provides good numerical stability and low computational effort. As far as the authors know, this is the first time that a wide-angle formalism based on Padé(1,1) and ADI technique is proposed to solve the semivectorial Helmholtz equation. The validation of this new wide-angle method is performed for three well known rib waveguides structures available in the literature, and its accuracy measured in terms of the following parameters: longitudinal step size, initial field (gaussian) width, transversal step size, iteration number, and reference refractive index. A D-shaped fiber is also investigated with this method for comparison purposes. The results obtained in all cases are checked against those available in the literature in order to guarantee the efficiency of the method.

Este trabalho tem por objetivo o desenvolvimento de métodos numéricos eficientes, tanto no domínio do tempo quanto na freqüência, para a modelagem da propagação de ondas em estruturas que apresentem combinações de meios convencionais e/ou metamateriais, particularmente os metamateriais onde tanto a permissividade quanto a permeabilidade são simultaneamente negativos. Em alguns casos à simulação de tais estruturas representa um grande desafio em virtude da grande demanda computacional requerida. Uma forma eficiente de se contornar este problema é a utilização de técnicas de divisão de operador, com destaque para a técnica implícita das direções alternadas (ADI), já amplamente explorada nos domínios do tempo e da freqüência, e mais recentemente a técnica localmente unidimensional (LOD). A técnica LOD é utilizada com destaque neste trabalho, onde pela primeira vez esta foi empregada em um método de propagação de feixe de ângulo largo em diferenças finitas no domínio da freqüência, o qual foi denominado por LOD FD-BPM. O passo seguinte foi estender sua aplicação para o domínio do tempo, sendo a primeira abordagem empregada em um método de propagação de onda em diferenças finitas no domínio do tempo, denominado por LOD TD-WPM. Em seguida, a técnica LOD foi aplicada ao método FDTD resultando em um formalismo implícito, denominado LOD-FDTD, o qual apresenta uma maior eficiência computacional do que o tradicional ADI-FDTD. Estas abordagens apresentaram uma excelente eficiência computacional em virtude da possibilidade de utilização de passos de tempos maiores do que o permitido pela condição de estabilidade de Courant-Friedrich-Levy (CFL), além de serem incondicionalmente estáveis como conseqüência da aplicação do esquema de Crank-Nicolson (CN). A restrição do método LOD-FDTD, referente à sua precisão de apenas primeira ordem no tempo, foi contornada com o uso do esquema de divisão de operadores conhecido como Strang splitting (SS), resultando no método de segunda ordem no tempo LOD-FDTD-SS. Os métodos FDTD, ADI-FDTD, LOD-FDTD e LOD-FDTD-SS foram também implementados com base no modelo de Drude com perdas, possibilitando, assim, uma modelagem adequada de meios metamateriais. Outra contribuição importante deste trabalho foi à implementação da condição de contorno split PML no formalismo LOD-FDTD para a simulação de problemas eletromagnéticos abertos. / This work focuses on developing efficient numerical methods, both in time and frequency domains, for modeling wave propagation in structures that present conventional media and/or metamaterial media combinations, particularly the metamaterials where both permeability and permittivity are simultaneously negative. In some cases, the simulation of such structures represent a great challenge, due to the great computational requirements. An efficient way of solving this problem is the usage of operator splitting techniques, specifically the alternate direction implicit (ADI) technique, already explored both in time and frequency domains, and recently the locally one-dimensional (LOD) . This work dedicates special attention to the LOD technique, where, for the first time, this one was applied in a finite difference frequency domain wide-angle propagation method, which was denominated LOD FD-BPM. The next step was to extend its application to the time domain, the first approach was used in a finite difference time domain wave propagation method, denominated LOD TD-WPM. Next, the LOD technique was applied to the FDTD method, resulting in an implicit formalism, denominated LOD-FDTD, which presents a better computational efficiency than the traditional ADI-FDTD. These approaches present an excellent computational efficiency, due to the possibility of using greater time steps than those permitted by the Courant-Friedrich-Levy (CFL) stability condition, being unconditionally stable as a consequence of applying the Crank-Nicolson (CN) scheme as well. The LOD-FDTD method restriction, referring to its first order accuracy in time, was circumvented by using the operator division scheme known as Strang splitting (SS), resulting in a second order time method LOD-FDTD-SS. The FDTD, ADI-FDTD, LOD-FDTD and LOD-FDTD-SS methods were also implemented with a lossy Drude model, making, this way, possible an adequate metamaterial media modeling. Another important contribution of this work was the implementation of the split PML contour condition in the LOD-FDTD formalism for the simulation of open electromagnetic problems.

Avec la diminution constante des dimensions des dispositifs électroniques, les structures MOS font face à de nombreux effets physiques liés à la miniaturisation. Dans le but de maintenir le rythme d'intégration indiqué par la loi de Moore, des nouvelles technologies, dont la structure résiste plus à ces effets physiques, remplacerons le transistor MOSFET bulk. Les modèles physiques permettant de prédire le comportement des transistors MOS atteignent rapidement leurs limites quand ils sont appliqués à ces structures émergentes. Ce travail de thèse est consacré au développement des modèles numériques et analytiques dédiés à la caractérisation des nouvelles architectures SOI et à substrat massif. Nous nous focalisons sur la modélisation du courant de drain basée sur le potentiel de surface, ainsi qu'à la modélisation du comportement en bruit basse fréquence de ces nouveaux dispositifs. Nous proposons un modèle explicite décrivant les potentiels de surface avant et arrière d'une structure SOI. Nous développons ensuite un modèle de bruit numérique et analytique permettant de caractériser les différents oxydes d'une structure FD SOI. La dernière partie de ce mémoire est consacrée à l'étude d'une nouvelle architecture du transistor MOS sur substrat massif. Une caractérisation de la conduction électrique de ce dispositif et de son comportement en bruit basse fréquence sont présentés / With the continuous reduction of the size of MOS devices, various associated short channel effects become significant and limit this scaling. To restrain this limit, multi-gate MOSFET devices seem to be more interesting, thanks to their better control of the gate on the channel. These new devices seem to be good candidates to replace the classical MOS architecture. The existing physical models used to predict the behaviour of MOSFET bulk devices are limited when they are applied to these emerging structures. This thesis is devoted to the development of numerical and analytical models dedicated to the characterization of new SOI architectures and bulk devices. We focus on the modeling of the drain current based on the surface potential as well was the modeling of the low frequency noise behaviour of these devices. We propose an explicit model describing the front and back surface potential of a FD SOI structure. We then develop numerical and analytical low frequency noise models allowing the characterization of the different oxides of a FD SOI structure. The last part of this thesis is devoted to the study of a new architecture of bulk MOS transistors. A characterization of the electrical conduction of this device and its low frequency noise behavior are presented

This diploma thesis examines the possibilities of a new method of astronomical calibration at the Pierre Auger Observatory in Argentina. Its goal is to use stars as objects with known brightness to calibrate the fluorescence detectors and compare these results with the existing calibration. The analysis was done using computer programs which use the star catalog and experimental background data to compare the current calibration with our method. Results that are presented conclude that the calibration using stars is consistent with the existing calibration, however, the error of the new method is much higher. Nevertheless, there is a good potential for scale - it could be used for all past and future data. Potential improvements to this method and its error are suggested.

Understanding the interaction of polyelectrolytes with oppositely charged lipid membranes is an important issue of soft matter physics, which provides an insight into mechanisms of interactions between biological macromolecules and cell membranes. Despite the fact that many (bio)macromolecules and filamentous supramolecular assemblies show semiflexible behavior, prior to this work very little was known about the conformational dynamics and Brownian motion of semiflexible particles attached to freestanding lipid membranes. In order to address these issues, diffusion and conformational dynamics of semiflexible DNA molecules and filamentous fd-virus particles electrostatically adsorbed to cationic freestanding lipid membranes were studied on the single particle level by means of optical wide-field fluorescence microscopy. Supergiant unilamellar vesicles (SGUVs) with diameters larger than 100 m represent a perfect model of a freestanding membrane. In this work, a method was developed that enabled the reliable and efficient electroformation of cationic SGUVs on ITO-coated coverslips. The utilization of SGUVs as model freestanding lipid bilayers allowed for determination of the previously unknown surface viscosity of DOPC/DOTAP membranes. In particular, the analysis of the translational diffusion coefficients of small (10, 20, 50 nm) membrane-attached anionic polystyrene beads has shown that the surface viscosity of DOPC/DOTAP membranes with CDOTAP = 1–7 mol% is independent of the DOTAP concentration and equals η = (5.9 ± 0.2) × 10−10 Pa s m. The fluorescence video-microscopy investigation of single DNA molecules attached to cationic SGUVs revealed a previously unreported conformational transition of a membrane-bound DNA molecule from a 2D random coil, the original conformation in which DNA attaches to the membrane, to a compact globule. This membrane-mediated DNA condensation is favored at high cationic lipid concentrations in the membrane and long DNA contour lengths. The DNA compaction rate in the coil–globule transition is 124 ± 46 kbp/s, and the resulting DNA globule sizes were found to be 250–350 nm at DOPC membranes containing 1 mol% DOTAP and 130–200 nm for 7 mol% DOTAP, indicating a stronger compaction for higher charge densities in the membrane. Additional experiments with freestanding cationic membranes in the gel state and supported cationic lipid membranes with gel–fluid coexistence suggest that the DNA collapse on a freestanding fluid cationic membrane may be initiated by a local lipid segregation in the membrane and is accompanied by local membrane deformations, which eventually stabilize the compact DNA globule. Furthermore, in this work single molecule studies of random-coil DNA molecules and filamentous fd-virus particles on a freestanding cationic lipid bilayer with a low charge density were carried out. The experiments revealed that these particles can be described as semiflexible chains in 2D. Taken together, DNA molecules and fd-virus particles cover a broad range of the ratio of contour length and persistence length from 0.4 to 82. The results of this work demonstrate that the mobility of such membrane-attached semiflexible particles is strongly affected by hydrodynamics in the lipid membrane and the surrounding bulk fluid, and can in essence be described using a hydrodynamics-based theory for a disk-shaped solid membrane inclusion with a characteristic size approximately equal to the radii of gyration of the particles.

L'efficacité énergétique est devenue une métrique clé de la performance des systèmes sur puce numériques, en particulier pour les applications tirant leur énergie de batteries ou de l'environnement. La miniaturisation technologique n'est plus suffisante pour atteindre les niveaux de consommation requis. Ce travail de recherche propose ainsi de nouvelles conceptions de circuits pour la génération d'horloge flexible, la mesure de puissance et de température ainsi que l'intégration de ces blocs au sein de systèmes sur puce complets.Le multiplieur de fréquence innovant en boucle ouverte proposé permet l'adaptation rapide de la fréquence générée (53MHz 0.5V - 889MHz 0.9 V). Sa surface réduite (981µm2) et faible consommation (0.45pJ/cycle à 0.5 V) facilitent son intégration dans des systèmes à basse consommation. Le capteur de puissance instrumente un convertisseur de tension switched-capacitor; validé sur deux architectures différentes, il permet une mesure de la puissance d'entrée et de sortie avec une précision de 2.5% à 6%. Enfin, un nouveau principe de capteur de température est proposé. Il exploite une méthode de calibration par body-biasing sur caisson n et un système numérique intégré pour la compensation de non-linéarité. Enfin, cette thèse illustre la manière dont ces circuits peuvent être intégrés pour assurer la gestion de consommation de systèmes complexes. Un travail de modélisation du body-biasing est proposé, illustrant sa complémentarité avec la gestion de tension d'alimentation. Puis trois exemples de stratégies de gestion de la consommation sont proposées au sein de systèmes complets. / Energy efficiency has become a key metric for digital SoC, especially for applications relying on batteries or energy harvesting. Hence, this work proposes new designs for on-chip flexible clock generator, power monitor and temperature sensor as well as the integration of those blocks within complete SoC.The novel open-loop clock multiplier architecture enables fast frequency scaling and is implemented to operate on the same voltage-frequency range as a digital core ((53MHz 0.5V - 889MHz 0.9 V). The achieved extremely low area (981µm2) and power consumption 0.45pJ/cycle 0.5 V) also ease its integration within low power SoC. The proposed power monitor instruments switched capacitor DC-DC converters, which are standard components of low voltage SoCs. The monitor has been demonstrated over two different converters topologies and provides a measurement of both the converter input and output power within 2.5% to 6% accuracy. Last, a new principle of temperature sensor is proposed. It leverages single n well body-biasing for calibration and integrated digital logic for large non-linearity correction. It is expected to achieve within 1C accuracy 0.1nJ / sample and 225 µm2 probe area. Then, this work illustrates how those circuits can be integrated within complex SoCs power management strategies. First, a modeling study of body biasing highlights the benefits it can provide in complement to voltage scaling, accounting for a wide temperature range. Last, three example of power management are proposed at SoC level.

Afin de suivre le rythme effréné des évolutions des systèmes embarqués et des dispositifs portables, il s’avère aujourd’hui indispensable d’optimiser la gestion de l’énergie sans pour autant compromettre la performance et la robustesse des circuits. Dans ce contexte, cette thèse étudie de nouveaux dispositifs de gestion de l’énergie ainsi que leur mise en œuvre, en combinant deux approches: la logique asynchrone et les techniques de polarisation du substrat (Adaptive Body Biasing - ABB). Cette thèse comporte quatre contributions permettant la conception de circuits asynchrones énergétiquement plus efficaces. 1) Une unité arithmétique et logique (UAL) asynchrone quasi insensible aux délais (Quasi Delay Insensitive - QDI) a été conçue et utilisée pour mener une analyse comparative entre systèmes synchrones et asynchrones. Cette étude démontre notamment  la meilleure efficacité énergétique et la plus grande robustesse des circuits asynchrones QDI, surtout lorsqu’ils fonctionnent à basse tension. 2) Une cellule standard a été spécialement développée pour mettre en œuvre nos schémas d’adaptation dynamique du substrat (ABB) qui ajustent la tension de seuil (Vth) des transistors. En outre, cette cellule s’est révélée très utile pour la détection de fautes transitoires causées par des radiations environnementales. Cette cellule est en outre un élément clé pour exploiter la polarisation du substrat, un des intérêts majeurs de la technologie FD-SOI, et d’améliorer la fiabilité du système. 3) Trois stratégies de polarisation de substrat ont été évaluées. Ces stratégies reposent sur la détection automatique de l’activité des circuits asynchrones QDI et de la polarisation de multiples domaines dans le substrat (Body Biasing Domains - BBD). De plus, une méthode pour analyser l’efficacité énergétique des stratégies de polarisation pour les circuits asynchrones QDI a également été proposée dans le cadre de cette thèse. 4) Enfin, un flot de conception de circuits numériques intégrés a été proposé et développé. Ce flot, basé sur des cellules standards, permet d’exploiter des stratégies de polarisation (ABB) avec plusieurs domaines (BBD) en utilisant la cellule standard spécialement développée. Un testchip a été conçu et fabriqué pour valider notre flot de conception et évaluer l’efficacité de la cellule proposée. / Keeping the fast evolving pace of embedded systems of portable devices require ameliorations of power management techniques, without compromising the circuit performance and robustness. In this context, this thesis studies novel energy management schemes, and how to implement them, by using two main design approaches: asynchronous logic and adaptive body biasing (ABB) techniques. Four main contributions have been done, thus enabling the design of more energy efficient asynchronous circuits. 1) We contributed with the design of a Quasi-delay Insensitive (QDI) asynchronous ALU architecture, used in a comparative analysis of asynchronous versus synchronous systems. This first study has demonstrated the energy efficiency and robustness of QDI circuits, especially if operating at low power supply (Vdd ). 2) We proposed a new body built-in cell for implementing ABB schemes by tuning the circuit threshold voltage (Vth) on-the-fly; and detecting short-duration and long-duration transient faults (TF) caused by environmental radiation. The proposed cell is a key building block to fully benefit from body biasing features of the FD-SOI technology while enhancing system’s reliability. 3) We assessed three different ABB strategies - based on automatic activity detection and multiple body-biasing domains (BBDs) - for QDI asynchronous circuits. Furthermore, a methodology for analyzing energy efficiency of ABB strategies in QDI asynchronous circuits is also proposed in this work. 4) We developed a standard cell-based IC design flow to apply ABB strategies with multiple BBDs by using the proposed body built-in cells. A testchip has been designed and fabricated to validate the developed design flow and the efficacy of the body built-in cell.

La réduction des dimensions des transistors à effet de champ MOS a depuis quelques années ralenti à cause de l'émergence de facteurs parasites tels que la résistance d'accès. En effet, la miniaturisation du canal s'est accompagnée par une diminution de sa résistance tandis que celle des zones d'accès à la frontière avec le canal est restée constante ou a augmenté. L'objectif de cette thèse a été de mettre en place une méthodologie de caractérisation électrique prenant en compte cette composante parasite longtemps considérée négligeable dans le milieu industriel.Dans un premier chapitre, le fonctionnement de la technologie CMOS et la spécificité de son adaptation FD-SOI sont d'abord présentées. La deuxième moitié du chapitre est quant à elle consacrée à l'état de l'art de la caractérisation électrique et de leur position vis-à-vis de la résistance d'accès.Le second chapitre présente une nouvelle méthode d'extraction des composantes parasites résistives et capacitives à l'aide de transistors de longueurs proches. Les résultats obtenus sont ensuite comparés aux modèles existants. De ces derniers, un nouveau modèle plus physiquement pertinent est proposé en fin de chapitre.Le troisième chapitre expose une nouvelle méthode de caractérisation électrique basée sur la fonction Y qui permet une analyse du comportement d'un transistor sur l'ensemble de son régime de fonctionnement. Cette nouvelle méthode est ensuite combinée à celle développée dans le chapitre 2 pour assembler un protocole expérimentale permettant de corriger et d'analyser l'impact des résistances d'accès sur les courbes de courant et les paramètres électriques.Finalement, le dernier chapitre applique la méthodologie vue dans la chapitre précédent à l'étude du désappariement stochastique des transistors. Les résultats obtenus sont ensuite comparés aux méthodes en vigueur dans les domaines industriel et académique qui présentent chacune leurs avantages et leurs inconvénients. La nouvelle méthode ainsi proposée tente de garder le meilleur de chacune de ces dernières. / The reduction of the dimensions of field effect MOS transistors has slowed down during the last years due to the increasing importance of parasitic factors such as access resistance. As a matter of fact, channel miniaturisation was accompanied by a reduction of its intrinsic resistance while that of the access region at the frontier with the channnel stayed constant or increased. The goal of this thesis was to set a new electrical characterization method to take into account this parasitic component long considered negligible in by industrials.In the first chapter, CMOS technologies working and its FD-SOI adaptation specificities are presented. The second half of the chapter deals with the state of the art of electrical characterization and their hypothesis about access resistance.The second chapter present a new resistive and capacitive parasitic components extraction method using transistors of close channel length. The results are then compared to existing models from which, a new one more physically accurate is proposed.The third chapter expose a new electrical characterization method based on Y function allowing the analyze of transistor behavior on the whole working regime. This new method is then combined with the one developped in the previous chapter to build a new experimental protocol to correct and analyze the impact of access resistances on current curves and parameters.Finally, the last chapter apply this new methodology to the case of stochastic mismatch between transistors. The results are then compared to the methods used by industrials and academics, each of them having their own pros and cons. The new method proposed tries to keep the best of both previous one.

Ce travail de thèse s’inscrit dans la technologie de fabrication de transistors à canal mince (Si ou SiGe) totalement déserté sur isolant (Fully-Depleted Silicon-on-Insulator ou FDSOI) qui constitue une option prometteuse pour les nœuds 14nm et au-delà. Les problèmes liés à cette nouvelle technologie sont dus à : (1) l’existence d’instabilités morphologiques conduisant, lors de recuits haute température, à la fragmentation de la couche mince formant le canal, (2) la nécessité d’une reprise d’épitaxie SiGe:B afin de former, sur le canal, des sources et drains surélevées (Raised Source and Drain ou RSD) et (3) des problèmes liés à l’hétérogénéité du dopage induits par l’importance des interfaces substrat/canal, canal/Source et canal/Drain.Ce travail expérimental a été effectué au sein de la société STMicroelectronics en partenariat avec le Centre Interdisciplinaire de Nanoscience de Marseille. Les principaux résultats obtenus sont : 1/ La mise au point, puis l’optimisation d’une méthode de nettoyage de surface à basse température permettant d’éviter la fragmentation du canal observée lors de recuits haute température.2/ L’optimisation des conditions de préparation de la surface du canal permettant de réaliser une bonne reprise d’épitaxie pour les sources et drains surélevées.3/ L’optimisation, via l’incorporation de carbone, des profils de dopage au bore des sources et drains épitaxiés. Les tests électriques effectués sur dispositifs industriels montrent que, grâce aux développements réalisés au cours de ces travaux de thèse, le pourcentage de puces actives sur une plaque est passé de 40% à 90%. / This work concerns the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology, which is a promising option for the technical nodes beyond 14nm.The use of a very thin Si or SiGe channel causes new technological problems due to (1) morphological instabilities that break the film during its high temperature annealing, (2) the necessity to grow Raised Source & Drain (RSD) by epitaxial Chemical-Vapor Deposition (CVD) of SiGe:B, (3) the non-uniformity of the boron profile in the channel because of the number of interfaces (substrate/channel, channel/ source, channel/drain). This experimental work has been performed at STMicroelectronics and Nanoscience Interdisciplinary Center of Marseille laboratory. The main results are:1/ The definition and the improvement of an efficient low temperature surface-cleaning process that avoids the dewetting of the channel.2/ The optimization of the surface preparation of the channel for a subsequent epitaxial growth of RSD materials compatible with electronic requirements.3/ The improvement, via carbon incorporation, of the boron dopant profile in the epitaxially grown RSD. Analysis of electrical devices show that all these improvements lead to a huge enhancement of the percentage of electrical active dies per wafer (from 40% to 90 %).