This paper is dedicated to the empirical analysis of the pilot trainee project Stáže ve firmách, which is considered as treatment in this analysis. The main objective of the empirical analysis is estimation of average treatment effect(ATE) and average treatment effect on treated(ATET) for characteristics like socioeconomic status and wage. Counterfactual methods for policy impact evaluation like Difference in Differences Estimator(DiD), First Differences Estimator(FD) and Propensity Score Matching(PSM) are used to estimation mentioned effects. This paper contains extension of Assignment Problem that is used for people matching purposes as alternative for PSM. This way of matching provides better control over creation of couples. Resulting pairs are more similar in selected characteristics due to better control during couples creation process.

This thesis deals with the application using digitally controlled current amplifiers DACA (Digitally Adjustable Current Amplifer), which was developed at the Department of Telecommunications FEEC in cooperation with ON Semiconductor in 2010. In introduction is decribed the topic of active filters and oscillators. Farther active current components, besides DACA are described current conveyor UCC (Universal Current Conveyor), current amplifier DO-CF (Dual-Output Current Follower), MO-CF (Multiple-Output Current Follower) and FD-CF (Fully Diferential Current Follower) and operational transconductant amplifier BOTA (Balanced-Output Operational Transconductance Amplifer) and MOTA (Multiple-Output Operational Transconductance Amplifier). The following is a compilation of theories circuits using signal flow graphs, which are designed using a simulated filter circuits to control the cutoff frequency or the quality factor. Then design and simulation with auxiliary oscillator circuit AGC for controlling the oscillation frequency. Simulations are conducted with ideal models and with models that include some real properties. The conclusion of this work is devoted to the printed circuit board design for a selected filter circuit realization and measurement.

In this report the regular finite differences method (FDM) and a least-squares radial basis function-generated finite differences method (RBF-FD-LS) is used to solve the two-dimensional incompressible Navier-Stokes equations for the lid driven cavity problem. The Navier-Stokes equations is solved using stream function-vorticity formulation. The purpose of the report is to compare FDM and RBF-FD-LS with respect to accuracy and computational cost. Both methods were implemented in MATLAB and the problem was solved for Reynolds numbers equal to 100, 400 and 1000. In the report we present the solutions obtained as well as the results from the comparison. The results are discussed and conclusions are drawn. We came to the conclusion that RBF-FD-LS is more accurate when the stepsize of the grids used is held constant, while RBF-FD-LS costs more than FDM for similar accuracy.

Les besoins en débit d’information à transmettre ne cessent de croitre. Aussi la généralisation des émetteurs-récepteurs large-bande implique l’intégration de solutions sur une technologie silicium CMOS afin que leur cout soit compatible avec une application grand public. Si l’intégration massive des traitements numériques est facilitée par les dernières technologies CMOS, la fonction de conversion analogique-numérique est quant à elle plus difficile. En effet, afin d’optimiser l’étage frontal analogique, le convertisseur analogique-numérique (CAN) doit répondre à des contraintes très fortes en termes de largeur de bande (de l’ordre du GHz) et de résolution (de 10 à 14bits). Les convertisseurs analogique-numérique basés sur l’entrelacement temporel (CAN-ET) connaissent un essor remarquable car ce sont aujourd’hui les seuls à pouvoir répondre aux deux contraintes énoncées ci-dessus. Cependant, cette structure de CAN reste sensible aux défauts d’appariement entre ses différentes voies de conversion et voit ses performances limitées par la présence de raies parasites liées à des erreurs statiques (offset et gain) et dynamiques (skew et bande passante). Pour réduire l’impact des erreurs dynamiques, nous avons implémenté une calibration mixte en technologie FD-SOI 28nm. Dans une première partie, un état de l’art portant sur les différentes techniques de minimisation et de compensations analogiques des erreurs de skew et bande passante est réalisé. A partir de cette étude, nous proposons différentes techniques analogiques pour compenser les d´esappariements de bande passante et de skew. Pour compenser le skew, nous profitons des avantages de la technologie FD-SOI en modulant fortement la tension de la face arrière d’un ou plusieurs transistor(s) d’ échantillonnage. Concernant l’erreur de bande passante, nous proposons d’ajuster la résistance équivalente du T/H en adaptant la résistance à l’état passant des transistors d’échantillonnage de cinq manières différentes. Pour définir parmi toutes les compensations proposées celle qui est la plus adaptée à nos besoins, nous comparons différents critères de performance. Après avoir identifié la meilleure compensation de skew et de bande passante, nous avons, dans une dernière partie, implémenté une calibration mixte des erreurs statiques et dynamiques o`u l’estimation numérique est basée sur la méthode des Moindres Carrés. / Data transmission requirements are ever more stringent, with respect to more throughput, less power consumption and reduced cost. The cable TV market is where broadband transceivers must continuously innovate to meet these requirements. In these transceivers, the analog front-end part must be adapted to meet the increasingly tighter specifications of the newest standards. A key bottleneck is the Analogto- Digital Converter (ADC), which must reach a sampling rate of several Gigasamples per second at effective conversion resolutions in the range of 10 to 14 bits. Among the possible choices, converters based on Time-Interleaving (TI-ADC) are experiencing remarkable growth, and today they appear to be the best candidates to rmeet the two constraints set out above. However, TI-ADCs are hampered by mismatches between its different conversion channels, which result in degraded performance due to the appearance of mismatch spurs in the frequency domain, arising both from static errors (gain and offset mismatch) and dynamic (skew and bandwidth) errors. To reduce these errors, we have investigated a mixeddomain calibration strategy for TI-ADCS in 28nm FDSOI technology. We strongly focused the analog compensation of dynamic errors. This report begins with a review of the state-of-theart w.r.t. the mismatch reduction and analog compensation techniques for both dynamic errors. Based on these results, we then introduce a variety of analog techniques aimed at compensating the bandwidth and skew mismatches. In order to compensate for the skew, we make the most of the FD-SOI technology by tightly regulating the voltage of the back gate of one or several sampling transistors. For the bandwidth error, we recommend that the T/H equivalent resistor be adjusted, adapting the on-resistor of the sampling transistors using up to five different techniques. Once the most appropriate skew and bandwidth compensations were identified, we ultimately implemented a mixed calibration of static and dynamic errors along with a digital calculation based upon the "Least- Squares" method.

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With the increasing number of wireless devices and the phenomenal amount of data that is being generated by them, there is a growing interest in the wireless communications community to complement the traditional model-driven design approaches with data-driven machine learning (ML)-based solutions. However, managing the large-scale multi-dimensional data to maintain the efficiency and scalability of the ML algorithms has obviously been a challenge. Tensors provide a useful framework to represent multi-dimensional data in an integrated manner by preserving relationships in data across different dimensions. This thesis studies two new applications of tensors to ML for wireless communications where the tensor structure of the concerned data is exploited in novel ways. The first contribution of this thesis is a tensor learning-based low-complexity precoder codebook design technique for a full-dimension multiple-input multiple-output (FD-MIMO) system with a uniform planar antenna (UPA) array at the transmitter (Tx) whose channel distribution is available through a dataset. Represented as a tensor, the FD-MIMO channel is further decomposed using a tensor decomposition technique to obtain an optimal precoder which is a function of Kronecker-Product (KP) of two low-dimensional precoders, each corresponding to the horizontal and vertical dimensions of the FD-MIMO channel. From the design perspective, we have made contributions in deriving a criterion for optimal product precoder codebooks using the obtained low-dimensional precoders. We show that this product codebook design problem is an unsupervised clustering problem on a Cartesian Product Grassmann Manifold (CPM), where the optimal cluster centroids form the desired codebook. We further simplify this clustering problem to a $K$-means algorithm on the low-dimensional factor Grassmann manifolds (GMs) of the CPM which correspond to the horizontal and vertical dimensions of the UPA, thus significantly reducing the complexity of precoder codebook construction when compared to the existing codebook learning techniques. The second contribution of this thesis is a tensor-based bandwidth-efficient gradient communication technique for federated learning (FL) with convolutional neural networks (CNNs). Concisely, FL is a decentralized ML approach that allows to jointly train an ML model at the server using the data generated by the distributed users coordinated by a server, by sharing only the local gradients with the server and not the raw data. Here, we focus on efficient compression and reconstruction of convolutional gradients at the users and the server, respectively. To reduce the gradient communication overhead, we compress the sparse gradients at the users to obtain their low-dimensional estimates using compressive sensing (CS)-based technique and transmit to the server for joint training of the CNN. We exploit a natural tensor structure offered by the convolutional gradients to demonstrate the correlation of a gradient element with its neighbors. We propose a novel prior for the convolutional gradients that captures the described spatial consistency along with its sparse nature in an appropriate way. We further propose a novel Bayesian reconstruction algorithm based on the Generalized Approximate Message Passing (GAMP) framework that exploits this prior information about the gradients. Through the numerical simulations, we demonstrate that the developed gradient reconstruction method improves the convergence of the CNN model. / Master of Science / The increase in the number of wireless and mobile devices have led to the generation of massive amounts of multi-modal data at the users in various real-world applications including wireless communications. This has led to an increasing interest in machine learning (ML)-based data-driven techniques for communication system design. The native setting of ML is {em centralized} where all the data is available on a single device. However, the distributed nature of the users and their data has also motivated the development of distributed ML techniques. Since the success of ML techniques is grounded in their data-based nature, there is a need to maintain the efficiency and scalability of the algorithms to manage the large-scale data. Tensors are multi-dimensional arrays that provide an integrated way of representing multi-modal data. Tensor algebra and tensor decompositions have enabled the extension of several classical ML techniques to tensors-based ML techniques in various application domains such as computer vision, data-mining, image processing, and wireless communications. Tensors-based ML techniques have shown to improve the performance of the ML models because of their ability to leverage the underlying structural information in the data. In this thesis, we present two new applications of tensors to ML for wireless applications and show how the tensor structure of the concerned data can be exploited and incorporated in different ways. The first contribution is a tensor learning-based precoder codebook design technique for full-dimension multiple-input multiple-output (FD-MIMO) systems where we develop a scheme for designing low-complexity product precoder codebooks by identifying and leveraging a tensor representation of the FD-MIMO channel. The second contribution is a tensor-based gradient communication scheme for a decentralized ML technique known as federated learning (FL) with convolutional neural networks (CNNs), where we design a novel bandwidth-efficient gradient compression-reconstruction algorithm that leverages a tensor structure of the convolutional gradients. The numerical simulations in both applications demonstrate that exploiting the underlying tensor structure in the data provides significant gains in their respective performance criteria.

Les circuits intégrés (CI) devenant de plus en plus complexes et vulnérables face aux décharges électrostatiques (ESD pour ElectroStatic Discharge), la capacité à vérifier de manière fiable la présence de défauts de conception ESD sur des puces comptant plusieurs milliards de transistors avant tout envoi en fabrication est devenu un enjeu majeur dans l’industrie des semi-conducteurs. Des outils commerciaux automatisés de dessin électronique (EDA pour Electronic Design Automation) et leur flot de vérification associé permettent d’effectuer différents types de contrôles qui se sont révélés être efficaces pour des circuits avec une architecture classique. Cependant, ils souffrent de limitations lorsqu’ils sont confrontés à des architectures inhabituelles, dites custom. De plus, ces méthodes de vérification sont généralement effectuées tard dans le flot de conception, rendant toute rectification de dessin coûteuse en termes d’efforts correctifs et de temps. Cette thèse de doctorat propose une méthodologie de vérification ESD systématique et multi-échelle introduite dans un outil appelé ESD IP Explorer qui a été spécifiquement implémenté pour couvrir le flot de conception dans sa globalité et pour adresser des circuits dits custom. Il est composé d’un module de reconnaissance et d’un module de vérification. Le module de reconnaissance identifie tout d’abord et de manière automatisée les structures de protection ESD, embarquées sur silicium dans le circuit intégré pour améliorer leur robustesse ESD, selon un mécanisme de reconnaissance topologique. Le module de vérification convertit ensuite le réseau de protection ESD, formé des structures de protection ESD, en un graphe dirigé. Finalement, une analyse ESD quasi-statique reposant sur des algorithmes génériques issus de la théorie des graphes est effectuée sur la globalité du circuit à vérifier. Des algorithmes d’apprentissage automatique ont été employés pour prédire les comportements quasi-statiques des protections ESD à partir des paramètres d’instance de leurs composants élémentaires sous la forme d’une liste d’interconnexions. L’avantage ici est qu’aucune simulation électrique n’est requise pendant toute la durée d’exécution d’ESD IP Explorer, ce qui simplifie l’architecture de l’outil et accélère l’analyse. Les efforts d’implémentation ont été concentrés sur la compatibilité d’ESD IP Explorer avec le nœud technologique 28nm FD-SOI (pour Fully Depleted Silicon On Insulator). L’outil de vérification développé a été utilisé avec succès pour l’analyse d’un circuit incorporant des parties numériques et à signaux mixtes et comprenant plus de 1,5 milliard de transistors en seulement quelques heures. Des circuits custom qui n’ont pas pu être vérifiés au moyen d’outils de vérification traditionnels du fait de problèmes d’incompatibilité ont également pu être soumis à analyse grâce à ESD IP Explorer. / As Integrated Circuits (ICs) become more complex and susceptible to ElectroStatic Discharges (ESD), the ability to reliably verify the presence of ESD design weaknesses over a multi-billion transistor chip prior to the tape-out is a major topic in the semiconductor industry. Commercial tools dedicated to Electronic Design Automation (EDA) and related verification flows are in charge of providing checks that have been proven to be efficient for circuits with a mainstream architecture. However, they suffer limitations when confronted with custom designs. Moreover, these verification methods are often run late in the design flow, making any design re-spin costly in terms of corrective efforts and time. This Ph. D. thesis proposes a systematic and scalable ESD verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. It is composed of a recognition module and a verification module. The recognition module first automatically identifies ESD protection structures, embedded in integrated circuits to enhance their ESD hardness, according to a topology-aware recognition mechanism. The verification module then converts the ESD protection network that is formed by ESD protection structures into a directed graph. There, technology-independent and graph-based verification mechanisms perform a chip-scale quasistatic ESD analysis. Machine learning algorithms have been used in order to infer the quasistatic behavior of ESD IPs from the netlist instance parameters of their primary devices. This approach has the advantage that no simulation is required during the execution of ESD IP Explorer, which makes the tool architecture simpler and improves execution times. Implementation efforts pertained to the compliance of ESD IP Explorer with the 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The developed verification tool has been used to successfully analyze a digital and mixed-signal circuit prototype counting more than 1.5 billion transistors in several hours, as well as custom designs that could not be analyzed by means of traditional verification tools due to incompatibility issues.

Afin de réaliser correctement leur fonction, certains blocs analogiques ou numériques comme les miroirs de courant ou les SRAM, nécessitent des paires de transistors MOS électriquement identiques. Cependant, les dispositifs sur silicium, même appariés, subissent des variations locales aléatoires ce qui fait varier leurs performances électriques. Ce phénomène est connu sous le nom désappariement. L'objectif de cette thèse est de comprendre les causes physiques de ce désappariement, de le quantifier et de proposer des solutions pour le réduire. Dans ce contexte, quatre thèmes principaux sont développés. Le premier thème se focalise sur l'optimisation des méthodologies de mesures des phénomènes de désappariement. Une nouvelle méthode de mesure du désappariement de Vt et de β ainsi qu'un nouveau modèle de désappariement de ID sont proposés, analysés et appliqués à des données mesurées sur des technologies 28nm Bulk et FD SOI. Le second thème se concentre sur la caractérisation des différentes configurations de transistor MOS afin de proposer l'architecture optimale en fonction des applications visées. Ainsi, la possibilité de remplacer le LDEMOS par une configuration cascode est analysée en détail. Le troisième thème se focalise sur l'analyse et la modélisation des phénomènes de désappariement des transistors MOS avancés. Trois aspects sont analysés : 1) l'introduction du Ge dans le canal P des technologies 28nm BULK, 2) la suppression de la contribution de la grille sur le désappariement de Vt en utilisant la technologie 20 nm métal-Gate-Last 3) un descriptif des principaux contributeurs au désappariement de Vt, β et ID dans les technologies 28 et 14nm FD SOI. Le dernier thème traite du comportement du désappariement des transistors MOS après vieillissement. Un vieillissement NBTI a été appliqué sur des PMOS de la technologie 28nm FD SOI. Des modèles de comportement de Vt et de β en fonction du nombre de charges fixes ou d'états d'interfaces induits à l'interface Si/SiO2 ou dans l'oxyde sont proposés et analysés. / For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed.

L'objectif principal de cette thèse est de proposer et d'évaluer une nouvelle architecture de Transistor Bipolaire à Héterojonction (TBH) Si/SiGe s’affranchissant des limitations de l'architecture conventionnelle DPSA-SEG (Double-Polysilicium Self-Aligned, Selective Epitaxial Growth) utilisée dans la technologie 55 nm Si/SiGe BiCMOS (BiCMOS055) de STMicroelectronics. Cette nouvelle architecture est conçue pour être compatible avec la technologie 28-nm FD-SOI (Fully Depleted Si-licon On Insulator), avec pour objectif d'atteindre la performance de 400 GHz de fT et 600 GHz de fMAX dans ce noeud. Pour atteindre cet objectif ambitieux, plusieurs études complémentaires ont été menées: 1/ l'exploration et la comparaison de différentes architectures de TBH SiGe, 2/ l'étalonnage TCAD en BiCMOS055, 3/ l'étude du budget thermique induit par la fabrication des technologies BiCMOS, et finalement 4/ l'étude d'une architecture innovante et son optimisation. Les procédés de fabrication ainsi que les modèles physiques (comprenant le rétrécissement de la bande interdite, la vitesse de saturation, la mobilité à fort champ, la recombinaison SRH, l'ionisation par impact, la résistance distribuée de l'émetteur, l'auto-échauffement ainsi que l’effet tunnel induit par piégeage des électrons), ont été étalonnés dans la technologie BiCMOS055. L'étude de l’impact du budget thermique sur les performances des TBH SiGe dans des noeuds CMOS avancés (jusqu’au 14 nm) montre que le fT maximum peut atteindre 370 GHz dans une prochaine génération où les profils verticaux du BiCMOS055 seraient ‘simplement’ adaptés à l’optimisation du budget thermique total. Enfin, l'architecture TBH SiGe EXBIC, prenant son nom d’une base extrinsèque épitaxiale isolée du collecteur, est choisie comme la candidate la plus prometteuse pour la prochaine génération de TBH dans une technologie BiCMOS FD-SOI dans un noeud 28 nm. L'optimisation en TCAD de cette architecture résulte en des performances électriques remarquables telles que 470 GHz fT et 870 GHz fMAX dans ce noeud technologique. / The ultimate objective of this thesis is to propose and evaluate a novel SiGe HBT architec-ture overcoming the limitation of the conventional Double-Polysilicon Self-Aligned (DPSA) archi-tecture using Selective Epitaxial Growth (SEG). This architecture is designed to be compatible with the 28-nm Fully Depleted (FD) Silicon On Insulator (SOI) CMOS with a purpose to reach the objec-tive of 400 GHz fT and 600 GHz fMAX performance in this node. In order to achieve this ambitious objective, several studies, including the exploration and comparison of different SiGe HBT architec-tures, 55-nm Si/SiGe BiCMOS TCAD calibration, Si/SiGe BiCMOS thermal budget study, investi-gating a novel architecture and its optimization, have been carried out. Both, the fabrication process and physical device models (incl. band gap narrowing, saturation velocity, high-field mobility, SRH recombination, impact ionization, distributed emitter resistance, self-heating and trap-assisted tunnel-ing, as well as band-to-band tunneling), have been calibrated in the 55-nm Si/SiGe BiCMOS tech-nology. Furthermore, investigations done on process thermal budget reduction show that a 370 GHz fT SiGe HBT can be achieved in 55nm assuming the modification of few process steps and the tuning of the bipolar vertical profile. Finally, the Fully Self-Aligned (FSA) SiGe HBT architecture using Selective Epitaxial Growth (SEG) and featuring an Epitaxial eXtrinsic Base Isolated from the Collector (EXBIC) is chosen as the most promising candidate for the 28-nm FD-SOI BiCMOS genera-tion. The optimization of this architecture results in interesting electrical performances such as 470 GHz fT and 870 GHz fMAX in this technology node.