Due to changes in health care, along with increasing technological demands, nurse's experiences increased stress. Nurses who are asked to staff another area other than their own have increased stress that can lead to increased nurse turnover, absences, and nursing dissatisfaction scores. The purpose of this quality improvement project was to assess whether limiting what units a nurse works on can reduce nurse stress, improve self-efficacy, and improve nurse job satisfaction. The design of this pilot placed like nursing units within a neighborhood staffing model for floating. The plan-do-check-act model was used as a framework to implement a change in the nurse floating practices. An electronic survey was sent to the nursing team pre and post implementation of the model. Nursing hours will also be tracked during this period of time. Data related to floating after the implementation of the neighborhood staffing model showed a significant increase in floating hours inside (13.1 vs 20.9; t=3.98, p<.001), and there was a significant decrease in hours floated outside the neighborhood (26.3 vs 18.0; t=5.15, p<.000). Self-efficacy results showed an initial decline in the nurses' self-efficacy 4 weeks after the launch and a statistically significant increase over preimplementation levels at 8 weeks (pre 28.46; post 33.51; U=5003, p<.001); on the 3rd administration of the self-efficacy survey, a statistically significant increase was seen (28.5 vs. 33.5; t=12.1, p<.001). Allowing nurses to float to similar nursing areas will result in improved self-efficacy, a precursor to reduced job stress and increased job satisfaction, which represents a positive contribution to social change for the nurses who work in the hospital system.

A method of synthesizing and controlling the size of germanium nanocrystals is developed. A tri-layer metal-insulator-semiconductor (MIS) memory device structure comprising of a thin (~5nm) silicon dioxide (SiO₂) layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO₂ of varying thickness (3 - 6 nm) deposited using a radio frequency (rf) co-sputtering technique, and a capping SiO₂ layer (50nm) deposited using rf sputtering is investigated. It was verified that the size of germanium (Ge) nanocrystals in the vertical z-direction in the trilayer memory device was controlled by varying the thickness of the middle (cosputtered Ge+SiO₂) layer. From analyses using transmission electron microscopy and capacitance-voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix. / Singapore-MIT Alliance (SMA)

The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulator-semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO₂ co-sputtered middle layer (i.e., lower Ge concentration), a higher charge storage capability was obtained than with devices with a thinner RTO layer, and the charge retention time was found to be less than in devices with a thicker RTO layer. / Singapore-MIT Alliance (SMA)

In this thesis, the traditional fixed-point CORDIC algorithm is extended to floating-point version in order to calculate transcendental functions (such as sine/cosine, logarithm, powering function, etc.) with high accuracy and large range. Based on different algorithm derivations, two different floating-point high-throughput pipelined CORDIC architectures are proposed. The first architecture adopts barrel shifters to implement the shift operations in each pipelined stage. The second architecture uses pure hardwired method for the shifting operations. Another key contribution of this thesis is to analyze the execution errors in the floating-point CORDIC architectures and make comparison with the execution resulting from pure software programs. Finally, the thesis applies the floating-point CORDIC to realizing the rotation-related operations required in 3D graphics applications.

我國動產擔保交易法之制訂，曾被亞洲發展銀行之亞洲擔保交易法律改革譽為大陸法系移植英美法系制度之典範。然而，世界銀行近年發布之「經商環境評比（Doing Business）」，有關「獲得貸款（Getting credit）」項下「法定權利指數(Legal Rights」的項目，依據該行2008年發布「2009年經商環境報告」，我國在181個經濟體中排名第68名，2010年在183個經濟體中排名第71名，2011年則排名第72名，排名表現並不佳，其中我國無英美法系相當普遍之浮動擔保制度（floating lien），為未能得分重要原因之一。事涉我國國際形象，此項評比引起行政院經濟建設委員會、行政院金融監督管理委員會等政府相關單位之重視，並就我國可否建立類似制度以利經商環境之發展，在國內進行一連串的法制研議及研商會議。 我國動產擔保交易法係參考英美法而制定，草擬時，美國統一商法典已經研擬完成，將過去九種商事統一法案全部納入，有關擔保交易的規定在第九章，以「擔保利益（security interest）」為中心，打破舊有各種擔保制度間的藩籬。但我國立法之時，可能是因應大陸法系的物權概念，仍採行動產抵押、附條件買買及信託占有三種動產擔保交易制度，將共同之原則列為總則，再各列一章，以利執行。然而，即使我國的動產擔保交易法是繼受英法的法制，並無浮動擔保之法制。 浮動擔保制度（floating lien）為英國衡平法發展100多年之產物，起初是律師們的設計經法院判決承認的制度，爾後英國的公司法將相關內容成文化。其特色在於發生確定事由前，擔保標的物處於不確定之狀態，亦即債務人可任意處分及更換擔保品，於債務人違約時，債權人可透過接管人接管標的物予以經營或進行處分，而獲得清償，且多用於擔保企業發行公司債之擔保。英國及美國係在公示制度及接管制度配合下，發展浮動擔保制度。 觀諸國內近二年召開的研商會議及相關立論，學者對於是否引進浮動擔保未有共識，然皆認同動產擔保交易公示平台統一及拍賣法立法為引進浮動擔保制度之重要前提要件。由於國內對於浮動擔保甚為陌生，學界對此議題之研究及相關文獻本不多，但欣見於本文研究之同時，行政院經濟建設委員會、銀行公會紛紛委託專家學者進行研究，使得學者對此議題加以關注，並得以提出創見。世界銀行2012年對我國Getting Credit指標的評比也在行政院金融監督管理委員會的努力下提升至67名。 本文探討如何在營造健全融資環境、擴大動產經濟效益，並兼顧產業融資需求與動產擔保交易安全，引進浮動擔保制度。本文先就浮動擔保之基本概念介紹，除介紹浮動擔保濫觴之英美法制，亦比較日本及中國大陸引進該法制之情形，得一基本概況，再就行政院金融監督管理委員會曾提出之草案分析說明，最後就我國法制環境引進此種制度提出建議架構及相關內容。

Det moderna informationssamhället har medfört en ökning av upplevd stress. Avslappningsmetoder används som ett sätt att motverka hög anspänning. En relativt ny företeelse utgör floating, där man flyter i saltkoncentrerat vatten inuti en stimulireducerad flyttank. Forskning har påvisat gynnsamma effekter av floatingutövande. Syftet i denna studie var att undersöka individers upplevelser av att ligga i en flyttank. Sex halvstrukturerade intervjuer gjordes med floatingutövare som flyter med varierande grad av sensorisk restriktion. Tematisk analys användes i databearbetningen. Resultaten visade att floating upplevdes som behagligt och avslappnande. Stora skillnader förelåg dock mellan individer i flera aspekter av floatingupplevelsen. Graden av sensorisk reducering i flyttanken tycktes påverka typen av erfarenheter. Ovanliga upplevelser var endast förekommande vid floating med strikt stimulireduktion. Ett vetenskapsteoretiskt resonemang förs kring synen på ovanliga upplevelser. Floatingens användbarhet som terapeutiskt verktyg diskuteras och vidare forskning kring floating och terapi rekommenderas.

Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology having many unique characteristics is one of the most hopeful methods in the direction. As semiconductor memory is concerned, The 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMOSFET, that can allow DRAM cell to be scaled down in depth with less area occupied .In this paper, we will propose a new structure of 1T-DRAM cell, which has the buried oxide and block oxide around its body. It can suppress the junction capacitor between the S/D and the body of the cell. In addition it can also improve the programming window of the 1T-DRAM cell more than 80% by utilizing its own structural characteristic. We fabricated our new device in National Nano Device Laboratories. The device was carried out by depositing oxide and poly film on bulk Si wafer, just like TFT process. But doing by this way it has some issues about the polycrystalline channel and the S/D. Although it has some issues, but we made it successful using bulk Si wafer rather than expensive SOI wafer. It indeed reduces the cost of process.

In the present study, a two-dimensional numerical model based on a time-independent finite difference method was developed and the model is used to analysis the dynamic interaction among wave, sloshing fluid in tank and the floating tank. The free surface of wave and sloshing fluid in the tank are all assumed to be a single value function and the wave breaking is, therefore, not considered in the study. The numerical model is firstly validated by some bench make studies. Extensive simulation were made to discuss the effects of geometry of the floating tank, the ratio of depth to breadth of fluid in tank, the fundamental freq of floating tank ¡V structure system etc.

In this paper, we propose a novel thin film MOSFET with source/drain tie and discontinuously block oxide layers. Improving process is very important, when the gate length of SOI MOSFET is reduced. To overcome the misalignment problem, we use self-aligned technology to fabricate this device. In addition, the device has discontinuously block oxide layers; they can improve short channel effects, reduce the parasitic capacitance, and decrease the leakage current cause by P-N junction between source/drain and body regions. They also supply two pass ways to eliminate carriers and heat which generated by impact ionization resulting in suppression of floating-body effect and self-heating effect. In addition, these two pass ways can be seen as the parallel equivalent resistance results in a reduced series resistance and an increased drain saturation current. According to the ISE TCAD 10.0 simulation results, the discontinuously block oxide layers can not only improve the short channel effects, but also eliminate the floating-body effect and diminish the self-heating effect because of the pass ways.

This thesis presents a new simulation model for floating gate transistor (FGMOS) in nanometer scale technology where the transistors suffer from non-negligible gate leakage current due to the very thin Silicon oxide (SiO2) layer. The new FGMOS simulation model is used for transient and DC simulation and with any industry standard simulators such as Spector and various SPICE programs (i.e. HSPICE, WinSPICE, etc.). This model can be used for any technology that has SiO2 thickness less than 3nm and suffer from gate leakage current with no changes to the model itself; however, minimal changes need to be done to the gate tunnelling cell to comply with the technology parameters where the gate tunnelling current exponentially increases as tox decreases.