Mitrionics is a company based in Lund, Sweden. They develop a platform for FPGA-based acceleration, the platform includes a virtual processor, the Mitrion Virtual Processor, that can be custom built to fit the application that is to be accelerated. The purpose of this thesis is to investigate the possible benefits of using a centralized scheduler for the Mitrion Virtual Processor instead of the current solution which is a distributed scheduler. A centralized scheduler has been implemented and evaluated using a set of benchmark applications. It has been found that the centralized scheduler can decrease the number of registers used to implement the Mitrion Virtual Processor on an FPGA. The size of the decrease depends on the application, and certain applications are more suitable than others. It has also been found that the introduction of a centralized scheduler makes it more difficult for the place and route tool to fit a design on the FPGA resulting in failed timing constraints for the largest benchmark application. / Mitrionics är ett företag i Lund. De utvecklar en platform för FPGA-baserad acceleration av applikationer. Platformen innehåller bland annat en virtuell processor, Mitrion Virtual Processor, vilken kan specialanpassas till applikationen som ska accelereras. Syftet med detta arbete är att implementera en centraliserad schedulerare för Mitrion Virtual Processor och utvärdera vilka möjliga fördelar det kan finnas jämfört med att använda den nuvarande lösningen vilket är en distribuerad skedulerare. En centraliserad skedulerare har implementerats och utvärderas genom att avända en uppsättning testapplikationer. Det har funnits att användandet av en centraliserad skedulerare kan minska antalet register som behövs för att implementera Mitrion Virtual Processor på en FPGA. Vidare har det funnits att storleken på minskningen beror på applikationen och att vissa applikationer lämpar sig bättre än andra. Det har även visat sig att processen att placera logik på FPGAn blir svårare om man använder en centraliserad skedulerare, detta har resulterat i att vissa timing krav inte har mötts när den största testapplikation har syntetiserats.

Actiwave AB delivers audio solutions for active speakers. One of the features is that audio can be streamed to the speakers over a local network connection. The module that provides this functionality is expensive. This thesis investigates if this can instead be achieved by taking advantage of the Spartan-6 FPGA on their platform, using part of it as a MicroBlaze soft processor on which a rendering device can be implemented. The thesis discusses design decisions such as selection and integration of operating system, UPnP framework and media decoder. A fully functional prototype application for a desktop computer was implemented, with the intention of porting it to the FPGA platform. There turned out to be too many compability issues though, so instead, a simpler renderer was implemented on the FPGA. Mp3 music files were successfully streamed to and decoded on the soft processor, but without fulfilling real-time constraints. The conclusion is that it is reasonable to implement a UPnP Media Renderer on the FPGA. Decoding in real-time can be an issue due to insufficient performance of the soft processor, but several possible solutions exist.

Road conditions are a critical issue for road users as, if not given sufficient attention, they may threaten users’ lives. The environmental parameters, such as snowy, icy, dry and wet, are important in relation to the condition of roads. This is particularly true in relation to the northern regions and greatest concern should be in relation to snowy and icy situations. In this thesis, a system based on an InGaAs area scan sensor utilizes NIR technology to detect water or ice on the road so as to enable drivers to avoid slippery road conditions. The conditions caused by freezing water on road surface are particularly dangerous and are not easy to observe and it is hope that this project will boost traffic safety. The system is able to assist road maintenance personnel in forecasting and detecting slippery road conditions during winter road maintenance (WRM). The system, which is based on FPGA, has functionalities that display the captured images on an HDMI monitor and send the images to the software on a host PC via the UART protocol. An interface board, which carries the sensor and which connects to the FPGA board, is developed for NIR sensor. VHDL implementation and PC software design are the works included in the project. Besides, this device is exploited utilizing InGaAs image sensor. According to its features, it can be applied in other applications which will also be discussed. Finally, experiments are conducted in order to investigate the system’s operation with the variation of temperature.

With today’s FPGA’s it’s possible to implement complete systems in a single FPGA. With help of Soft Processor Cores like the MicroBlaze processor several microcontrollers can be implemented in the same FPGA. The third generation telecommunications system, cdma2000, has several channels, which has specific assignments. The Sync channel purpose is to attain initial time synchronization. The purpose with this thesis has been to implement the Sync channel in a FPGA with use of a MicroBlaze processor. An evaluation of the concept of using a Soft Processor Core instead of ordinary DSP’s and microcontrollers would then be conducted. This thesis has resulted in a system with a MicroBlaze processor that has the Sync channel as a peripheral. It’s possible to write information via HyperTerminal to the MicroBlaze processor which then uses this data as input to the Sync channel. The Sync channel then modulates the data according to the cdma2000 specifications and then outputs it onto an external pin at the FPGA. The evaluation of this concept hasn’t resulted in a general recommendation whether to use ASIC or FPGA’s in a system. The concept of using Soft Processor Cores certainly has its benefits and is something that could be thought of in the future when designing a system.

The fast growth of wireless local area networks today has opened up a whole new market for wireless solutions. Released in 1999, the IEEE 802.11a is a standard for high-speed wireless data transfer that much of modern Wireless Local Area Network technology is based on. This project has been about implementing the transmitter part of the 802.11a physical layer in VHDL to run on the Altera Stratix II FPGA. Special consideration was taken to divide the system into parts based on sample rate. This report contains a brief introduction to Orthogonal Frequency Division Multiplexing and to the IEEE 802.11a physical layer as well as a description of the implemented system.

The IEEE 802.15.4 standard defines the implementation of a Low-Rate Wireless Personal Area Network (WPAN). While the current version of the standard was ratified in 2006, there is still no readily available Medium Access Control (MAC) layer and/or Physical (PHY) layer for Altera Field Programmable Gate Arrays (FPGAs) in the public domain. This research investigates the implementation of the standard using an Altera FPGA for the MAC layer and PHY layer drivers. The Freescale MC13192 transceiver was used for the physical portion of the PHY layer, which includes the RF front end of the system. The purpose of this research was to implement a basic full function device (FFD), which is capable of acting as a node in the network, as well as co-ordinating it. This allows a simple network to be tested by loading the same code on two FPGA boards, with one configured to act as a coordinator and the other as a device. The flexibility of the standard means that there are several implementation choices to be made, each of which limits the compatibility with devices using other implementation options. The implementation and design decisions made in producing a preliminary core are described in detail. The implementation of the MAC layer primitives is discussed at length as these were not available as source code. These primitives are the building blocks for the core functions of the system. Specifically, the functionality of the Energy Detection (ED) scan, stream transmit and stream receive functions are explored in detail. The code has been implemented using C and is run on the Altera Nios II soft-core processor. The work presented here is an initial implementation meant to serve as a foundation for further research. Additional functionality defined by the standard could be added, or optimization of individual functions could be explored. The current implementation also has the potential to serve as the foundation for research into various sensors which may be part of end devices in the network.

The use of two dimensional (2D) digital filters for real-time 2D data processing has found important practical applications in many areas, such as aerial surveillance, satellite imaging and pattern recognition. In the case of military operations, real-time image pro-cessing is extensively used in target acquisition and tracking, automatic target recognition and identi cation, and guidance of autonomous robots. Furthermore, equal opportunities exist in civil industries such as vacuum cleaner path recognition and mapping and car collision detection and avoidance. Many of these applications require dedicated hardware for signal processing. It is not efficient to implement 2D digital filters using a single processor for real-time applications due to the large amount of data. A multiprocessor implementation can be used in order to reduce processing time. Previous work explored several realizations of 2D denominator separable digital filters with minimal throughput delay by utilizing parallel processors. It was shown that regardless of the order of the filter, a throughput delay of one adder and one multiplier can be achieved. The proposed realizations have high regularity due to the nature of the processors. In this thesis, all four realizations are implemented in a Field Programming Gate Array (FPGA) with floating point adders, multipliers and shift registers. The implementation details and design trade-offs are discussed. Simulation results in terms of performance, area and power are compared. From the experimental results, realization four is the ideal candidate for implementation on an Application Specific Integrated Circuit (ASIC) since it has the best performance, dissipates the lowest power, and uses the least amount of logic when compared to other realizations of the same filter size. For a filter size of 5 by 5, realization four can produce a throughput of 16.3 million pixels per second, which is comparable to realization one and about 34% increase in performance compared to realization one and two. For the given filter size, realization four dissipates the same amount of dynamic power as realization one, and roughly 54% less than realization three and 140% less than realization two. Furthermore, area reduction can be applied by converting floating point algorithms to fixed point algorithms. Alternatively, the denormalization and normalization stage of the floating point pipeline can be eliminated and fused together in order to save hardware resources.

In February 2002, the FCC (2002 a, b) issued a ruling that ultra-wideband (UWB) could be used for data communications as well as for radar and safety applications. UWB system is constrained to have a maximum power transmission of -41 dBm and a bandwidth ranging from 3.1-10.6 GHz. UWB co-exists and does not interfere with the existing narrowband or wideband communication systems in the same spectrum. However, due to its low power in the same bandwidth, UWB is affected by the so-called narrowband (NB) interference. This thesis presents a method to estimate and detect narrowband signals in radio impulse receiver with the intention to eliminate the NB interference. <p>Narrowband bandwidth is very small compared to the bandwidth of UWB therefore the interference can be considered as a single tone. To detect such a tone using conventional techniques is not feasible at least up to this time for UWB as current technology can not support such high data rates. Alternatives way to track down the narrowband signal include using a power spectral density estimation technique called spectrogram. For all cases, the spectrogram at specific frequency range where the narrowband active statistically be larger than its overall average power. Here, a threshold detector is built which reports detection at the frequency range where the narrowband is located if the spectrogram exceeds a threshold value. <p>Upon completing of successful NB detection, the NB signal in the UWB system will be estimated in digital form and cancelled in analog form. The pipelined LMS algorithm is used to estimate the NB signal; the algorithm is implemented using a built-in IP core from the Altera DSP library which can be simulated in either Matlab platform or in FPGA boards. The design correctness has been validated by means of Monte-Carlo simulation and hardware implementation using standard UWB IEEE standard channel models, Time Hopping-Pulse Position Modulation and the rake receiver technique.

Majority of the modern day compute intensive applications are heterogeneous in nature. To support their ever increasing computational requirements, present day System-on-Chip (SoC) architectures have adapted multicore style of modeling, thereby incorporating multiple, heterogeneous processing cores on a single chip. The emerging Network-On-Chip (NoC) interconnect paradigm provides a scalable and power-efficient solution for communication among multiple cores, serving as a powerful replacement for traditional bus based architectures. A fast, robust and exible emulation platform is the key to successful realization and validation of such architectures within a very short span of time. This research focuses on various aspects of Hardware/Software (HW/SW) codesign for AcENoCs (Accelerated Emulation Platform for NoCs), a Field Programmable Gate Array (FPGA) accelerated, con gurable, cycle accurate platform for emulation and validation of NoC architectures. This work also details the design, implementation and evaluation of AcENoCs' software framework along with the various design optimizations carried out and tradeoffs considered in AcENoCs' HW/SW codesign for achieving an optimum balance between emulated network dimensions and emulation performance. AcENoCs emulation platform is realized on a Xilinx Virtex-5 FPGA. AcENoCs' hardware framework consists of the NoC built using configurable hardware library components, while the software framework consists of Traffic Generators (TGs) and their associated source queues, Traffic Receptors (TRs) along with statistics analysis module and dynamically controlled emulation clock generator. The software framework is implemented using on-chip Xilinx MicroBlaze processor. This report also describes the interaction between various HW/SW events in an emulation cycle and assesses AcENoCs' performance speedup and tradeoffs over existing FPGA emulators and software simulators. FPGA synthesis results showed that networks with dimensions upto 5x5 could be accommodated inside the device. Varying synthetic traffic workloads, generated by TGs, were used to evaluate the network. Real application based traces were also run on AcENoCs platform to evaluate the performance improvement achieved in comparison to software simulators. For improving the emulator performance, software profiling was carried out to identify and optimize the software components consuming highest number of processor cycles in an emulation cycle. Emulation testcases were run and latency values recorded for varying traffic patterns in order to evaluate AcENoCs platform. Experimental results showed emulation speedups in order of 10000-12000X over HDL (Hardware Description Language) simulators and 14-47X over software simulators, without sacri cing cycle accuracy.

This master thesis report covers an investigation of how FPGA based hardware can be used to create customizable measurement instruments, for test of electrical equipment in JAS 39 Gripen. The investigation is done at Saab Support and Services in Arboga. Electrical equipment are gradually replacing functions, which previously have been obtained by other systems, in safety critical environments. Since the functions are safety critical, they require regular testing in order to verify proper operation. The aircraft JAS 39 Gripen, which is manufactured and developed by Saab, is an example of such system. Proper operation of the avionics in it are essential in order to maintain flying safety. There already exist systems today that can verify the functionality of electronics in JAS 39 Gripen. However, there are a number of scenarios where those test systems are somewhat inflexible. More flexible test systems are often desired. This flexibility can be obtained by using congurable hardware, suggestively with FPGAs. This approach is investigated in this master thesis.