The Large Hadron Collider (LHC) at the CERN laboratory was designed to study the elementary particles and forces and search for new physics.  Detectors at LHC were designed to observe proton-proton collisions with center of mass energies up to 14 TeV, seven times higher than previously possible. One of the largest of these is the general purpose detector ATLAS. After almost 20 years of planning and construction, LHC and its detectors were finished in 2008. Since then ATLAS has produced valuable data, which contributed to the discovery of the 1964 postulated Higgs-particle and thus to the Nobel prize in physics in 2013. To expand the searches, LHC and its detectors will undergo several upgrades to the increase luminosity at least by a factor of 5 and to exploit the full potential of the machine. In order to adapt the detector to the resulting increasing event rates and radiation levels, new electronics have to be developed. This thesis describes the development process of a new upgraded digital readout system for one of the sub-detectors in ATLAS, the scintillating Tile Calorimeter (TileCal), and more specifically one of its key components, the high-speed data link DaughterBoard. Starting from the idea of transferring all recorded information of the detector using high speed serial optical links and the concept of using re-programmable logic for the readout electronics, completely new on-detector electronics were designed to be used as a core component for communication, control and monitoring. The electronics was tested, electrical characterized and proven to work in a setup similar to the upgraded readout electronics. The DaughterBoard is the Stockholm University contribution to the ATLAS upgrade in 2023.

Hardware Trojan Horses (HTHs or Trojans) are malicious design modifications intended to cause the design to function incorrectly. Globalization of the IC development industry has created new opportunities for rogue agents to compromise a design in such a way. Offshore foundries cannot always be trusted, and the use of trusted foundries is not always practical or economical. There is a pressing need for a method to reliably detect these Trojans, to prevent compromised designs from being put into production. This thesis proposes a multi-parameter analysis method that is capable of reliably detecting function-altering and performance-degrading Trojans in FPGA bitstreams. It is largely autonomous, able to perform functional verification and power analysis of a design with minimal user interaction. On-the-fly test vector generation and verification reduces the overhead of test creation by removing the need to pre-generate and verify test vector sets. We implemented the method on a testbed constructed from COTS components, and tested it using a red-team/blue-team approach. The system was effective at detecting performance-degrading and function-altering embedded within combinational or sequential designs. The method was submitted for consideration in the 2012 Embedded Systems Challenge, which served to independently verify our results and evaluate the method; it was awarded first place in the competition.

This thesis discusses certain aspects of the noninvasive imaging technique known as optical coherence tomography (OCT). Topics include three-dimensional image rendering as well as application of the Fast Fourier Transform to reconstruct the axial scan as a function of depth. Implementations use LabVIEW system design software and a Xilinx Spartan-6 field-programmable gate array (FPGA). The inherent parallel-processing capability of an FPGA opens the possibility of designing a "super-sensor" which entails simultaneous capturing of image and sensor data, giving medical practitioners more data for potentially improved diagnosis. FPGA-based processing would benefit many methods of characterizing biological samples; OCT and photonic crystal microarray biosensors are discussed. / text

Video surveillance systems have been popular as a security tool for years, and the technological development helps monitoring accident-prone areas with the help of digital image processing.A thermal and a visual camera are being used in the surveillance project. The thermal camera is sensitive to the heat emitted by objects, and it is essential to employ the thermal camera as the visual camera is only useful in the presence of light. These cameras do not provide images of the same resolution. In order to extract the region of interest (ROI) of the visual camera, the images of these cameras need to have the same resolution; therefore the thermal images are processed in order to have the same size as the visual image.The ROI extraction is needed in order to reduce the data that needs to be transmitted. The region of interest is extracted from the visual image and the required processes are mostly done on the thermal image as it has lower resolution and therefore requires less computational processing. The image taken from the thermal camera is up scaled by using the nearest neighbor algorithm and it is zero-padded to make the resolutions of the two images equal, and then the region of interest is extracted by masking the result with the related converted version of visual image to YCbCr color space.

Architectural research for Field-Programmable Gate Arrays (FPGAs) tends to use an experimental approach. The benchmark circuits are used not only to compare different architectures, but also to ensure that the FPGA is sufficiently flexible to implement the desired variety of circuits. The most common benchmark circuits used for architectural research are circuits from the Microelectronics Center of North Carolina (MCNC). These circuits are small; they occupy less than 3% [5] of the largest available commercial FPGA. Moreover, these circuits are more representative of the glue logic circuits that were targets of early devices. This contrasts with the trend towards implementing Systems on Chip (SoCs) on FPGAs where several functional modules are integrated into a single circuit which is mapped onto one device. In this thesis, we develop a synthetic system-level circuit generator that connects pre-existing circuits in a realistic manner to build large netlists that share the characteristics of real SoC circuits. This generator is based on a survey of contemporary circuit designs from industrial and academic sources. We demonstrate that these system-level circuits scale well and that their post-routing characteristics match the results of large pre-existing benchmarks better than the results of circuits from previous synthetic generators.

In this paper it is described a method of creation of a neuroprocessor prototype, from high abstraction level to FPGA technology. Most common neuroprocessor architectures are overviewed, and canonical model of the neuroprocessor is created accordingly. Based on the canonical model the serial structure neuroprocessor mathematical model is formed and evaluated. The model is than described in SystemC programming language. In the experimental part, the correct functionality of the neuroprocessor is evaluated and the results of synthesis are analyzed.

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This thesis develops a hardware circuit implementation of a novel algorithm for reducing a SRM drives input current ripple or equivalently to improve the SRM drives input power quality. The algorithm requires the SRMs phase current to follow a trapezoidal trajectory relative to the rotors position with the magnitude of the current dependent on the desired average torque. This thesis deals with the generation of the required current command that is the input to a separate analog current regulator that forces the SRMs current to follow the generated current command. The final circuit design must be capable of operating at 200C to be part of a high temperature aircraft actuator. In this thesis, room temperature hardware is used to emulate and verify the high temperature design. Both a high temperature microcontroller based design and a high temperature gate array based design are considered with the high temperature gate array based design being chosen. Ultimately, a standard room temperature Xilinx FPGA is chosen to emulate the high temperature gate array. The FPGA is programmed using Verilog HDL and the code is downloaded into the chip using Xilinx ISE software. The experimentally generated output is validated by comparing it with simulation results from a detailed Simulink model of the complete drive system.

This thesis is devoted to the investigation of prioritization mechanism for web based anomaly detection. We propose a hardware realization of parallel binary heap as an application of web based anomaly prioritization. The heap is implemented in pipelined fashion in FPGA platform. The propose design takes O(1) time for all operations by ensuring minimum waiting time between two consecutive operations. We present the various design issues and hardware complexity. We explicitly analyze the design trade-offs of the proposed priority queue implementations.

Les codes correcteurs d'erreurs LDPC (Low Density Parity Check) font partie des codes en bloc permettant de s'approcher de quelques fractions de dB de la limite de Shannon. Ces remarquables performances associeés à leur relative simplicité de décodage rendent ces codes très attractifs pour les prochaines générations de systèmes de transmissions numériques. C'est notamment déjà le cas dans la norme de télédiffusion numérique par satellite (DVB-S2) qui utilise un code LDPC irrégulier pour la protection de la transmission des données descendantes. Dans cette thèse, nous nous sommes intéressés aux algorithmes de décodage des codes LDPC et à leur implantation matérielle. Nous avons tout d'abord proposé un algorithme sous-optimal de décodage (l'algorithme lambda-min) permettant de réduire de façon significative la complexité du décodeur sans perte de performances par rapport à l'algorithme de référence dit propagation de croyance (algorithme BP). Nous avons ensuite étudié et conçu une architecture générique de décodeur LDPC,que nous avons implantée sur une plateforme dédiée à base de circuits logiques programmables FPGA. Ce décodeur matériel permet avant tout d'accélérer les simulations d'un facteur supérieur à 500 par rapport à une simulation logicielle. De plus, par sa conception entièrement programmable, modulaire et générique, il possède de nombreuses fonctionnalités: Il peut ainsi être configuré pour une large classe de codes, et en conséquence permettre la recherche de codes efficaces