This master thesis report is a part of the thesis project conducted by Jakob Uhlin at Syntronic R R and D, Stockholm Sweden. The objective of this thesis is to develop a way to process the signal being sent on a CAN-bus and subsequently analyse its quality and its source in the network. A process of gathering appropriate theories and data has been done, parallel with the development of the analyzer module. The intelligence is implemented in an FPGA through the hardware description language VHDL. In this way, the algorithms can process the data in a real-time domain. The central findings and conclusions have been that is possible to analyze the signal quality of a CAN message properly on a FPGA.

Real-time tracking and object recognition is a large field with many possible applications. In this thesis we present a technical demo of a stereoscopic tracking system using artificial neural networks (ANN) and also an overview of the entire system, and its core functions. We have implemented a system able of tracking an object in real time at 60 frames per second. Using stereo matching we can extract the object coordinates in each camera, and calculate a distance estimate from the cameras to the object. The system is developed around the Xilinx ZC-706 evaluation board featuring a Zynq XC7Z045 SoC. Performance critical functions are implemented in the FPGA fabric. A dual-core ARM processor, integrated on the chip, is used for support and communication with an external PC. The system runs at moderate clock speeds to decrease power consumption and provide headroom for higher resolutions. A toolbox has been developed for prototyping and the aim has been to run the system with a one-push-button approach. The system can be taught to track any kind of object using an eight bit 32 × 16 pixel pattern generated by the user. The system is controlled over Ethernet from a regular workstation PC, which enables it to be very user-friendly.

The McTronX research group of the North–West University has over some years established a knowledge base in active magnetic bearing (AMB) systems. In 2009, an AMB system that met industrial standards in being robust, reliable and economical was developed by the research group. The digital control of the AMB system was implemented with the use of a dedicated single–board computer and communication hardware that interface with the motor drive electronics, power amplifiers and sensor drive units of the AMB system. A Xilinx® field programmable gate array (FPGA), connected to the single–board computer, was used to control the AMB system. The AMB system was designed to be used in a helium blower application and to form a basis for AMB and digital control research. A programmable logic controller (PLC) is connected to the controller to operate the AMB system. To establish communication between the PLC and the FPGA, the Fieldbus standard PROFIBUS DP was chosen as being a robust industrial standard communication protocol. To reduce the cost of the entire system, the need arose to implement the PROFIBUS DP protocol on the current FPGA of the system. This project involves the research, design, implementation, verification and validation of the PROFIBUS DP protocol on a Xilinx® Virtex©–5 FPGA. The PROFIBUS DP standard was researched, analyzed and developed in VHDL for the specific Xilinx® Virtex©–5 FPGA. The implemented protocol is used to establish a standardized PROFIBUS DP network between the PLC and the FPGA controller. Through simulation the basic protocol was tested and later implemented in the real–time environment. Intensive verification and validation was done to ensure that the developed protocol conforms to the robust PROFIBUS DP standard and simultaneously meet the requirements and specifications of the AMB control system. This dissertation documents the entire PROFIBUS implementation process, from standard analysis through to verification and validation of the developed protocol. In conclusion, the developed protocol is compared against a commercial off–the–shelf PROFIBUS PMC module. It was found that the VHDL–based PROFIBUS DP protocol not only competes well with the commercial PROFIBUS device, but also outperforms the device in various aspects. / Thesis (M.Ing. (Computer and Electronical Engineering))--North-West University, Potchefstroom Campus, 2011.

The McTronX research group of the North–West University has over some years established a knowledge base in active magnetic bearing (AMB) systems. In 2009, an AMB system that met industrial standards in being robust, reliable and economical was developed by the research group. The digital control of the AMB system was implemented with the use of a dedicated single–board computer and communication hardware that interface with the motor drive electronics, power amplifiers and sensor drive units of the AMB system. A Xilinx® field programmable gate array (FPGA), connected to the single–board computer, was used to control the AMB system. The AMB system was designed to be used in a helium blower application and to form a basis for AMB and digital control research. A programmable logic controller (PLC) is connected to the controller to operate the AMB system. To establish communication between the PLC and the FPGA, the Fieldbus standard PROFIBUS DP was chosen as being a robust industrial standard communication protocol. To reduce the cost of the entire system, the need arose to implement the PROFIBUS DP protocol on the current FPGA of the system. This project involves the research, design, implementation, verification and validation of the PROFIBUS DP protocol on a Xilinx® Virtex©–5 FPGA. The PROFIBUS DP standard was researched, analyzed and developed in VHDL for the specific Xilinx® Virtex©–5 FPGA. The implemented protocol is used to establish a standardized PROFIBUS DP network between the PLC and the FPGA controller. Through simulation the basic protocol was tested and later implemented in the real–time environment. Intensive verification and validation was done to ensure that the developed protocol conforms to the robust PROFIBUS DP standard and simultaneously meet the requirements and specifications of the AMB control system. This dissertation documents the entire PROFIBUS implementation process, from standard analysis through to verification and validation of the developed protocol. In conclusion, the developed protocol is compared against a commercial off–the–shelf PROFIBUS PMC module. It was found that the VHDL–based PROFIBUS DP protocol not only competes well with the commercial PROFIBUS device, but also outperforms the device in various aspects. / Thesis (M.Ing. (Computer and Electronical Engineering))--North-West University, Potchefstroom Campus, 2011.

The goal of this research is to present a framework to accelerate the execution of software legacy systems without having to redesign them or limit future changes. The speedup is accomplished through hardware acceleration, based on a semi-automatic infrastructure which supports design decisions and simulate their impact. Many programs are available for translating code written in C into VHDL (Very High Speed Integrated Circuit Hardware Description Language). What is missing is simpler and more direct strategies to incorporate encapsulatable portions of the code, translate them to VHDL and to allow the VHDL code and the C code to communicate through a flexible interface. SHARP is a streamlined, easily understood infrastructure which facilitates this process in two phases. In the first part, the SHARP GUI (An interactive Graphical User Interface) is used to load a program written in a high level general purpose programming language, to scan the code for SHARP POINTs (Portions Only Including Non-interscoping Types) based on user defined constraints, and then automatically translate such POINTs to a HDL. Finally the infrastructure needed to co-execute the updated program is generated. SHARP POINTs have a clearly defined interface and can be used by the SHARP scheduler. In the second part, the SHARP scheduler allows the SHARP POINTs to run on the chosen reconfigurable hardware, here an FPGA (Field Programmable Gate Array) and to commu- nicate cleanly with the original processor (for the software). The resulting system will be a good (though not necessarily optimal) acceleration of the original software application, that is easily maintained as the code continues to develop and evolve. / Graduate

In recent years, financial simulations have gotten computationally intensive due to larger portfolio sizes, and an increased demand to perform real-time risk analysis. In this paper, we propose a hardware implementation that uses a recursive analytical method to price the Collateralized Debt Obligations. A novel convolution approach based on FIFOs for storage is implemented for the recursive convolution. It is also used to address one of the main drawbacks of the analytical approach. The FIFO-based convolution approach is compared against two different convolution approaches outperforming them with a much smaller memory usage. The CDO core designed with the FIFO-based convolution method is implemented and tested on a Virtex-5 FPGA and compared against a C implementation, running on a 2.8GHz Intel Processor, resulting in a 41-fold speed up. A brief comparison against a Monte Carlo based hardware implementation for structured instruments yields mixed results.

In recent years, financial simulations have gotten computationally intensive due to larger portfolio sizes, and an increased demand to perform real-time risk analysis. In this paper, we propose a hardware implementation that uses a recursive analytical method to price the Collateralized Debt Obligations. A novel convolution approach based on FIFOs for storage is implemented for the recursive convolution. It is also used to address one of the main drawbacks of the analytical approach. The FIFO-based convolution approach is compared against two different convolution approaches outperforming them with a much smaller memory usage. The CDO core designed with the FIFO-based convolution method is implemented and tested on a Virtex-5 FPGA and compared against a C implementation, running on a 2.8GHz Intel Processor, resulting in a 41-fold speed up. A brief comparison against a Monte Carlo based hardware implementation for structured instruments yields mixed results.

The IEEE 802.15.4 standard defines the implementation of a Low-Rate Wireless Personal Area Network (WPAN). While the current version of the standard was ratified in 2006, there is still no readily available Medium Access Control (MAC) layer and/or Physical (PHY) layer for Altera Field Programmable Gate Arrays (FPGAs) in the public domain. This research investigates the implementation of the standard using an Altera FPGA for the MAC layer and PHY layer drivers. The Freescale MC13192 transceiver was used for the physical portion of the PHY layer, which includes the RF front end of the system. The purpose of this research was to implement a basic full function device (FFD), which is capable of acting as a node in the network, as well as co-ordinating it. This allows a simple network to be tested by loading the same code on two FPGA boards, with one configured to act as a coordinator and the other as a device. The flexibility of the standard means that there are several implementation choices to be made, each of which limits the compatibility with devices using other implementation options. The implementation and design decisions made in producing a preliminary core are described in detail. The implementation of the MAC layer primitives is discussed at length as these were not available as source code. These primitives are the building blocks for the core functions of the system. Specifically, the functionality of the Energy Detection (ED) scan, stream transmit and stream receive functions are explored in detail. The code has been implemented using C and is run on the Altera Nios II soft-core processor. The work presented here is an initial implementation meant to serve as a foundation for further research. Additional functionality defined by the standard could be added, or optimization of individual functions could be explored. The current implementation also has the potential to serve as the foundation for research into various sensors which may be part of end devices in the network.

The use of two dimensional (2D) digital filters for real-time 2D data processing has found important practical applications in many areas, such as aerial surveillance, satellite imaging and pattern recognition. In the case of military operations, real-time image pro-cessing is extensively used in target acquisition and tracking, automatic target recognition and identi cation, and guidance of autonomous robots. Furthermore, equal opportunities exist in civil industries such as vacuum cleaner path recognition and mapping and car collision detection and avoidance. Many of these applications require dedicated hardware for signal processing. It is not efficient to implement 2D digital filters using a single processor for real-time applications due to the large amount of data. A multiprocessor implementation can be used in order to reduce processing time. Previous work explored several realizations of 2D denominator separable digital filters with minimal throughput delay by utilizing parallel processors. It was shown that regardless of the order of the filter, a throughput delay of one adder and one multiplier can be achieved. The proposed realizations have high regularity due to the nature of the processors. In this thesis, all four realizations are implemented in a Field Programming Gate Array (FPGA) with floating point adders, multipliers and shift registers. The implementation details and design trade-offs are discussed. Simulation results in terms of performance, area and power are compared. From the experimental results, realization four is the ideal candidate for implementation on an Application Specific Integrated Circuit (ASIC) since it has the best performance, dissipates the lowest power, and uses the least amount of logic when compared to other realizations of the same filter size. For a filter size of 5 by 5, realization four can produce a throughput of 16.3 million pixels per second, which is comparable to realization one and about 34% increase in performance compared to realization one and two. For the given filter size, realization four dissipates the same amount of dynamic power as realization one, and roughly 54% less than realization three and 140% less than realization two. Furthermore, area reduction can be applied by converting floating point algorithms to fixed point algorithms. Alternatively, the denormalization and normalization stage of the floating point pipeline can be eliminated and fused together in order to save hardware resources.

The speed of fuzzy controllers implemented on dedicated hardware is adequate for control of any physical process, but too slow for todays high-complexity data networks. Defuzzification has been the bottleneck for fast implementations due to the large number of computationally expensive multiplication and division operations. In this thesis, we propose a high-speed fuzzy inferential system based on log-domain arithmetic, which only requires addition and subtraction operations. The system is implemented on a Xilinx Virtex-II FPGA with a processing speed of 67.6 MFLIPS having a maximum combinational path delay of 4.2 ns. It is a clear speedup compared to the reported fastest 50 MFLIPS implementation. A pipelined version of the controller is also implemented, which achieves a speed of 248.7 MFLIPS. Although a small approximation error is introduced, software simulation and hardware implementation on FPGA confirm high similarity of the outputs for control surfaces and a number of second-order plants. / Software Engineering and Intelligent Systems