Ingeniero Civil Eléctrico / Taote es un dispositivo de ultrasonido portátil de bajo costo completamente diseñado y construido en la Universidad de Chile. Su portabilidad, fácil uso y bajo costo lo hacen una herramienta idónea para el pre diagnostico conducido por médicos generales, dando solución al problema de congestión de la red de salud pública al evitar derivar casos innecesarios a otros centros de atención de mayor complejidad y dando un mayor acceso a este tipo de exámenes en zonas donde su acceso es restringido. Como producto en desarrollo, aún enfrenta diversos desafíos que deben resolverse, entre ellos, el tratamiento de imágenes para su realce. Los dispositivos de ultrasonido son afectos a un fenómeno particular llamado speckle, generado por la interferencia de la señal exploradora con los elementos pequeños en las superficies examinadas, lo que se traduce en artefactos granulares, zonas de alta y baja intensidad que dificultan el diagnóstico médico y automatizado. El objetivo principal de este trabajo consiste en diseñar e implementar distintas técnicas de procesamiento considerando las restricciones que impone Taote, tal que permitan realzar las imágenes de ultrasonido que provienen de él. Para ello, se estudian algunas técnicas existentes en el estado del arte , se simulan y evalúan para su posterior implementación. Al respecto, el operador lineal con ganancia adaptable de Lee y el operador no lineal de mediana multicapa, entregan los mejores desempeños seguidos por los operadores fundamentales (promedio y mediana convencional) para los índices de transformación de imágenes. Éstos entregan una métrica de la calidad de la transformación y no de la calidad de la imagen por sí misma (la cual es subjetiva y depende del observador) . Debido a la complejidad computacional, se diseñan circuitos que implementan estos operadores con ganancia fija, es decir, representándolos como la interpolación constante de operadores fundamentales en Verilog, para su posterior síntesis e implementación en la FPGA del equipo. En su implementación en el equipo, las capturas de las nuevas imágenes procesadas demuestran transformaciones similares a las obtenidas en las simulaciones, aunque con métricas de transformación diferente. Aún así , éstas logran validar las transformaciones en la imagen original de Taote. Finalmente, estas capturas fueron sometidas a la evaluación del ojo experto, donde el operador no lineal con ventana de tamaño 5 X 5 fue la elegida para ser incorporada en el proyecto. Si bien fue posible incorporar técnicas que modifican métricas de la imagen, un examen exhaustivo debe hacerse al obtener el índice de eficiencia de diagnostico de los operadores del producto y compararlos con los del producto sin la técnica de procesamiento. Hacer estas pruebas escapa a los alcances de este trabajo, pero hacerlo llevará a validar objetivamente las técnicas de procesamiento y abre las puertas a nuevos desarrollos, como el diagnóstico automatizado, segmentación de imágenes y otro tipo de desarrollos que acercarán al proyecto para lograr su cometido; incorporar un nuevo elemento en el diagnóstico médico general. / 03/10/2021

The introduction of autonomous vehicles has the potential to reduce the number of accidents and save countless lives. These benefits can only be realized if autonomous vehicles can prove to be safer than human drivers. There is a large amount of active research around developing robust algorithms for all parts of the autonomous vehicle stack including sensing, localization, mapping, perception, prediction, planning, and control. Additionally, some of these research projects have involved the use of the Robot Operating System (ROS). However, another key aspect of realizing an autonomous vehicle is a fault-tolerant design that can ensure the safe operation of the vehicle under unfavorable conditions. The goal of this thesis is to evaluate the feasibility of adding a dedicated fault tolerance module into a ROS based architecture. The fault tolerance module is used to implement a safety controller that can take over safety-critical operations of the system when a fault is detected in the main computer. A Xilinx Zynq-7000 SoC with a dual-core ARM Cortex-A9 and an FPGA programmable logic region is chosen as the platform. The platform works in the Asymmetric Multiprocessing (AMP) configuration with a Linux based operating system on one core and a real-time operating system (RTOS) on the other. Results are gathered from an implementation done on a ROS based mobile robot platform.

This master thesis deals with the design of the 400GBASE-R PCS in accordance with the IEEE 802.3bs-2017 standard which defines 400 Gbps Ethernet. The first part of this thesis focuses on general architecture of FPGA and its possible variants for implementation for 400 Gbps Ethernet communication, therefore there is description of those architectures and its resources. The next part describes progression of the Ethernet and its connection to the ISO/OSI reference model. The next section of this thesis is about description of physical layer of Ethernet for 400 Gbps version, after which follows design of PCS unit and its implementation with use of resources of selected FPGA. In the last part of this thesis is description of the simulation of the implemented unit. Achieved results and outcomes of this master thesis are evaluated in a conclusion.

This diploma thesis deals with the design of a precise multi-channel pulse generator for the synchronization of laser-induced breakdown spectroscopy (LIBS) instrumentation. The thesis reflects current state-of-the-art solutions in communication and trends in the field of laser spectroscopy. Moreover, the device is based on the modern implementation of embedded devices using C and C++ programming languages using the Ethernet for communication. The communication with the control software is provided via the SDD protocol; designed at CEITEC BUT. Finally, the data of the SDD protocol are sent by the hypertext transfer protocol (HTTP) protocol in native file format (JSON). This thesis brings the synchronization of the 10 devices by precision timing.

RSA cryptography is one of the most widely used cryptosystems in the world. FPGA/ASIC implementations for the classic RSA cryptosystem have high resource utilization due to the use of the Extended Euclid's algorithm for MOD inverse generation, the MOD exponent operation for encryption and decryption, and through non finite-field arithmetic. This thesis translates the RSA cryptosystem into the finite-field domain of arithmetic which greatly increases the range of encryption and decryption keys and replaces the MOD exponent with a multiplication. A new algorithm, the SPX algorithm, is presented and shown to outperform Euclid's algorithm, which is the most widely used mechanism to compute the GCD in FPGA implementations of RSA. The SPX algorithm is then extended to support the computation of the MOD inverse and supply decryption keys. Lastly, a finite-field RSA system is created and shown to support character encryption and decryption while being designed to be integrated into any larger system.

This master thesis deals with Z80 core implementation inside FPGA. In this thesis we discuss possible cabalities of the core as a microcontroller or as a ZX Spectrum. There is also described proposed control system, which can change contents of the memory and registers during communication with PC via serial line. There are also shown a describe of development tools, especially compilers and development boards, which we have used.

The master’s thesis is focused on desing high-speed ethernet switch based on circuit FPGA. The switch is able to divide one data stream, created from ethernet frames to the two data streams with half data flow.

The thesis deals with the theory and design of the network traffic generator on the FPGA platform. The VHDL programming language is used for the description. The work involves getting acquainted with the development processes and design tools needed to create the overall project. It also includes familiarity with the necessary FPGA, NetCOPE and COMBO cards. Based on this information, was designed, tested and implemented packet generator project for the Combo-80G card. For implementation was used framework from NetCOPE.

This thesis deals with controlling a color graphic LED display using an FPGA. The first half of the theoretical part of this paper describes the properties of the used FPGA, the data source and a principle of controlling an RGB LED display. The second half describes an implementation of pulse width modulation and binary code modulation which enables the control of brightness of the display and of color depth of every sub-pixel. The practical part on the other hand describes the designing and the implementation of this module in the VHDL language. Then it explains the transfer of image data from Blackfin processor to the memory via PPI interface, the subsequent process of reading data from the memory, conversion of the data to a serial format and finally it describes the process of sending the data to the LED controller. The module was realized on the Digilent Atlys development board equipped with the Spartan-6 FPGA and was tested on a 32x20 light panel for the firm Ing. Ivo Herman, CSc.

Many avenues exist to insert malicious circuitry into an FPGA designs, including compromised CAD tools, overwriting bitstream files, and post-deployment attacks. The proprietary nature of the Xilinx bitstreams precludes the ability to validate an implemented design. This thesis introduces the BitRec and IPRec projects in an effort to support trojan detection tools. BitRec provides a novel approach to mapping of the Xilinx bitstream format into FPGA features in order to recreate the original design's netlist. BitRec supports the 7 Series, UltraScale and UltraScale+ architectures. IPRec then provides a novel approach to recognizing parameterizable IP within a flattened netlist in an effort to eliminate large sections of trusted circuitry from needing to be analyzed by a trojan detection tool.