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La presente tesis pretende establecer un puente entre el modelado, identificación y control de sistemas y la microelectrónica, aportando una herramienta con la capacidad de afrontar requerimientos de velocidad, precisión y tamaño de implementación. Así mismo pretende, implementar algoritmos de identificación que puedan ser desarrollados en un chip y proveer un análisis de los errores que se producen como consecuencia de la digitalización y operaciones de punto fijo. / This thesis aims to establish a bridge from modeling, identification and control systems to microelectronics, providing a tool with the ability to meet requirements of speed, accuracy and size of the implementation. Furthermore, implement an identification algorithm that can be implemented on the chip and provide, also, an analysis of the errors occurring as a result of digitization and fixed point operations.

En el ámbito del diseño de circuitos integrados, el proceso de asegurar que la intención del diseño es mapeada correctamente en su implementación se denomina verificación funcional. En este contexto, los errores lógicos son discrepancias entre el comportamiento previsto del dispositivo y su comportamiento observado. La verificación funcional es hoy en día el cuello de botella del flujo de diseño digital y la simulación de eventos discretos sigue siendo la técnica de verificación más utilizada, principalmente debido a que es la única aplicable a sistemas grandes y complejos. En este trabajo se aborda, mediante un enfoque teórico práctico, dos de los conceptos más relevantes de la verificación funcional de hardware basada en simulación, esto es, la arquitectura de los testbenches, los cuales le dan soporte práctico a dicha técnica y los modelos de cobertura funcional, los cuales definen las funcionalidades y escenarios que deben ser probados guiando de esta forma la creación de pruebas y el respectivo progreso del proceso de verificación. En primer lugar, se encara la temática de la arquitectura de los testbenches modernos identificando las propiedades deseadas de los mismos, reusabilidad y facilidad para aumentar el nivel de abstracción. En función de estas dos propiedades se selecciona la metodología de Universal Verification Methodology (UVM) para el diseño, análisis e implementación de dos testbenches. En segundo lugar, dada la problemática del crecimiento del espacio de prueba de los diseños modernos y la subsecuente dificultad para generar modelos de cobertura adecuados para los mismos a partir de sus especificaciones, se introduce un método empírico de caja negra para derivar un modelo de cobertura para diseños dominados por el control. Este método está basado en la utilización de un modelo abstracto de la funcionalidad del dispositivo bajo prueba (DUV, sigla en inglés de Device Under Verification). Este modelo facilita la extracción de conjuntos de secuencias de prueba, los cuales representan el modelo de cobertura funcional. Dada la complejidad de los posibles espacios de prueba generados, las conocidas técnicas de Testing de Software, partición en clases de equivalencia y análisis de valores límites, son aplicadas para reducirlos. Adicionalmente, se desarrolla una notación formal para expresar las secuencias de prueba equivalentes extraídas del modelo. Por ultimo se aplica el método de derivación de modelo de cobertura funcional presentado para obtener casos de prueba relevantes para un modulo de buffer FIFO, y se utiliza el testbench implementado para darle soporte a la ejecución de dichos casos de prueba, implementando las pruebas derivadas y los correspondientes puntos de cobertura, combinando de esta forma los dos conceptos abordados. / In the integrated circuit design field, the process of assuring that the design intent is properly mapped in its implementation is known as functional verification. In this context, logic errors are discrepancies between the device’s expected behavior and its observed behavior. The functional verification of a design is now a days the bottleneck of the digital design flow and discrete event simulation still is the most used verification technique, mostly because it is the only technique which is applicable to big and complex systems. In this work, through a theoretical and practical approach, two of the most relevant simulation based hardware functional verification concepts are addressed. Those concepts are, the testbench architecture, which gives practical support to the simulation technique, and the functional coverage model, which defines the functionalities and scenarios that should be tested, guiding the creation of tests and the measurement of the verification process’s progress. In first place, modern testbench architectures are studied identifying their desired properties, which are reusability and the facility to raise the level of abstraction. According to these properties the Universal Verification Methodology (UVM) is chosen for the design, analysis and implementation of two testbenches. In second place, given the test space growth challenge of modern designs and the subsequent difficulty for generating their appropriate coverage models from their specifications, an empirical black box method is introduced for the creation of coverage models for control dominated designs. This method is based in the definition of a functional model of the DUV (Design Under Verification) which facilitates the extraction of sets of test sequences which define a functional coverage model. Given the complexity of the test space, the well known software testing techniques, equivalence class partition and limit value analysis, are applied to reduce it. A formal notation is developed in order to express equivalent test sequences. Lastly, the presented functional coverage creation method is applied to a FIFO (First Input First Output) buffer module in order to obtain relevant test sequences, and one of the previously implemented testbench is used to give support to the execution of those test cases, implementing the test sequences and its corresponding coverage points, combining in this manner both of this work addressed concepts.

Advances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes in a design can lead to fast turnaround times for implementing even large designs. A high-level overview of an incremental productivity flow, focusing on the back-end FPGA design is provided in this thesis. This thesis presents a management paradigm that is used to capture the design specific information in a format that is reusable across the entire design process. A C++ based internal data structure stores all the information, whereas XML is used to provide an external view of the design data. This work provides a vendor independent, universal format for representing the logical and physical information associated with FPGA designs. / Master of Science

During the development of complex embedded systems like controllers, conducting real-world testing can often be impractical due to factors such as cost, safety concerns, or unavailability during certain stages of development. In such scenarios, hardware-in-the-loop testing is a practical alternative. Hardware-in-the-loop testing involves interfacing the device under test with a simulation environment that mimics real-world inputs, enabling comprehensive testing without the associated risks or constraints. This thesis focuses on the transformation of a Matlab model depicting the behavior of a falling missile into VHDL. The purpose of this model is to integrate with an FPGA to facilitate real-time testing of control algorithm and associated hardware. The conversion successfully translated the Matlab model into VHDL, enabling execution within the constraints of the real-time system.  While the VHDL model closely mirrors the original Matlab model, minor deviations exist due to the discretisation process, resulting in slight discrepancies. However, suggestions on how to overcome these are proposed.

While Field-Programmable Gate Arrays (FPGAs) exist in many design configurations throughout the data center, cloud, and edge, the promise of performance and flexibility offered by the FPGA often remains unrealized for lack of hardware design expertise, with most computation remaining in fixed hardware such as CPUs, GPUs, and ASICs e.g. tensor processors. Identifying programmability as a barrier to FPGA usage, we seek to augment High Level Synthesis (HLS) design flows with machine learning. The overall goal of this dissertation is to advance the art of using unmodified high-level language (HLL) programs to create FPGA configurations that are performant, programmable, and portable. The problems in using HLL code to program FPGAs arise from the serial execution model of the target application codes, in particular, the mismatch between that model and the arbitrary data flow model of the target hardware. However, a variety of code transformation techniques, tedious to perform by a human but readily and effortlessly done by CPU compilers, allow many compute-intensive operations to be transformed into a form that is highly or massively parallel. A challenge then exists in selecting the best set of optimizations and an order in which to perform them, a choice among staggeringly many options. Brute-force and automated orthogonal search techniques have failed to produce solutions that lie within the realm of practicality. We evaluate the suitability of machine learning (ML) models to address this challenge. We develop and assess designs for systems that use ML and present feedback to these models based on their recommendations. In support of using ML models, we begin by developing and assessing methods for preparing the original program as input for processing by the model. We next develop and assess methods to apply the model's output to a compilation system and evaluate the results for use as feedback. Machine learning experiments are performed to demonstrate their potential. Feasibility is studied through simulations and specialized evaluation techniques as appropriate. Specific new artifacts are created, including extensions to the open-source GCC compiler. The significance of this work is of several types: the many options and variants to the overall design that are considered, with their distinct advantages and disadvantages; the application of proper units and baselines to experimental measurements; and the numerous contributions in the form of published extensions and improvements to open-source projects.

RSA cryptography is one of the most widely used cryptosystems in the world. FPGA/ASIC implementations for the classic RSA cryptosystem have high resource utilization due to the use of the Extended Euclid's algorithm for MOD inverse generation, the MOD exponent operation for encryption and decryption, and through non finite-field arithmetic. This thesis translates the RSA cryptosystem into the finite-field domain of arithmetic which greatly increases the range of encryption and decryption keys and replaces the MOD exponent with a multiplication. A new algorithm, the SPX algorithm, is presented and shown to outperform Euclid's algorithm, which is the most widely used mechanism to compute the GCD in FPGA implementations of RSA. The SPX algorithm is then extended to support the computation of the MOD inverse and supply decryption keys. Lastly, a finite-field RSA system is created and shown to support character encryption and decryption while being designed to be integrated into any larger system.

Denna rapport omfattar ett 15 poängs (22,5 högskolepoäng) examensarbete vid Karlstads universitet. Arbetet har utförts på plats hos BAE Systems Bofors i Karlskoga. Företaget ville kunna styra en radiostyrd leksaksstridsvagn med en laserpekare. En kamera ansluten till en digital signalprocessor (DSP) skulle kunna detektera var en laserpunkt befinner sig och styra stridsvagnen mot den. Ett styrgränssnitt mellan DSP:n och leksaksstridsvagnen konstruerades och byggdes med hjälp av en programmerbar logisk krets. Leksaksstridsvagnens interna signalsystem analyserades. En manchesterkodad signal i form av ett 32-bitars seriellt kodord hittades, vilket ursprungligen kom från radiostyrningen. Ett styrgränssnitt konstruerades kring en CPLD (Complex Programmable Logic Device) vilken programmerades med VHDL (Very high speed integrated Hardware Description Language) som återskapar den Manchesterkodade styrsignalen. Gränssnittet ansluter till DSP:n som kontrollerar stridsvagnens styrning och övriga funktioner till fullo. Kommunikationen mellan styrgränssnittet och DSP:n sker via ett parallellgränssnitt som är 16-bitar brett. 13 bitar är datasignaler och övriga tre är ”styrbitar” som konfigurerar gränssnittet. En applikation integrerades i projektet för att demonstrera styrgränssnittets funktion. DSP:n tolkar var en laserpunkt befinner sig inom ett kameraområde och skickar motsvarande styrsignaler till leksaksstridsvagnen. / This report consists of a 15 points (22.5 ECTS) Exam Degree project at Karlstad University. The work was done on location at BAE Systems Bofors AB in Karlskoga. The company wanted to control a radio controlled toy tank from a digital signal processor (DSP). A camera connected to the DSP locates the laser point and steers the toy tank towards it. An interface using a programmable logic device was constructed that connects the DSP to the toy tank. The internal signals in the toy tank was analyzed and a Manchester coded signal in form of a 32-bit serial code word was detected. The code word originated from the radio controller. The control interface was built around a CPLD (Complex Programmable Logic Device) which was programmed in VHDL (Very high speed integrated Hardware Description Language). The control interface recreates the signal controlling the toy tank. The interface connects the toy tank to the DSP which controls the toy tank and it’s functions to the full extent. Communication between the interface and the DSP is done via a 16 bit parallel connection. 13 of the bits are data bits and the remaining 3 are control bits that are used to set up the interface. An application was integrated in the project where the DSP is detecting a laser point. Corresponding signals to the laser points position where sent to the control interface to demonstrate the function of the interface.

Detta examensarbetet har utförs vid Calmon Stegmotorteknik AB (CST) för att utveckla FPGA delen av derasutvecklingsplattform. Denna rapport avser att ge tankar och teori om utvecklingsmetodiken av detta arbetet. CST:s utvecklingsplattform ska användas för videobehandling, motorstyrningar samt mät och instrumentapplikationer. Dock berör detta arbetet endast de funktioner som behövs för att kunna använda utvecklingskortet för motorstyrningar. Detta innefattar implementationer av PWM, mikrostegningstyrning samt motorstyrning med hjälp av fullsteg och halvsteg. / This Bachelor thesis have been done for Calmon Stegmotorteknik AB (CST) to develop the FPGA part of their developmentplatform. This thesis is created to give thoughts and theory about the development methodology used in this project. CST:s development platform will be used for video processing, motor controls and also measurement and instrument applications.This thesis however concerns only the functions that is needed for using motor controls on the development board. Which includes implementation of PWM, microstepping control and also motor control with help of fullstep and halfstep.

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