The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It also enables the designer to try out dierent optimization strategies early in the design stage. In-spite of all these advantages, high-level synthesis design methodologies have not gained much popularity in the mainstream design flow mainly because of the reasons like lack of readability and reliability of the generated register transfer level (RTL) code. The compiler framework presented in this thesis allows the user to draw high-level graphical models of the system. The compiler translates these models into synthesizeable RTL Verilog designs that exhibit their desired functionality following communicating sequential processes (CSP) model of computation. CSP model of computation introduces a good handshaking mechanism between different components in the design that makes designs less prone to timing violations during implementation and bottlenecks while in actual operation. / Master of Science

“Smart” surveillance systems require a visual tracking system that is able to detect and follow a moving target in the field of view of a camera. Visual tracking systems have been traditionally developed either as application specific hardware or as software written for parallel architectures because of the large number of computations that have to be performed at very high speeds. This thesis describes the implementations of two visual tracking systems on a custom computing machine based on Field Programmable Gate Arrays (FPGAs). The implementations apply a coarse-to-fine search on Gaussian pyramids constructed from the images generated by a camera. One system tracks a target of size 16x16 in an image sequence with output images of size 256x256. This system is capable of operating at 30 pyramids per second. The second system tracks a target of size 16x16 in an image sequence with output images of size 512x512. This system is capable of operating at 15 pyramids per second. Both systems are designed with pipelined architectures and numerical computations are handled using a SIMD approach. / Master of Science

Made available in DSpace on 2014-12-17T15:48:12Z (GMT). No. of bitstreams: 1 CamilaA.pdf: 551643 bytes, checksum: c211e0d0bbaf86da86337efffe6f407b (MD5) Previous issue date: 2007-07-28 / The Reconfigurables Architectures had appeares as an alternative to the ASICs and the GGP, keeping a balance between flexibility and performance. This work presents a proposal for the modeling of Reconfigurables with Chu Spaces, describing the subjects main about this thematic. The solution proposal consists of a modeling that uses a generalization of the Chu Spaces, called of Chu nets, to model the configurations of a Reconfigurables Architectures. To validate the models, three algorithms had been developed and implemented to compose configurable logic blocks, detection of controllability and observability in applications for Reconfigurables Architectures modeled by Chu nets / As Arquiteturas Reconfigur?veis surgiram no ambiente acad?mico como uma alternativa aos ASICs e aos GGP, mantendo um equil?brio entre flexibilidade e performance. Este trabalho apresenta uma proposta para a modelagem de Arquiteturas Reconfigur?veis com Espa?os de Chu, descrevendo os principais assuntos relativos a esta tem?tica. A solu??o proposta consiste em uma modelagem que utiliza uma generaliza??o dos Espa?os de Chu, denominada de Chu nets, para modelar as configura??es de uma Arquitetura Reconfigur?vel. Como forma de validar os modelos, foram desenvolvidos e implementados tr?s algoritmos que realizam a composi??o de c?lulas l?gicas program?veis, detec??o dos vetores de controlabilidade e observabilidade em aplica??es para Arquiteturas Reconfigur?veis, que est?o modeladas atrav?s das Chu nets

L’augmentation de la taille des réseaux actuels ainsi que de la diversité des applications qui les utilisent font que les architectures de calcul traditionnelles deviennent limitées. En effet, les architectures purement logicielles ne permettent pas de tenir les débits en jeu, tandis que celles purement matérielles n’offrent pas assez de flexibilité pour répondre à la diversité des applications. Ainsi, l’utilisation de solutions de type matériel programmable, en particulier les Field Programmable Gate Arrays (FPGAs), a été envisagée. En effet, ces architectures sont souvent considérées comme un bon compromis entre performances et flexibilité, notamment grâce à la technique de Reconfiguration Dynamique Partielle (RDP), qui permet de modifier le comportement d’une partie du circuit pendant l’exécution. Cependant, cette technique peut présenter des inconvénients lorsqu’elle est utilisée de manière intensive, en particulier au niveau du stockage des fichiers de configuration, appelés bitstreams. Pour palier ce problème, il est possible d’utiliser la relocation de bitstreams, permettant de réduire le nombre de fichiers de configuration. Cependant cette technique est fastidieuse et exige des connaissances pointues dans les FPGAs. Un flot de conception entièrement automatisé a donc été développé dans le but de simplifier son utilisation.Pour permettre une flexibilité sur l’enchaînement des traitements effectués, une architecture de communication flexible supportant des hauts débits est également nécessaire. Ainsi, l’étude de Network-on-Chips dédiés aux circuits reconfigurables et au traitements réseaux à haut débit.Enfin, un cas d’étude a été mené pour valider notre approche. / The increase in both size and diversity of applications regarding modern networks is making traditional computing architectures limited. Indeed, purely software architectures can not sustain typical throughputs, while purely hardware ones severely lack the flexibility needed to adapt to the diversity of applications. Thus, the investigation of programmable hardware, such as Field Programmable Gate Arrays (FPGAs), has been done. These architectures are indeed usually considered as a good tradeoff between performance and flexibility, mainly thanks to the Dynamic Partial Reconfiguration (DPR), which allows to reconfigure a part of the design during run-time.However, this technique can have several drawbacks, especially regarding the storing of the configuration files, called bitstreams. To solve this issue, bitstream relocation can be deployed, which allows to decrease the number of configuration files required. However, this technique is long, error-prone, and requires specific knowledge inFPGAs. A fully automated design flow has been developped to ease the use of this technique. In order to provide flexibility regarding the sequence of treatments to be done on our architecture, a flexible and high-throughput communication structure is required. Thus, a Network-on-Chips study and characterization has been done accordingly to network processing and bitstream relocation properties. Finally, a case study has been developed in order to validate our approach.

Smoothing filters have been extensively used for noise removal and image restoration. Directional filters are widely used in computer vision and image processing tasks such as motion analysis, edge detection, line parameter estimation and texture analysis. It is practically impossible to tune the filters to all possible positions and orientations in real time due to huge computation requirement. The efficient way is to design a few basis filters, and express the output of a directional filter as a weighted sum of the basis filter outputs. Directional filters having these properties are called "Steerable Filters." This thesis work emphasis is on the implementation of proposed computationally efficient separable and steerable Gaussian smoothers on a Xilinx VirtexII Pro FPGA platform. FPGAs are Field Programmable Gate Arrays which consist of a collection of logic blocks including lookup tables, flip flops and some amount of Random Access Memory. All blocks are wired together using an array of interconnects. The proposed technique [2] is implemented on a FPGA hardware taking the advantage of parallelism and pipelining.

A diminuição no tamanho dos transistores vem aumentando cada vez mais o número de funções que os dispositivos eletrônicos podem realizar. Apesar da diminuição do tamanho mínimo dos transistores, a velocidade máxima dos circuitos não consegue seguir a mesma taxa de aumento. Um dos grandes culpados apontados pelos pesquisadores são as interconexões entre os transistores e também entre os componentes. O aumento no número de interconexões dos circuitos traz consigo um significativo aumento do cosumo de energia, aumento do atraso de propagação dos sinais, além de um aumento da complexidade e custo do projeto dos circuitos integrados. Como uma possível solução a este problema é proposta a utilização de lógica multivalorada, mais especificamente, a lógica quaternária. Os dispositivos FPGAs são caracterizados principalmente pela grande flexibilidade que oferecem aos projetistas de sistemas digitais. Entretanto, com o avanço nas tecnologias de fabricação de circuitos integrados e diminuição das dimensões de fabricação, os problemas relacionados ao grande número de interconexões são uma preocupação para as próximas tecnologias de FPGAs. As tecnologias menores que 90nm possuem um grande aumento na taxa de erros dos circuitos, na lógica combinacional e sequencial. Apesar de algumas potenciais soluções começara a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe o uso de circuitos quaternários com modificações para tolerar falhas provenientes de eventos transientes. Como principal contribuição deste trabalho destaca-se o desenvolvimento de uma CLB (do inglês Configurable Logic Block) quaternária capaz de suportar eventos transientes e, na possibilidade de um erro, evitá-lo ou corrigi-lo. / The decrease in transistor size is increasing the number of functions that can be performed by the electronic devices. Despite this reduction in the transistors minimum size, the circuit’s speed does not follow the same rate. One of the major reasons pointed out by researchers are the interconnections between the transistors and between the components. The increase in the number of circuit interconnections brings a significant increase in energy consumption, propagation delay of signals, and an increase in the complexity and cost of new technologies IC designs. As a possible solution to this problem the use of multivalued logic is being proposed, more specifically, the quaternary logic. FPGA devices are characterized mainly by offering greater flexibility to designers of digital systems. However, with the advance in IC manufacturing technologies and the reduced size of the minimum fabricated dimensions, the problems related to the large number of interconnections are a concern for future technologies of FPGAs. The sub 90nm technologies have a large increase in the error rate of its functions for the combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes the use of quaternary circuits with modifications to tolerate faults from transient events. The main contribution of this work is the development of a quaternary CLB (Configurable Logic Block) able to withstand transient events and the occurrence of soft errors.

Submitted by camilla martins (camillasmmartins@gmail.com) on 2016-12-13T13:41:29Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_MetodosExtracaoObjetos.pdf: 4311109 bytes, checksum: 6e08c6d9873edcc3fc808b09600ca4a9 (MD5) / Rejected by Edisangela Bastos (edisangela@ufpa.br), reason: on 2016-12-15T12:10:14Z (GMT) / Submitted by camilla martins (camillasmmartins@gmail.com) on 2016-12-15T13:50:53Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_MetodosExtracaoObjetos.pdf: 4311109 bytes, checksum: 6e08c6d9873edcc3fc808b09600ca4a9 (MD5) / Rejected by Edisangela Bastos (edisangela@ufpa.br), reason: on 2016-12-15T14:01:33Z (GMT) / Submitted by camilla martins (camillasmmartins@gmail.com) on 2016-12-15T14:27:31Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_MetodosExtracaoObjetos.pdf: 4311109 bytes, checksum: 6e08c6d9873edcc3fc808b09600ca4a9 (MD5) / Approved for entry into archive by Edisangela Bastos (edisangela@ufpa.br) on 2016-12-19T15:40:45Z (GMT) No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_MetodosExtracaoObjetos.pdf: 4311109 bytes, checksum: 6e08c6d9873edcc3fc808b09600ca4a9 (MD5) / Made available in DSpace on 2016-12-19T15:40:45Z (GMT). No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_MetodosExtracaoObjetos.pdf: 4311109 bytes, checksum: 6e08c6d9873edcc3fc808b09600ca4a9 (MD5) Previous issue date: 2009-12-04 / A segmentação de vídeo é um passo fundamental em muitos sistemas de visão, tais como sistemas de vigilância e monitoramento de tráfego. O método denominado subtração da imagem de fundo é comumente utilizado para detecção de objetos em seqüências de vídeo comparando-se cada pixel do quadro corrente com um modelo da imagem de referência. Neste trabalho, apresenta-se uma arquitetura em hardware para segmentação de vídeo desde a etapa de implementação do algoritmo em PC até a elaboração da arquitetura em hardware. O método de segmentação de vídeo destina-se ao processamento de operações em ponto fixo e visa aprimorar o método de detecção de objetos baseado em modelos Gaussianos. Este aprimoramento é realizado por meio da aplicação de uma técnica para compensação das variações das intensidades dos pixels que objetiva reduzir os falsos positivos ocasionados por ruídos ou variações de iluminação. Primeiramente, o algoritmo foi validado em MATLAB em ponto flutuante e em ponto fixo. Em seguida, foi implementado em um arranjo de portas programáveis em campo (FPGA), utilizando um kit desenvolvimento da Altera (DE-2). A arquitetura opera com uma freqüência igual a 100 MHz e processa 30 quadros por segundo com resolução igual é 640 x 507. A capacidade do sistema é demonstrada com várias imagens de teste. / Video segmentation is a fundamental step in many vision systems including video surveillance and traffic monitoring. Background subtraction is a method typically used to segment moving regions in video sequences taken from a static camera by comparing each new frame to a model of the scene background. In this paper, a hardware system for video segmentation is proposed from algorithm to hardware architecture level. The video segmentation algorithm is aimed at fixed-point operations and improves a Gaussian background model by applying a two-stage linear compensation procedure to remove the undesirable subtraction results from noise and illumination changes. First, the algorithm was validated in MATLAB. Then, it was prototyped on an Altera field-programmable gate array platform (DE-2). At a clock rate of 100 MHz, the architecture can process 30 frames per second, where the image resolution is 640 x 507 pixels. The capability of the system is demonstrated for several video sequences.

Submitted by camilla martins (camillasmmartins@gmail.com) on 2017-03-27T14:15:54Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Dissertacao_FPGAImplementationEvaluationSynchronization.pdf: 2830093 bytes, checksum: e1b387f09fb4dc8dfe1b7ef75888a84e (MD5) / Approved for entry into archive by Edisangela Bastos (edisangela@ufpa.br) on 2017-03-28T13:02:13Z (GMT) No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Dissertacao_FPGAImplementationEvaluationSynchronization.pdf: 2830093 bytes, checksum: e1b387f09fb4dc8dfe1b7ef75888a84e (MD5) / Made available in DSpace on 2017-03-28T13:02:13Z (GMT). No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Dissertacao_FPGAImplementationEvaluationSynchronization.pdf: 2830093 bytes, checksum: e1b387f09fb4dc8dfe1b7ef75888a84e (MD5) Previous issue date: 2016-01-18 / CNPq - Conselho Nacional de Desenvolvimento Científico e Tecnológico / A utilização da infra-estrutura Ethernet disponível na maioria dos edifícios comerciais pode aliviar os custos envolvidos com provisionamento de fronthaul em redes de acesso de rádio em nuvem. No entanto, as especificações atuais de interfaces fronthaul contam com links síncronos e dedicados, os quais suportam nativamente recursos como a distribuição da sincronização através da camada física dos dispositivos. Neste contexto, uma solução de bom custo benefício e compatível com protocolos e equipamentos em atual uso e adaptar as interfaces fronthaul padrão (e.g. CPRI) para redes assíncronas usando equipamentos capazes de atingir requisitos de sincronização através de redes Ethernet legadas. Esta dissertação propõe considerações de projeto e avalia a viabilidade de arquiteturas de sincronização em tal cenário, através do desenvolvimento de um banco de testes com hardware baseado em FPGA. São contrastadas duas soluções: uma abordagem simples que emprega fila elástica de recepção para a recuperação de frequência e uma solução fim-a-fim utilizando o protocolo de precisão de tempo IEEE 1588 para alinhamento em tempo e frequência. Resultados sugerem que o esquema utilizando PTP somente nos pontos finais pode atingir os requisitos de sincronização de tempo e frequência estabelecidos por padrões de telefonia móvel atuais se a variação de atraso de pacote for tratada com razoáveis estratégias implementadas a n´nível de algoritmo. / The use of Ethernet infrastructure available in most commercial buildings can alleviate the costs involved with fronthaul provisioning in cloud radio access networks. However, current fronthaul specifications rely on dedicated synchronous links, which natively support features such as accurate synchronization across radio devices. In this context, a cost-effective and backwardscompatible solution is to adapt standard fronthaul interfaces (e.g. CPRI) to asynchronous networks by using endpoint equipments capable of meeting synchronization requirements over legacy Ethernet. This dissertation proposes design considerations for synchronization of radio over Ethernet and evaluates the feasibility of synchronization architectures by developing an FPGA-based hardware testbed. It contrasts two solutions, a simplistic approach that employs elastic buffering for recovering frequency and an end-to-end IEEE 1588 Precision Time Protocol solution for time and frequency alignment. Results suggest that the scheme with PTP solely at the endpoints can comply with time and frequency alignment requirements of current mobile standards if packet delay variation is treated with sound algorithms.

A diminuição no tamanho dos transistores vem aumentando cada vez mais o número de funções que os dispositivos eletrônicos podem realizar. Apesar da diminuição do tamanho mínimo dos transistores, a velocidade máxima dos circuitos não consegue seguir a mesma taxa de aumento. Um dos grandes culpados apontados pelos pesquisadores são as interconexões entre os transistores e também entre os componentes. O aumento no número de interconexões dos circuitos traz consigo um significativo aumento do cosumo de energia, aumento do atraso de propagação dos sinais, além de um aumento da complexidade e custo do projeto dos circuitos integrados. Como uma possível solução a este problema é proposta a utilização de lógica multivalorada, mais especificamente, a lógica quaternária. Os dispositivos FPGAs são caracterizados principalmente pela grande flexibilidade que oferecem aos projetistas de sistemas digitais. Entretanto, com o avanço nas tecnologias de fabricação de circuitos integrados e diminuição das dimensões de fabricação, os problemas relacionados ao grande número de interconexões são uma preocupação para as próximas tecnologias de FPGAs. As tecnologias menores que 90nm possuem um grande aumento na taxa de erros dos circuitos, na lógica combinacional e sequencial. Apesar de algumas potenciais soluções começara a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe o uso de circuitos quaternários com modificações para tolerar falhas provenientes de eventos transientes. Como principal contribuição deste trabalho destaca-se o desenvolvimento de uma CLB (do inglês Configurable Logic Block) quaternária capaz de suportar eventos transientes e, na possibilidade de um erro, evitá-lo ou corrigi-lo. / The decrease in transistor size is increasing the number of functions that can be performed by the electronic devices. Despite this reduction in the transistors minimum size, the circuit’s speed does not follow the same rate. One of the major reasons pointed out by researchers are the interconnections between the transistors and between the components. The increase in the number of circuit interconnections brings a significant increase in energy consumption, propagation delay of signals, and an increase in the complexity and cost of new technologies IC designs. As a possible solution to this problem the use of multivalued logic is being proposed, more specifically, the quaternary logic. FPGA devices are characterized mainly by offering greater flexibility to designers of digital systems. However, with the advance in IC manufacturing technologies and the reduced size of the minimum fabricated dimensions, the problems related to the large number of interconnections are a concern for future technologies of FPGAs. The sub 90nm technologies have a large increase in the error rate of its functions for the combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes the use of quaternary circuits with modifications to tolerate faults from transient events. The main contribution of this work is the development of a quaternary CLB (Configurable Logic Block) able to withstand transient events and the occurrence of soft errors.

Cette thèse s'intéresse en premier lieu à l'analyse des effetsfonctionnels des erreurs dans laconfiguration de FPGAs à base de SRAM. Ces erreurs peuvent provenir deperturbations naturelles(rayonnements, particules) ou d'attaques volontaires, par exemple avecun laser. La famille Virtex IIde Xilinx est utilisée comme premier cas pratique d'expérimentation,puis une comparaison est réaliséeavec la famille AT40K de chez ATMEL. Ceci a permis de mieux comprendrel'impact réel dedifférentes sources de perturbations, et les motifs d'erreur devantréellement être pris en compte pouraméliorer la robustesse d'un circuit implanté sur ce type detechnologie. Cette étude a nécessité ledéveloppement d'outils de conception spécifiques, permettantd'automatiser les analyses. Uneméthodologie innovante est proposée pour l'évaluation de lasensibilité de la mémoire de configurationaux SEUs : une classification des bits de configuration est établie enfonction des effets produits parleur inversion sur le fonctionnement normal de l'application. Cecipermet de déterminer les zones lesplus critiques, autorisant le développement de stratégies deprotection sélectives et à faible coût. / This thesis deals primarily with the analysis of the functionaleffects of errors in the configuration ofSRAM-based FPGAs. These errors can be due either to naturalperturbations (radiations, particles) orto malicious attacks, for example with a laser. The Xilinx Virtex IIfamily is used as first case study,then a comparison is made with the ATMEL AT40K family. This workallowed us a betterunderstanding of the real impact of perturbations, and of the errorpatterns that need to be taken intoaccount when improving the robustness of a circuit implemented on thistype of technology. Thisstudy required the development of specific design tools to automatethe analyses. An innovativemethodology is proposed for the evaluation of the configuration memorysensitivity to SEUs: aclassification of configuration bits is made with respect to theeffects produced on the application by asingle bit-flip. This enables us to identify the most critical areas,and to propose selective hardeningsolutions, improving the global reliability of the application at low cost.