Cette thèse s’inscrit dans le cadre du développement d’une filière de transistors de puissance à base de nitrure de Gallium au CEA-LETI. Ces transistors, en particulier les HEMT utilisant l’hétérostructure AlGaN/GaN, présentent des propriétés très utiles pour les applications de puissance. L’essor de cette technologie passe notamment par le développement de contacts ohmiques peu résistifs. Cette thèse a pour objectif d’approfondir la compréhension des mécanismes de formation du contact ohmique sur une structure AlGaN/GaN. Dans un premier temps, une étude thermodynamique sur une dizaine de métaux de transition utilisables comme base de l’empilement métallique du contact a été menée, ce qui a permis de retenir une métallisation Ti/Al. Puis, les différentes réactions physico-chimiques de cet empilement avec des substrats nitrurés ont été étudiées en faisant varier la composition et les températures de recuit de formation du contact ohmique. Enfin, plusieurs études sur structure AlGaN/GaN couplant caractérisations électriques et physico-chimiques ont permis d’identifier des paramètres décisifs pour la réalisation d’un contact ohmique, peu résistif et nécessitant une faible température de recuit. / This PhD is part of the development of Gallium nitride based power transistors at the CEA-LETI. These transistors, especially those based on AlGaN/GaN heterostructure, are very promising for power electronics applications. The goal of this PhD is to increase the knowledge of the mechanisms responsible for the ohmic contact formation on a AlGaN/GaN structure. First, a thermodynamic study of several transition metals has been performed, leading us to select Ti/Al metallization. Then, the multiple physico-chemical reactions of this stack with nitride substrates have been studied depending on the stack composition and the annealing temperature. Finally, several studies on AlGaN/GaN structure coupling both physico-chemical and electrical characterizations reveal different decisive parameters for the formation of an ohmic contact with a low-resistance and a low annealing temperature.

Power device robustness refers to the device capability of withstanding abnormal events in power electronics applications, which is one of the key device capabilities that are desired in numerous applications. While the current robustness test methods and qualification standards are developed across the 70 years of Silicon (Si) device history, their applicability to the recent wide bandgap (WBG) power devices is questionable. While the market of WBG power devices has exceeded $1 billion and is fast growing, there are many knowledge gaps regarding their robustness, including the failure or degradation physics, testing methods, and lifetime extraction. This dissertation work studies the robustness of Gallium Nitride (GaN) power device. The structures of many GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness. Based on the device structure, this dissertation is divided into two parts: The first half discusses the robustness of lateral GaN high electron mobility transistor (HEMT), which recently sees rapid adoption among wide range of applications such as the power adapter and chargers, data center, and photovoltaic panels. The absence of p-n junction between the source and drain of GaN HEMT results in the lack of avalanche mechanism. This raises a concern on the device capability of withstanding surge-energy or overvoltage stress, which hinders the penetration of GaN HEMTs in broader applications. To address this concern, the study begins with conducting the single-event unclamped inductive switching (UIS) test on two mainstream commercial p-gate GaN HEMTs with the Ohmic- and Schottky-type gate contacts, where the GaN HEMT is found to withstand surge energy through a resonant energy transfer between the device capacitance and the loop inductance. The failure mechanism is identified to be a pure electrical breakdown determined by device transient breakdown voltage (BV). The BV of GaN HEMT is further found to be "dynamic" from the switching tests with various pulse widths and frequencies, which is further explained by the time-dependent buffer trapping. This dynamic BV (BVDYN) phenomenon indicates that the static or single-pulse test may not reveal the true BV of GaN HEMT in high frequency switching applications. To address this gap, a novel testbed based on a zero-voltage-switching converter with an active clamping circuit is developed to enable the stable switching with kilovolt overvoltage and megahertz frequency. The overvoltage failure boundaries and failure mechanisms of four commercial p-gate GaN HEMTs from multiple vendors are explored. In addition to the frequency-dependent BVDYN, two new failure mechanisms are observed in some devices, which are attributable to the serious carrier trapping in GaN HEMTs under the high-frequency overvoltage switching. At last, based on the findings in the high frequency overvoltage test (HFOT), a physics-based lifetime model for commercial GaN HEMTs utilizing the device on resistance (RON) shift is established and validated by experimental results. Overall, the switching-based test methodology and experimental results provide critical references for the overvoltage protection and qualification of GaN power HEMTs. The second half of the dissertation discusses the robustness of the vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercialized GaN power device with the p-n junction embedded between the gate and drain which enables the avalanche breakdown. The robustness study on GaN JFET follows similar test approaches as Si metal-oxide-semiconductor field-effect transistor (MOSFET) with two key interests: the avalanche and short circuit capabilities. The avalanche breakdown is first explored via the single-event and repetitive UIS tests and under various gate drivers, from which an interesting "avalanche-through-fin-channel" mechanism is discovered. By leveraging this avalanche path, the electro-thermal stress migrates from the main blocking p-n junction to the n-GaN fin channel, resulting in a very favorable failure-to-open-circuit signature. The single-pulse critical avalanche energy density (EAVA) of vertical GaN Fin-JFET is measured to be as high as 10 J/cm2, which is much higher than the Si MOSFET and comparable to the SiC MOSFET. The short circuit capability is explored utilizing the hard-switching fault on the 650-V rated GaN Fin-JFET, with a gate driving circuit identical to the switching application to best mimic device operation in converters. The short circuit withstanding time is measured to be 30.5 µs at an input voltage of 400 V, 17.0 µs at 600 V, and 11.6 µs at 800 V, all among the longest reported for 600-700 V normally-off transistors. In addition, the failure-to-open-circuit signature is also shown in the single-event and repetitive short circuit tests; all devices retain the avalanche breakdown after failure, which is highly desirable for system applications. These results suggest that, while GaN HEMT is already available in market, vertical GaN Fin-JFET shows superior avalanche and short-circuit robustness and thereby can unlock great potential of GaN devices for applications like automotive powertrains, motor drives, and grids. / Doctor of Philosophy / In recent years, many power electronics applications such as data centers and electric vehicles have witnessed a rapid increase in the adoption of wide bandgap (WBG) power devices. The Gallium Nitride (GaN) device is one of the most attractive candidates in WBG devices, owing to its good tradeoff between breakdown voltage and on resistance, as well as the small gate charge that enables high frequency switching. For power devices, their robustness against overvoltage and overcurrent stresses is as important as their performance under normal operations. However, the new material, new device structure, and new device physics in GaN power devices brought up many open knowledge gaps in their robustness study, particularly under the dynamic operation in switching circuits. This dissertation presents the work in exploring the robustness of GaN power devices. Based on the device structure, the discussion is divided in two parts: The first half of the dissertation focuses on the overvoltage robustness of the lateral GaN High Electron Mobility Transistor (HEMT), the commercially available device covering 30 to 900 V voltage classes. A key feature of this device is the lack of p-n junction between source and drain, leading to an absence of avalanche capability. The study is conducted on mainstream, commercial p-gate GaN HEMTs, with a combination of circuit testing, microscale failure analysis, and physics-based device simulation. The main contribution is on three aspects: identifying the single-event and high-frequency repetitive overvoltage boundaries of GaN HEMT, unveiling the failure and degradation mechanisms under transient overvoltage conditions, and providing guidelines to GaN HEMT device users with proper robustness test methodology for device qualification and screening. The second half of the dissertation focuses on the robustness of vertical GaN fin-channel junction field effect transistor (Fin-JFET), a promising pre-commercial GaN power device with the p-n junction implemented between the source and drain. The robustness tests follow the classic approaches deployed for Silicon power devices, where both the avalanche and short circuit capabilities are investigated. From the single-event and repetitive test results, the GaN JFET shows excellent avalanche robustness with a desirable failure-to-open-circuit behavior, as well as a critical avalanche energy (EAVA) of 10 J/cm2 that is higher than the Silicon metal-oxide-semiconductor field-effect transistor (MOSFET) and comparable to the Silicon Carbide MOSFET. For a 650-V rated GaN Fin-JFET, a record high 30.5 μs short circuit time is demonstrated under the hard-switching fault condition at 400 V input voltage. Overall, the results show great potential of GaN power devices for the power electronics applications that involve more stressful operation conditions for devices.

Gallium Nitride (GaN) based transistors have been in the spotlight for power electronics due to promising properties like high bandgap, high breakdown field, high electron mobility, and high-frequency applications. While there are some commercial devices based on these transistors available, there is still room for improvement in these devices for widespread usage. In this project, GaN-based transistors fabricated at RISE AB were investigated. These devices had previously shown high leakage current. Different approaches taken to reduce the said leakage current were analysed. The main scope of the thesis was static electrical testing of a new batch of these transistors at room temperature, mainly investigating their leakage current. The new transistors were subjected to surface treatments and also a new in-situ dielectric layer was used. The surface treatments did not show much improvement but the in-situ grown dielectric showed almost half of the initial leakage current. In addition to this different device architectures with varying gate length, gate width, and gate to drain distance were tested and compared. It was found that devices with 3 μm gate length and 12 μm gate to drain distance showed the best performance. The blocking characteristic of the transistors was also tested and the devices could withstand up to 350V. Suggestions to further identify the sources of the leakage current are presented. Possible improvement in the design of the transistors to increase the blocking voltage is also described. / Transistorer baserade på galliumnitrid (GaN) har varit i strålkastaren för kraftelektronik på grund av lovande egenskaper som högt bandgap, högt nedbrytningsfält, hög elektronmobilitet. Dessa egenskaper gör materialet synnerligen lämpligt för komponentapplikationer vid höga effekter och, framför allt, höga frekvenser. Även om det finns några kommersiella applikationer baserade på dessa transistorer finns det fortfarande stort utrymme för förbättringar. I detta projekt undersöktes GaN-baserade transistorer tillverkade vid RISE AB. Dessa komponenter hade tidigare visat hög läckström och olika tillvägagångssätt för att minska nämnda läckström har analyserats. Transistorerna i detta projekt var ytbehandlade på ett nytt sätt och dielektirkat i styrelektroden var ocskå tillverkat på ett nytt sätt. Ytbehandlingarna visade inte mycket förbättring men det dielektrikat visade nästan hälften av den initiala läckströmmen. Utöver detta testades och jämfördes olika layouter med varierande geometri, gate-längd, gate-bredd och avstånd mellan gate/source. Det visade sig att komponenter med 3 μm gate-längd och 12 μm mellan gate och drain visade bästa prestanda. Transistorernas blockeringskaraktäristik testades också och visade sig tåla upp till 350V. Förslag för att ytterligare identifiera källorna till läckströmmen presenteras. Eventuell förbättring av utformningen av transistorerna för att öka blockeringsspänningen beskrivs också.

Gallium nitride (GaN) based high electron mobility transistors (HEMTs) are promising for power electronic applications due to their high breakdown voltage and power efficiency compared to Si-based power devices. As known, the design of the HEMT has high impact on the performance of the devices. In this project various GaN HEMTs on SiC substrate with different design configurations are characterized and investigated. These HEMTs are designed and fabricated by the Research Institutes of Sweden (RISE). The important properties of the HEMTs such as contact resistance, current density, capacitance, and breakdown voltage are characterized and emphasized. The uniformity of the contact resistance of the devices located across a 4’’ wafer is investigated, which reveals the lowest contact resistance of 4.3Ω·mm at the center of the wafer. The highest maximum current density of the devices is 1.15A/mm, and the maximum current scales with the gate dimensions of the devices. The gate capacitance of the devices is between 0.1 and 0.6pF under 1MHz. The gate insulation breakdown voltage of the devices is above 40V and the drain to source breakdown voltage is higher than 360V. Based on the results, discussions about the effects of the designs on the device performance are provided. Suggestions for further improvement of the device performance are given. / Galliumnitrid (GaN) baserade högelektronmobilitetstransistorer (HEMTs) är lovande för kraftelektroniska applikationer på grund av deras höga nedbrytningsspänning och effektivitet jämfört med Si-baserade kraftenheter. Som känt har designen av HEMT stor inverkan på enheternas prestanda. I detta projekt karakteriseras och undersöks olika GaN HEMTs på SiC-substrat med olika designkonfigurationer. Dessa HEMTs är designade och tillverkade av Sveriges forskningsins titut (RISE). De viktiga egenskaperna hos HEMTs såsom kontaktmotstånd, strömtäthet, kapacitans och nedbrytningsspänning karakteriseras och betonas. Enhetligheten i kontaktmotståndet för enheterna som är placerade över en 4'' skiva undersöks, vilket avslöjar det lägsta kontaktmotståndet på 4.3 Ω·mm i mitten av skivan. Den högsta maximala strömtätheten för enheterna är 1.15A/mm, och den maximala strömskalan med enheternas grindmått. Portens kapacitans för enheterna är mellan 0.1 och 0.6pF under 1MHz. Enhetsspänningen för grindisoleringen för enheterna är över 40V och avloppsspänningen till källan är högre än 360V. Baserat på resultaten ges diskussioner om designens effekter på enhetens prestanda. Förslag för ytterligare förbättring av enhetens prestanda ges.

Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. The primary design target of a unipolar power device is to achieve low on-resistance and high breakdown voltage. Although GaN high electron mobility transistor (HEMT) is commercially available in a voltage class from 15 V to 900 V, the performance of GaN devices is still far below the GaN material limit, due to several reasons: 1) To achieve the normally-off operation in a GaN HEMT, the density of two-dimensional electron gas (2DEG) channel cannot be too high; this limits the on-resistance reduction in the access region. 2) The gate capacitance of GaN HEMT is usually low so that the carrier concentration in the channel underneath the gate is relatively low, limiting the on-resistance reduction in the gated channel region. 3) The electric-field distribution in the drift region is not uniform, resulting in a limited breakdown voltage. We proposed to use the junction-based structure in GaN power devices to address the above problems and fully exploit GaN's material properties. The first part of this dissertation characterizes nickel oxide (NiO) as a p-type material to construct the junction-based GaN power devices. Although the homogenous p-GaN/n-GaN junction is preferred in many devices, the selective-area, p-GaN regrowth can lead to excessive leakage current; in comparison, the p-NiO/n-GaN junction is stable without leakage. This section describes the optimization of NiO deposition as well as the NiO characterization. Although acceptor in NiO is not generated by impurity doping, the acceptor concentration modulation is realized by tuning the O2 partial pressure during the sputtering process. Practical breakdown electric field is also characterized and confirmed to be higher than GaN. These results provide the design guidelines for NiO-GaN junction-based power devices. The second part of this dissertation demonstrates the 3D NiO-GaN junction gate to improve the GaN HEMT's on-resistance. The 3D junction gate structure enables a high carrier concentration under the gate region in the device on-state. Meanwhile, the strong depletion effect of the junction-based gate allows for a robust normally-off operation; as a result, the GaN wafer with a higher 2DEG concentration can be used to achieve both normally-off and low on-state resistance in HEMT devices. Simulation is also performed to project the performance space of trigate GaN junction HEMTs using the p-GaN instead of NiO. The third part of this dissertation presents the application of the p-GaN/n-GaN junction in the drift region of the multi-channel lateral devices to achieve the high breakdown voltage. Here p-GaN is grown in-situ with the multi-channel AlGaN/GaN structure, and there is no leakage problem. The structure is designed to achieve charge balance between the acceptor in p-GaN and the net donor in the multichannel AlGaN/GaN. This design enables a uniform electric field distribution and breakdown voltage over 10 kV. The fourth part of this dissertation presents the application of the p-NiO/n-GaN junction in vertical superjunction (SJ) devices. We show the design and simulation of this heterojunction structure in a SJ and confirm the uniform electric field and high breakdown voltage under the charge balance. Then the device fabrication is presented in detail, which mainly comprises the deep GaN trench etch, NiO self-aligned lift off, and photoresist trench planarization. The optimized device shows a trade-off between its drift region specific on-resistance versus breakdown that exceeds the 1D GaN's limit. The last part of this dissertation is exploring the design and fabrication of p-GaN/n-GaN based SJ devices. First, the challenges in p-GaN regrowth especially the introduction of interface impurities are discussed, followed by device simulation and modeling to optimize the SJ performance considering these interface impurities. The activation of regrown p-GaN in deep trenches is more difficult than planar p-GaN, and we present the characterization and physical model for the activation of the deep buried p-GaN. Last, the results of p-GaN filling regrowth and the acceptor concentration calibration in the lightly doped p-GaN are presented and discussed. In summary, our work combines experimental device fabrication and characterization, TCAD simulation, and device modeling to demonstrate the benefit of multi-dimensional, junction-based GaN power devices as compared to the traditional GaN power devices. The junction-based structure at gate region can provides stable normally-off operation and low on-resistance. When being applied to the drift region, the multidimensional junction structure can push the device specific on-resistance versus breakdown voltage trade-off near or even exceeding the material limit. These results will advance the performance and application spaces of GaN power devices. / Doctor of Philosophy / Power electronics plays an important role in many energy conversion applications in modern society including consumer electronics, data centers, electric vehicles, and power grids, etc. The key components of power electronic circuits are power semiconductor devices including diodes and transistors, which determine the performance of power electronics circuits. Traditional power devices are based on the semiconductor silicon (Si), which have already reached the silicon's material limit. Gallium nitride (GaN) is a wide bandgap semiconductor with high electron mobility and high critical electric field. GaN-based power devices promise superior device performance over the Si-based counterpart. Currently, GaN power devices performance is still far below its material limit due to several reasons: 1) To achieve normally-off operation, the carriers at gate region need to be fully depleted at zero bias. Due to a relatively limited depletion capability of the planar gate, the normally-off operation poses an upper limit on the channel carrier density, which increases the device on-resistance. 2) The electric field distribution is not uniform when the device is blocking off-state voltage, and the crowded electric field will cause the device premature breakdown. This work proposed to use multi-dimensional, p-n junction-based device structure to overcome the above challenges. The devices with diverse structures are fabricated, characterized, and compared with the commercially available devices. The multi-dimensional, junction-based gate structure provides strong electrostatic control to realize normally-off operation and allow for higher carrier concentration and lower on-resistance. The devices with multi-dimensional, junction-based drift region enables the uniform electric field distribution at the device off-state, allowing devices to block high voltage without compromising the on-state resistance. Examples of such devices investigated in this dissertation include the tri-gate junction transistors, reduced-surface-field (RESURF) diodes, and superjunction diodes. In summary, this work demonstrates the multi-dimensional, junction-based device structure to overcome the performance limitations of planar devices and fully exploit GaN's material benefits for power devices. The multi-dimensional, junction-based devices are experimentally fabricated and characterized, manifesting the superior performance over traditional GaN devices. This work will significantly boost the performance and application space of GaN power devices.

The largest 21st century radio telescope, the Square Kilometre Array (SKA) is now being planned, and the first phase of construction is estimated to commence in the year 2016. Phased array technology, the key feature of the SKA, requires the use of a tremendous number of receivers, estimated at approximately 37 million. Therefore, in the context of this project, the Low Noise Amplifier (LNA) located at the front end of the receiver chain remains the critical block. The demanding specifications in terms of bandwidth, low power consumption, low cost and low noise characteristics make the LNA topologies and their design methodologies one of the most challenging tasks for the realisation of the SKA. The LNA design is a compromise between the topology selection, wideband matching for a low noise figure, low power consumption and linearity. Considering these critical issues, this thesis describes the procedure for designing a monolithic microwave integrated circuit (MMIC) LNA for operation in the mid frequency band (400 MHz to 1.4 GHz) of the SKA. The main focus of this work is to investigate the potential of MMIC LNA designs based on a novel InGaAs/InAlAs/InP pHEMT developed for 1 µm gate length transistors, fabricated at The University of Manchester. An accurate technique for the extraction of empirical linear and nonlinear models for the fabricated active devices has been developed. In addition to the linear and nonlinear model of the transistors, precise models for passive devices have also been obtained and incorporated in the design of the amplifiers. The models show excellent agreement between measured and modelled DC and RF data. These models have been used in designing single, double and differential stage MMIC LNAs. The LNAs were designed for a 50 Ω input and output impedance. The excellent fits between the measured and modelled S-parameters for single and double stage single-ended LNAs reflects the accurate models that have been developed. The single stage LNA achieved a gain ranging from 9 to 13 dB over the band of operation. The gain was increased between 27 dB and 36 dB for the double stage and differential LNA designs. The measured noise figures obtained were higher by ~0.3 to ~0.8 dB when compared to the simulated figures. This is due to several factors which are discussed in this thesis. The single stage design consumes only a third of the power (47 mW) of that required for the double stage design, when driven from a 3 V supply. All designs were unconditionally stable. The chip sizes of the fabricated MMIC LNAs were 1.5 x 1.5 mm2 and 1.6 x 2.5 mm2 for the single and double stage designs respectively. Significantly, a series of differential input to single-ended output LNAs became of interest for use in the Square Kilometre Array (SKA), as it utilises differential output antennas in some of its configurations. The single-ended output is preferable for interfacing to the subsequent stages in the analogue chain. A noise figure of less than 0.9 dB with a power consumption of 180 mW is expected for these designs.

Les matériaux III-N sont présents dans la vie quotidienne pour des applications optoélectroniques (diodes électroluminescentes, lasers). Les propriétés remarquables du GaN (grand gap, grand champ de claquage, champ de polarisation élevé, vitesse de saturation des électrons importante…) en font un candidat de choix pour des applications en électronique de puissance à basse fréquence, mais aussi à haute fréquence, par exemple en gamme d'ondes millimétriques. L’enjeu de ce travail de thèse consiste à augmenter la fréquence de travail des transistors tout en maintenant une puissance élevée. Pour cela, des hétérostructures HEMTs (High Electron Mobility Transistors) sont développées et les épaisseurs de cap et de barrière doivent être réduites, bien que ceci soit au détriment de la puissance délivrée. Une étude sera donc menée sur l’influence des épaisseurs de cap et de barrière ainsi que le type de barrière (AlGaN, AlN et InAlN) de manière à isoler les hétérostructures offrant le meilleur compromis en termes de fréquence et de puissance. De plus, les moyens mis en œuvre pour augmenter la fréquence de travail entrainent une dégradation du confinement des électrons du canal. De manière à limiter cet effet, une back-barrière est insérée sous le canal. Ceci fera l’objet d’une deuxième étude. Enfin, une étude de la passivation de surface des transistors sera menée. La combinaison des ces trois études permettra d’identifier la structure optimale pour délivrer le plus de puissance à haute fréquence (ici à 40 GHz). / Nitride based materials are present in everyday life for optoelectronic applications (light emitting diodes, lasers). GaN remarkable properties (like large energy band gap, high breakdown electric field, high polarization field, high electronic saturation velocity…) make it a promising candidate for low frequency power electronic applications, but also for high frequency like microwaves range for example. The aim of this work is to increase the transistors working frequency by keeping a high power. To do this, high electron mobility transistor heterostructures are developed, and cap and barrier thicknesses have to be reduced, although it is detrimental for a high power. A first study deals with the influence of cap and barrier thicknesses as well as the type of barrier (AlGaN, AlN and InAlN), in order to isolate heterostructures offering the best compromise in terms of power and frequency. Moreover, the means implemented to increase the working frequency lead to electron channel confinement degradation. In order limit this effect, a back-barrier is added underneath the channel. It will be the subject of the second study. Finally, a transistor surface passivation study will be led. The combination of those three parts will allow identifying the optimum structure to deliver the highest power at high frequency (here at 40 GHz).

Heterostructures of the materials system GaN/AlGaN/GaN were grown by molecular beam epitaxy on 6H-SiC substrates and high electron mobility transistors (HEMTs) were fabricated. For devices with large gate periphery an air bridge technology was developed for the drain contacts of the finger structure. The devices showed DC drain currents of more than 1 A/mm and values of the transconductance between 120 and 140 mS/mm. A power added efficiency of 41 % was measured on devices with a gate length of 1 µm at 2 GHz and 45 V drain bias. Power values of 8 W/mm were obtained. Devices with submicron gates exhibited power values of 6.1 W/mm (7 GHz) and 3.16 W/mm (25 GHz) respectively. The rf dispersion of the drain current is very low, although the devices were not passivated. / Heterostrukturen im Materialsystem GaN/AlGaN/GaN wurden mittels Molekularstrahlepitaxie auf 6H-SiC-Substraten gewachsen und High-Electron-Mobility-Transistoren (HEMTs) daraus hergestellt. Für Bauelemente mit großer Gateperipherie wurde eine Air-Bridge-Technik entwickelt, um die Drainkontakte der Fingerstruktur zu verbinden. Die Bauelemente zeigten Drainströme von mehr als 1 A/mm und Steilheiten zwischen 120 und 140 mS/mm. An Transistoren mit Gatelängen von 1 µm konnten Leistungswirkungsgrade (Power Added Efficiency) von 41 % (bei 2 GHz und 45 V Drain-Source-Spannung) sowie eine Leistung von 8 W/mm erzielt werden. Bauelemente mit Gatelängen im Submikrometerbereich zeigten Leistungswerte von 6,1 W/mm (7 GHz) bzw. 3,16 W/mm (25 GHz). Die Drainstromdispersion ist sehr gering, obwohl die Bauelemente nicht passiviert wurden.

GaN-HEMTs (Gallium Nitride-based High Electron Mobility Transistors) have, thanks to the large band gap of GaN, electrical properties that are suitable for applications of high electrical voltages, high currents, and fast switching. The large band gap also gives GaN-HEMTs a high resistance to radiation. In this degree project, the effects of 2 MeV proton irradiation of GaN-HEMTs constructed on both silicon carbide and silicon substrates are investigated. 20 transistors per substrate were irradiated in the particle accelerator 5 MV NEC Pelletron in the Ångström laboratory at Uppsala University. These transistors were exposed to radiation doses in the range of 10^11 to 10^15 protons/cm^2. The analysis shows that both transistors on silicon, as well as silicon carbide, are unaffected by proton irradiation up to a dose of 10^14 protons/cm^2. GaN-on-Si transistors show less influence of radiation than GaN-on-SiC transistors. The capacitances between gate and drain as well as drain and source for both GaN-on-SiC and GaN-on-Si HEMTs show hysteresis as a function of forward and backward gate voltage sweeps for the radiation dose of 10^15 protons/cm^2. / GaN-HEMTs (Galliumnitridbaserade High Electron Mobility Transistors) har tack vare det stora bandgapet i GaN goda elektriska egenskaper som lämpar sig för höga elektriska spänningar, höga strömmar och snabb växling mellan av- och på-tillstånd. Det stora bandgapet ger även GaN-HEMTs ett stort motstånd mot strålning.I detta examensarbete undersöks effekterna av 2 MeV protonbestrålning av GaN-HEMTs. Dessa HEMTs är konstruerade på både kiselkarbid- och kiselsubstrat.20 transistorer per transistorsubstrat bestrålades i partikelacceleratorn 5 MV NEC Pelletron i Ångströmslaboratoriet vid Uppsala Universitet. Dessa transistorer utsattes för strålningsdoser inom intervallet 10^11 till 10^15 protoner/cm^2. Resultaten visar att både tranisistorer på kisel såsom kiselkarbid är opåverkade av strålning upp till en dos av 10^14 protoner/cm^2. GaN-på-Si-transistorer visar en mindre påverkan av protonstrålning än GaN-på-SiC-transistorer. Ytterligare uppstod hysteresis för kapacitanser mellan gate och drain och mellan gate och source som en funktion av fram- och bakriktad gate-spänning efter en strålningsdos av 10^15 protoner/cm^2.

Le projet industriel français MEGaN vise le développement de module de puissance à base de compostant HEMT en GaN. Une des application industrielle concerne l’aéronautique avec une forte contrainte en isolation galvanique (>100 kV/s) et en température ambiante (200°C). Le travail de thèse a été concentré sur une brique module de puissance (bras d’onduleur 650 V 30 A). L’objectif est d’atteindre un prototype de facteur de forme peu épais, 30 cm2 et embarquant l’ensemble des fonctions driver, alimentation de driver, la capacité de bus et capteur de courant phase. Cet objectif implique un fort rendement énergétique, et le respect de l’isolation galvanique alors que la contrainte en surface est forte. Le manuscrit, outre l’état de l’art relatif au module de puissance et notamment celui à base de transistor GaN HEMT, aborde une solution d’isolation de signaux de commande à base de micro-transformateur. Des prototypes de micro-transformateur ont été caractérisés et vieillis pendant 3000 H pour évaluer la robustesse de la solution. Les travaux ont contribué à la caractérisation de plusieurs composants GaN afin de mûrir des modèles pour la simulation circuit de topologie de convertisseur. Au sein du travail collaboratif MEGaN, notre contribution ne concernait pas la conception du circuit intégré (driver de grille), tout en ayant participé à la validation des spécifications, mais une stratégie d’alimentation du driver de grille. Une première proposition d’alimentation isolée pour le driver de grille a privilégié l’utilisation de composants GaN basse-tension. La topologie Flyback résonante avec clamp permet de tirer le meilleur parti de ces composants GaN mais pose la contrainte du transformateur de puissance. Plusieurs technologies pour la réalisation du transformateur ont été validées expérimentalement et notamment une proposition originale enfouissement du composant magnétique au sein d’un substrat polymère haute-température. En particulier, un procédé de fabrication peu onéreux permet d’obtenir un dispositif fiable (1000 H de cyclage entre - 55 ; + 200°C), avec un rendement intrinsèque de 88 % pour 2 W transférés. La capacité parasite d’isolation est réduite par rapport aux prototypes précédent. Deux prototypes d’alimentations à forte intégration utilisent soit les transistors GaN basse tension (2.4 MHz, 2 W, 74 %, 6 cm2), soit un circuit intégré dédié en technologie CMOS SOI, conçu pour l’application (1.2 MHz, 2 W, 77 %, 8.5 cm2). Le manuscrit propose par la suite une solution intégrable de mesure de courant de phase du bras de pont, basé sur une magnétorésistance. La comparaison expérimentale vis à vis d’une solution à résistance de shunt. Enfin, deux prototypes de convertisseur sont décrits, dont une a pu faire l’objet d’une validation expérimentale démontrant des pertes en commutation réduites. / The french industrial project MEGaN targets the development of power module based on GaN HEMT transistors. One of the industrial applications is the aeronautics field with a high-constraint on the galvanic isolation (>100 kV/s) and ambient temperature (200°C). The intent of this work is the power module block (3 phases inverter 650 V 30 A). The goal is to obtain a small footprint module, 30 cm2, with necessary functions such as gate driver, gate driver power supply, bulk capacitor and current phase sensor. This goal implies high efficiency as well as respect of the constraint of galvanic isolation with an optimized volume. This dissertation, besides the state of the art of power modules and especially the GaN HEMT ones, addressed a control signal isolation solution based on coreless transformers. Different prototypes based on coreless transformers were characterized and verified over 3000 hours in order to evaluate their robustness. The different studies realized the characterization of the different market available GaN HEMTs in order to mature a circuit simulation model for various converter topologies. In the collaborative work of the project, our contribution did not focus on the gate driver chip design even if experimental evaluation work was made, but a gate driver power supply strategy. The first gate driver isolated power supply design proposition focused on the low-voltage GaN HEMT conversion. The active-clamp Flyback topology allows to have the best trade-off between the GaN transistors and the isolation constraint of the transformer. Different transformer topolgies were experimentally performed and a novel PCB embedded transformer process was proposed with high-temperature capability. A lamination process was proposed for its cost-efficiency and for the reliability of the prototype (1000 H cycling test between - 55; + 200°C), with 88 % intrinsic efficiency. However, the transformer isolation capacitance was drastically reduced compared to the previous prototypes. 2 high-integrated gate driver power supply prototypes were designed with: GaN transistors (2.4 MHz, 2 W, 74 %, 6 cm2), and with a CMOS SOI dedicated chip (1.2 MHz, 2 W, 77 %, 8.5 cm2). In the last chapter, this dissertation presents an easily integrated solution for a phase current sensor based on the magnetoresistance component. The comparison between shunt resistor and magnetoresistance is experimentally performed. Finally, two inverter prototypes are presented, with one multi-level gate driver dedicated for GaN HEMT showing small switching loss performance.