As computer systems become increasingly complex and diverse, so too do the architectures they implement. This leads to an increase in complexity in the tools used to design new hardware and software. One particularly important tool in hardware and software design is the Instruction Set Simulator, which is used to prototype new architectures and hardware features, verify hardware, and test and debug software. Many Architecture Description Languages exist which facilitate the description of new architectural or hardware features, and generate a tools such as simulators. However, these typically suffer from poor performance, are difficult to test effectively, and may be limited in functionality. This thesis considers three objectives when developing Instruction Set Simulators: performance, correctness, and completeness, and presents techniques which contribute to each of these. Performance is obtained by combining Dynamic Binary Translation techniques with a novel analysis of high level architecture descriptions. This makes use of partial evaluation techniques in order to both improve the translation system, and to improve the quality of the translated code, leading a performance improvement of over 2.5x compared to a naïve implementation. This thesis also presents techniques which contribute to the correctness objective. Each possible behaviour of each described instruction is used to guide the generation of a test case. Constraint satisfaction techniques are used to determine the necessary instruction encoding and context for each behaviour to be produced. It is shown that this is a significant improvement over benchmark-driven testing, and this technique has led to the discovery of several bugs and inconsistencies in multiple state of the art instruction set simulators. Finally, several challenges in ‘Full System’ simulation are addressed, contributing to both the performance and completeness objectives. Full System simulation generally carries significant performance costs compared with other simulation strategies. Crucially, instructions which access memory require virtual to physical address translation and can now cause exceptions. Both of these processes must be correctly and efficiently handled by the simulator. This thesis presents novel techniques to address this issue which provide up to a 1.65x speedup over a state of the art solution.

Dynamic balancing of computation and communication load is vital for the execution stability and performance of distributed, parallel simulations deployed on shared, unreliable resources of large-scale environments. High Level Architecture (HLA) based simulations can experience a decrease in performance due to imbalances that are produced initially and/or during run-time. These imbalances are generated by the dynamic load changes of distributed simulations or by unknown, non-managed background processes resulting from the non-dedication of shared resources. Due to the dynamic execution characteristics of elements that compose distributed simulation applications, the computational load and interaction dependencies of each simulation entity change during run-time. These dynamic changes lead to an irregular load and communication distribution, which increases overhead of resources and execution delays. A static partitioning of load is limited to deterministic applications and is incapable of predicting the dynamic changes caused by distributed applications or by external background processes. Due to the relevance in dynamically balancing load for distributed simulations, many balancing approaches have been proposed in order to offer a sub-optimal balancing solution, but they are limited to certain simulation aspects, specific to determined applications, or unaware of HLA-based simulation characteristics. Therefore, schemes for balancing the communication and computational load during the execution of distributed simulations are devised, adopting a hierarchical architecture. First, in order to enable the development of such balancing schemes, a migration technique is also employed to perform reliable and low-latency simulation load transfers. Then, a centralized balancing scheme is designed; this scheme employs local and cluster monitoring mechanisms in order to observe the distributed load changes and identify imbalances, and it uses load reallocation policies to determine a distribution of load and minimize imbalances. As a measure to overcome the drawbacks of this scheme, such as bottlenecks, overheads, global synchronization, and single point of failure, a distributed redistribution algorithm is designed. Extensions of the distributed balancing scheme are also developed to improve the detection of and the reaction to load imbalances. These extensions introduce communication delay detection, migration latency awareness, self-adaptation, and load oscillation prediction in the load redistribution algorithm. Such developed balancing systems successfully improved the use of shared resources and increased distributed simulations' performance.

The major sources of power dissipation in a nanometer CMOS circuit are capacitive switching, short-circuit current, static leakage and gate oxide tunneling. However, with the aggressive scaling of technology the gate oxide direct tunneling current (gate leakage) is emerging as a prominent component of power dissipation. For sub-65 nm CMOS technology where the gate oxide (SiO2) thickness is very low, the direct tunneling current is the major form of tunneling. There are two contribution parts in this thesis: analytical modeling of behavioral level components for direct tunneling current and propagation delay, and the reduction of tunneling current during behavioral synthesis. Gate oxides of multiple thicknesses are useful in reducing the gate leakage dissipation. Analytical models from first principles to calculate the tunneling current and the propagation delay of behavioral level components is presented, which are backed by BSIM4/5 models and SPICE simulations. These components are characterized for 45 nm technology and an algorithm is provided for scheduling of datapath operations such that the overall tunneling current dissipation of a datapath circuit under design is minimal. It is observed that the oxide thickness that is being considered is very low it may not remain constant during the course of fabrication. Hence the algorithm takes process variation into consideration. Extensive experiments are conducted for various behavioral level benchmarks under various constraints and observed significant reductions, as high as 75.3% (with an average of 64.3%).

The primary purpose of this research was to improve the accuracy and robustness of pipeline transient modeling. An algorithm was developed to model the transient flow in closed tubes for thin walled pipelines. Emphasis was given to the application of this type of flow to pipelines with small radius 90° elbows. An additional loss term was developed to account for the presence of 90° elbows in a pipeline. The algorithm was integrated into an optimization routine to fit results from the improved model to experimental data. A web based interface was developed to facilitate the pre- and post- processing operations. Results showed that including a loss term that represents the effects of 90° elbows in the Method of Characteristics (MOC) [1] improves the accuracy of the predicted transients by an order of magnitude. Secondary objectives of pump optimization, blockage detection and removal were investigated with promising results.

A estatura é um dos atributos físicos de grande destaque para o homem e para a mulher e, dependendo do meio ou da cultura, é valorizada de diferentes formas. Quando se faz referência ao esporte e a atletas de alto nível, a primeira imagem que nos vem à mente é a de uma figura alta e forte. No entanto, na Ginástica Artística (GA), especialmente no setor feminino, a maioria das ?grandes? campeãs apresenta uma característica em comum: a estatura baixa. No Brasil, a população em geral acredita que o fato se deve ao treinamento intensivo da modalidade. Conseqüentemente, pais chegam a proibir que as filhas pratiquem a modalidade preocupados com o comprometimento da estatura adulta. Até o momento, os estudos científicos realizados têm demonstrado que os aspectos biomecânicos, a rigorosa seleção natural e, principalmente, fatores hereditários provavelmente sejam os maiores responsáveis pela estatura baixa das ginastas. No entanto, a maioria desses estudos são realizados com atletas pré-púberes e adolescentes que estão em plena fase de crescimento. A falta de estudos conclusivos e especialmente relacionados à fase adulta das ginastas, mesmo no contexto internacional, contribui para a perpetuação do mito da estatura baixa na GA em alguns países como o Brasil. Assim, é preciso conduzir estudos específicos e em maior profundidade a fim de verificar se há ou não comprometimento da estatura final da ginasta de alto nível na fase adulta devido ao treinamento. Estudos que relacionem o crescimento estatural com ênfase na fase adulta da atleta de GA ainda não foram encontrados na nossa literatura. Além de raros, inclusive no contexto internacional, essas pesquisas são necessárias para esclarecer dúvidas e levantar evidências que possam justificar ou quebrar o mito relacionado à modalidade. O objetivo da nossa pesquisa foi levantar dados referentes à estatura de ex-ginastas e ginastas adultas de alto nível no Brasil, para verificar possíveis evidências de que o potencial hereditário estabelecido para estatura adulta tenha sido prejudicado devido ao treinamento de alto nível na Ginástica Artística. Utilizou-se o método quantitativo para comparação dos dados familiares referentes à estatura e maturação de 45 ex-ginastas e 06 ginastas em atividade com idade mínima de 18 anos. Os nossos resultados demonstraram que a estatura da ginasta de alto nível no Brasil está dentro da normalidade de acordo com os órgãos oficiais que estabelecem os referenciais para estatura em cada faixa etária. Evidenciaram também estreita relação entre a estatura média dos pais e a estatura final das ginastas, fator também observado na comparação entre as ginastas e respectivas irmãs, indicando que, aparentemente, o potencial genético ou fator hereditário estabelecido para a estatura não foi prejudicado em decorrência do treinamento de alto nível na Ginástica Artística / The stature is one of the physical attributes of great prominence for the man and for the woman and depending on the means or the culture it is valued in different ways. When reference is done to the sport and athletes of high level the first image that it comes to mind is of one that is tall and strong. However, in the artistic gymnastics (GA), especially in the feminine section, most of the \"great\" champions present a characteristic in common: the low stature. In Brazil, the population, in general believes, that the fact is due to the intensive training of the modality. Consequently, parents even prohibit their daughters to practice the modality worried about the compromising of the adult stature. Until the moment, the accomplished scientific studies have demonstrated that the aspects biomechanics, the rigorous natural selection and, mainly, hereditary factors are probably the largest responsible for the low stature of the gymnasts. However, most of these studies are accomplished with prepubescent and adolescent athletes that are in the middle of the growth phase. The lack of conclusive studies and especially related to the adult phase of the gymnasts, even in the international context, they contribute to the perpetuation of the myth of the low stature in GA in some countries, as Brazil. So, it is necessary to drive specific studies in larger depth in order to verify if there is or not compromising in the final stature of the gymnast of high level in the adult phase due to the training. Studies which are related to height growth with emphasis in the athletes of GA adult phase still were not found in our literature. Besides being rare, also in the international context, these studies are necessary to explain doubts and evidences that can justify to raise or to break the myth related to the modality. The objective of our research was to lift data regarding the stature of former-gymnasts and adult gymnasts of high level in Brazil, to verify possible evidences that the established hereditary potential for adult stature has been harmed due to the training of high level in the Artistic Gymnastics. The quantitative method was used for comparison of the family data regarding the stature and maturation of 45 former-gymnasts and 06 gymnasts in activity with minimum age 18 years old. Our results demonstrated that the stature of the gymnast of high level in Brazil is in the normality in accordance with the official organs which establish the reference for stature in each age group. It was also evidenced the narrow relationship between the parents medium stature and the final stature of the gymnasts, fact also observed in the stature in comparison with the gymnasts and respective sisters, indicating that seemingly, the genetic potential or established hereditary factor for the stature were not harmed due to the training of high level in the artistic gymnastics

Today's society is increasingly software-driven and dependent on powerful computer technology. Therefore it is important that advancements in the low-level processor hardware are made available for exploitation by a growing number of programmers of differing skill level. However, as we are approaching the end of Moore's law, hardware designers are finding new and increasingly complex ways to increase the accessible processor performance. It is getting more and more difficult to effectively target these processing resources without expert knowledge in parallelization, heterogeneous computation, communication, synchronization, and so on. To ensure that the software side can keep up, advanced programming environments and frameworks are needed to bridge the widening gap between hardware and software. One such example is the pattern-centric skeleton programming model and in particular the SkePU project. The work presented in this thesis first redesigns the SkePU framework based on modern C++ variadic template metaprogramming and state-of-the-art compiler technology. It then explores new ways to improve performance: by providing new patterns, improving the data access locality of existing ones, and using both static and dynamic knowledge about program flow. The work combines novel ideas with practical evaluation of the approach on several applications. The advancements also include the first skeleton API that allows variadic skeletons, new data containers, and finally an approach to make skeleton programming more customizable without compromising universal portability. / <p>Ytterligare forskningsfinansiärer: EU H2020 project EXA2PRO (801015); SeRC.</p>

abstract: The following document describes the hardware implementation and analysis of Temporal Interference Mitigation using High-Level Synthesis. As the problem of spectral congestion becomes more chronic and widespread, Electromagnetic radio frequency (RF) based systems are posing as viable solution to this problem. Among the existing RF methods Cooperation based systems have been a solution to a host of congestion problems. One of the most important elements of RF receiver is the spatially adaptive part of the receiver. Temporal Mitigation is vital technique employed at the receiver for signal recovery and future propagation along the radar chain. The computationally intensive parts of temporal mitigation are identified and hardware accelerated. The hardware implementation is based on sequential approach with optimizations applied on the individual components for better performance. An extensive analysis using a range of fixed point data types is performed to find the optimal data type necessary. Finally a hybrid combination of data types for different components of temporal mitigation is proposed based on results from the above analysis. / Dissertation/Thesis / Masters Thesis Computer Engineering 2020

A large number and a variety of sensors and actuators, also known as edge devices of the Internet of Things, belonging to various industries - health care monitoring, home automation, industrial automation, have become prevalent in today's world. These edge devices need to communicate data collected to the central system occasionally and often in burst mode which is then used for monitoring and control purposes. To ensure secure connections, Asymmetric or Public Key Cryptography (PKC) schemes are used in combination with Symmetric Cryptography schemes. RSA (Rivest - Shamir- Adleman) is one of the most prevalent public key cryptosystems, and has computationally intensive operations which might have a high latency when implemented in resource constrained environments. The objective of this thesis is to design an accelerator capable of increasing the speed of execution of the RSA algorithm in such resource constrained environments. The bottleneck of the algorithm is determined by analyzing the performance of the algorithm in various platforms - Intel Linux Machine, Raspberry Pi, Nios soft core processor. In designing the accelerator to speedup bottleneck function, we realize that the accelerator architecture will need to be changed according to the resources available to the accelerator. We use high level synthesis tools to explore the design space of the accelerator by taking into consideration system level aspects like the number of ports available to transfer inputs to the accelerator, the word size of the processor, etc. We also propose a new accelerator architecture for the bottleneck function and the algorithm it implements and compare the area and latency requirements of it with other designs obtained from design space exploration. The functionality of the design proposed is verified and prototyped in Zynq SoC of Xilinx Zedboard.

This thesis describes the design and implementation of an client-server application. This application is used to remote access to models of systems, which are saved on the server. Application also provides editation of the models and their simulation. In the thesis there is a design of Communication Protocol between the client and server too. For the implementation of the client and prototype of the server was used Qt library. Server is realized as a part of existing simulation core (SmallDEVS), which is implemented by Smalltalk.

This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.