MP3 compression format is essential categorized one of the MPEG (Moving Picture Experts Group) standards for digital audio compression nowadays. For its superiority and convenient,MP3 has been widely used in multimedia player and storage application. In this thesis, we use software/hardware co-design methodology to design the MP3 player system. In addition, system level scheduling is adopted to arrange the execute time of SW and HW and significantly reduce the hardware cost under the construct of real-time processing. We can obtain fewer extra hardware cost while attaining the goal of real- time playing system. In order to perform software/hardware partitioning, simulate and analyze the MP3 application program to find out the critical parts with high time complexity and regular computation. These parts with high time complexity, e.g. IMDCT and Poly Phase synthesis filter bank, then are implemented by hardware to achieve better system performance. We use high level synthesis concept to optimize the hardware part and integrate software and hardware¡Asuch that communication between software and hardware can be performed smoothly. Finally, MP3 player system is using verified by hardware¡Bsoftware co- verified methodology on an SoC development platform. In order to build a complete verification environment, we attach extra input and output interfaces to the SoC development platform, e.g. the network card and sound card. Write some driver to drive related peripheral device. Since OS is conducive to the operations between software and hardware, Linux OS is ported to the SoC platform to manage software and hardware resources and drive the peripheral devices.

This thesis puts forth a process for ontology driven distributed simulation through a case study. Ontology is regarded as a domain model, including objects, attributes, methods and object relations. The case study involves trajectory simulation. A trajectory simulation is a piece of software that calculates the flight path and other parameters of a munition, such as its orientation and angular rates, from launch to impact. Formal specification of trajectory simulation domain is available as a domain model in the form of an ontology, called Trajectory Simulation ONTology (TSONT). Ontology driven federation development process proposed in this thesis is executed in three steps. The first step is to analyze the TSONT and to create instances of individuals guided by the requirements of the targeted simulation application, called Puma Trajectory Simulation. Puma is the simulation of a ficticious air-to-ground guided bomb. The second step is to create the High Level Architecture(HLA) Federation Object Model (FOM) using Puma Simulation individuals. FOM will include the required object and interaction definitions to enable information exchange among federation members, including the Puma federate and the Exercise Manager federate. Transformation from the ontology to FOM is realized in two ways: manually, and by using a tool called OWL2OMT. The third step is to implement the Trajectory Simulation federation based on the constructed FOM. Thus, the applicability of developing HLA federates and the federation under the guidance of ontology is demonstrated.

The Effect of Comparative Tests Between Self-questioning Strategy And Cooperative Learning (Group Discussion) on Junior High School Students' Chinese Reading Comprehension Abstract The main purpose of this study was to discuss the effect of comparative tests between self-questioning strategy and cooperative learning (group discussion) on junior high school students' Chinese reading comprehension. The questions explored here were: 1. How did self-questioning strategy influence reading comprehension ability? 2. How did self-questioning strategy and the group discussion of cooperative learning improve and influence reading comprehension ability? 3. How did self-questioning strategy and the group discussion of cooperative learning affect the levels of question types? The study used experimental research method. The subjects were 50 second grade students of junior high. According to the scores of the prior test on "reading comprehension ability," students were divided into an experimental group and a control group, and each one was composed of 25 students. The instrument was "test of reading comprehension ability," and the information acquired was dealt with statistical testing on the basis of t-test. The results were as followings: 1. After receiving the teaching of "self-questioning strategy," students' reading comprehension abilities were improved. 2. After the students in the experimental group received the co-teaching of self-questioning strategy and the group discussion of cooperative learning, their scores of the posttest on "reading comprehension ability" were superior to the scores of the students in the control group. 3. After the students in the experimental group accepted the co-teaching of self-questioning strategy and the group discussion of cooperative learning, their scores of the posttest on "high-level question type" were superior to the scores of the students in the control group. Finally the study discussed the above results in more detail, and provided suggestions and references of further research concerning teaching of the reading comprehension.

How to use self-owned knowledge to face the future challenge and diversity, to absorb the fashion knowledge and to create the more valuable knowledge is the most important issue for the corporation that want to become the multinational corporation. In order to use the superiority of globalization well, the headquarter must transfer the core competency to other subsidiary. However, the topic about cross border knowledge transfer will let the factor become more complexity. The character of industry, the strategies of globalization, the inner organizational competency and the top management team will have serious impact to the meaning of knowledge transfer, and will have influence to the whole structure of knowledge transfer. To find out which factors influence the border knowledge transfer of multinational corporation is the core issue in this research. We got the results by mean of the interaction among the character of industry, the strategies of globalization and the inner organizational competency. Further, we can obtain the mutual relations with human capital of the corporation. Although the influence factors of cross border knowledge transfer are too numerous to count, three subs ructions of entirety are the industry of corporation, the inner organizational competency and the strategies of globalization. According to the qualitative analysis and data collection, the inductive inferences of this research are as following: 1. The factors influence sorts of knowledge transfer (1) The maturer product life cycle is, explicit knowledge is more than tacit knowledge of the cross border knowledge transfer. (2) If the industry technique of corporation is superior, the disposition of capital and resources is nearer centralization and origin of inner competency in the corporation is from high-level executive group. (3) Most tacit knowledge of R&D would be produced by headquarter when the product life cycle lasts longer. (4) The origin of inner competency in the corporation is from high-level executive group, because the corporation has the ¡§market ¡Vaccess¡¨ competency and the inner disposition of capital and resources is nearer centralization. 2. The factors influence model of knowledge transfer (1) The correlation between externalization articulating of cross border knowledge transfer and higher knowledge worker in this industry is straight. (2) More requisite the forces for national responsiveness / differentiation, higher degree the externalization articulating and socialization empathizing of cross-border knowledge transfer are.

<p>Modelica is an equation-based object-oriented language (EOO). PELAB at Linköping University along with the OpenModelica development group, is developing a metamodeling extension, MetaModelica, to this language along with a compiler called the OpenModelica Compiler (OMC).</p><p>The goal of this thesis was to analyze the compiler, extend it with union type support and then write a report about the extension with union types in particular and extension with high level data structures in general, to facilitate further development. </p><p>The implementation made by this thesis was implemented with the goal of keeping the current structure intact and extending case-clauses where possible. The main parts of the extension is implemented by this thesis work but some parts concerning the pattern matching algorithms are still to be extended. The main goal of this is to bootstrap the OpenModelica Compiler, making it able to compile itself although this is still a goal for the future.</p><p>With this thesis I also introduce some guidelines for implementing a new highlevel data structure into the compiler and which modules needs extension.</p>

Title from PDF of title page. / Document formatted into pages; contains 97 pages. / Thesis (M.S.Cp.E.)--University of South Florida, 2003. / Includes bibliographical references. / Text (Electronic thesis) in PDF format. / ABSTRACT: In this thesis, a new tool, named CHESS, is designed and developed for control and data-flow graph (CDFG) extraction and the high-level synthesis of VLSI systems. The tool consists of three individual modules for:(i) CDFG extraction, (ii) scheduling and allocation of the CDFG, and (iii) binding, which are integrated to form a comprehensive high-level synthesis system. The first module for CDFG extraction includes a new algorithm in which certain compiler-level transformations are applied first, followed by a series of behavioral-preserving transformations on the given VHDL description. Experimental results indicate that the proposed conversion tool is quite accurate and fast. The CDFG is fed to the second module which schedules it for resource optimization under a given set of time constraints. The scheduling algorithm is an improvement over the Tabu Search based algorithm described in [6] in terms of execution time. / ABSTRACT: The improvement is achieved by moving the step of identifying mutually exclusive operations to the CDFG extraction phase, which, otherwise, is normally done during scheduling. The last module of the proposed tool implements a new binding algorithm based on a game-theoretic approach. The problem of binding is formulated as a non-cooperative finite game, for which a Nash-Equilibrium function is applied to achieve a power-optimized binding solution. Experimental results for several high-level synthesis benchmarks are presented which establish the efficacy of the proposed synthesis tool. / System requirements: World Wide Web browser and PDF reader. / Mode of access: World Wide Web.

Στην παρούσα διδακτορική διατριβή προτείνονται μεθοδολογίες σχεδίασης εφαρμογών σε ενσωματωμένες πλατφόρμες ειδικού σκοπού για την βελτίωση της απόδοσης εφαρμογών που εκτελούνται σε αυτές. Τα θεωρούμενα συστήματα στοχεύουν σε αριθμητικά απαιτητικές εφαρμογές, όπως είναι εφαρμογές Ψηφιακής Επεξεργασίας Σήματος και πολυμέσων. Οι περιγραφές των εφαρμογών γίνεται σε γλώσσα υψηλού επιπέδου γεγονός που διευκολύνει την υλοποίηση των εφαρμογών στις θεωρούμενες επεξεργαστικές πλατφόρμες. Οι μεθοδολογίες έχουν αυτοματοποιηθεί, με την χρήση πρωτότυπων και εμπορικά διαθέσιμων εργαλείων, για την αποτελεσματική και γρήγορη αποτίμηση των λύσεων σχεδίασης και απεικόνισης. Αρχικά, προτείνεται μια μέθοδος για την αποτελεσματική υλοποίηση εφαρμογών Ψηφιακής Επεξεργασίας Σήματος σε ένα σύστημα μικροεπεξεργαστή που περιέχει σαν επιταχυντή κρίσιμων τμημάτων ένα ευέλικτο χειριστή δεδομένων (data-path). Η υπεροχή του προτεινόμενου data-path σε σχέση με υπάρχοντες χειριστές δεδομένων δείχνεται για ένα σύνολο χαρακτηριστικών αριθμητικών υπολογιστικών πυρήνων (kernels). Παρουσιάζεται μια αυτοματοποιημένη μέθοδος σύνθεσης πυρήνων για το χειριστή δεδομένων. Αυτή η διαδικασία σύνθεσης ενσωματώνεται σε ένα γενικό περιβάλλον σχεδίασης εφαρμογών για το θεωρούμενο σύστημα που έχει σαν στόχο την βελτίωση της απόδοσης και την μείωση κατανάλωση ενέργειας. Στην συνέχεια, παρουσιάζεται ένα περιβάλλον λογισμικού που υλοποιεί μια φορμαλισμένη μεθοδολογία για τον διαχωρισμό εφαρμογών Ψηφιακής Επεξεργασίας Σήματος μεταξύ επαναπροσδιοριζόμενων τμημάτων μικτής υφής για πρώτη φορά στην βιβλιογραφία. Κρίσιμα τμήματα επιταχύνονται στο επαναπροσδιοριζόμενο υλικό χονδροειδούς υφής για να ικανοποιηθούν οι χρονικοί περιορισμοί του κώδικα της εφαρμογής που απεικονίζεται στην επαναπροσδιοριζόμενη λογική του συστήματος. Η επαναπροσδιοριζόμενη λογική λεπτής υφής υλοποιείται από ένα ενσωματωμένο Field Programmable Gate Array (FPGA), ενώ η επαναπροσδιοριζόμενη λογική χονδροειδούς υφής από ένα δικό μας αναπτυγμένο χειριστή +δεδομένων υψηλής απόδοσης. Η αποτελεσματικότητα του πρωτότυπου λογισμικού επιβεβαιώνεται χρησιμοποιώντας ρεαλιστικές εφαρμογές. Αναλυτικά πειράματα δείχνουν σημαντικές βελτιώσεις στην απόδοση, ενώ καθορισμένοι χρονικοί περιορισμοί ικανοποιούνται για όλες τις δοκιμασμένες εφαρμογές. Παρουσιάζεται η ενσωμάτωση ενός προτεινόμενου ευέλικτου προτύπου Επαναπροσδιοριζόμενης Αρχιτεκτονικής Πίνακα (ΕΑΠ) χονδροειδούς υφής σε δύο διαφορετικά συστήματα σε ολοκληρωμένα κυκλώματα. Για την αποτελεσματική εκτέλεση υπολογιστικά απαιτητικών τμημάτων στην ΕΑΠ αναπτύχθηκε μια πρωτότυπη αυτοματοποιημένη διαδικασία απεικόνισης, που βασίζεται σε έναν νέο αλγόριθμο διοχέτευσης βρόχου. Η αποτελεσματικότητα της ΕΑΠ και της αντίστοιχης διαδικασίας απεικόνισης διαπιστώνονται με εκτέλεση ρεαλιστικών εφαρμογών. Στο πρώτο σύστημα η ΕΑΠ μαζί με ένα FPGA σχηματίζουν την επαναπροσδιοριζόμενη λογική μιας υβριδικής πλατφόρμας. Στο δεύτερο σύστημα σε ολοκληρωμένο κύκλωμα, η ΕΑΠ συνδέεται άμεσα με έναν μικροεπεξεργαστή γενικού σκοπού ενεργώντας σαν συνεπεξεργαστής για την εκτέλεση κρίσιμων βρόχων. Πρωτότυπα αυτοματοποιημένα περιβάλλοντα σχεδίασης προτείνονται για την αποτελεσματική και εύκολη υλοποίηση ολόκληρων εφαρμογών στα συστήματα. Τέλος, προτείνεται μια πρωτότυπη μεθοδολογία διαχωρισμού υλικού/λογισμικού για την βελτίωση της απόδοσης ρεαλιστικών εφαρμογών σε ένα ενσωματωμένο σύστημα σε ολοκληρωμένο κύκλωμα που αποτελείται από έναν προγραμματιζόμενο μικροεπεξεργαστή και FPGA επαναπροσδιοριζόμενη λογική. Η μεθοδολογία έχει αυτοματοποιηθεί σε μεγάλο βαθμό με την χρήση ακαδημαϊκών και εμπορικών εργαλείων. Το FPGA ενεργεί σαν επιταχυντής κρίσιμων τμημάτων κώδικα βελτιώνοντας την απόδοση των εφαρμογών κοντά σε θεωρητικά μέγιστα όρια επιταχύνσεων. Αναλυτικά πειράματα με διαφορετικού τύπου μικροεπεξεργαστές και FPGA δείχνουν την αποτελεσματικότητα της μεθοδολογίας. / In this Ph.D. dissertation, design methodologies for embedded platforms with the aim of improving the performance of realistic applications executed on them are proposed. The considered system platforms target on arithmetic intensive applications, as in the case of Digital Signal Processing and multimedia applications. The applications are coded in a high-level language, fact that eases the implementation of applications in the considered processing platforms. The methodologies have been automated, with the usage of prototype and commercial tools, for the efficient and rapid evaluation of the design and mapping solutions. Initially, a method is proposed for the effective implementation of Digital Signal Processing applications on a microprocessor system that includes as an accelerator of critical application parts a flexible data-path. The effectiveness of the proposed data-path relative to existing ones is illustrated for a set of characteristic arithmetic intensive kernels. An automated synthesis methodology for kernels is presented. This synthesis method is incorporated on a design flow for the considered system that aims in improving application performance and reducing energy consumption. Afterwards, a software framework that implements a formalized methodology for partitioning Digital Signal Processing and multimedia applications between mixed granularity reconfigurable hardware parts is presented. Critical application parts are accelerated on the coarse-grained reconfigurable hardware for satisfying timing constraints of application code mapped on the reconfigurable logic of the platform. The fine-grained reconfigurable hardware is implemented by an embedded Field Programmable Gate Array (FPGA), whereas the coarse-grained reconfigurable logic by an our-developed high-performance reconfigurable data-path. The efficiency of the prototype software is justified using realistic applications. Analytical experiments illustrate that important performance improvements are achieved, while the targeted timing constraints are satisfied for all the tested applications. The incorporation of a proposed flexible template of a Coarse Grained Reconfigurable Array (CGRA) in two different system on chip is presented. For the efficient execution of computational intensive parts on the CGRA an automated mapping process, that it is based on a software loop pipelining algorithm, is developed. The efficiency of the CGRA and of its respective mapping procedure are realized with the execution of real-life applications. In the first system, the CGRA together with an FPGA form the reconfigurable logic of a hybrid platform. In the second system on chip, the CGRA is directly attached to a general purposed microprocessor acting as a co-processor for the execution of critical loops. Automated design frameworks are proposed for the efficient and straightforward implementation of complete applications on the systems. Finally, a hardware/software partitioning methodology is proposed for the performance improvements of realistic applications in an embedded system on chip that it is composed by a programmable microprocessor and an FPGA reconfigurable hardware. The methodology has been automated in a large extend with the usage of academic and commercial tools. The FPGA acts as an accelerator for critical code segments improving by this way the performance of applications close to maximum theoretical bounds. Extensive experiments with different types of microprocessors and FPGAs show the effectiveness of the methodology.

Darbas skirtas suprojektuoti ir realizuoti kuriamam kosminiam žingsniniam strateginiam žaidimui reikalingos grafinio varikliuko statinės dalies aukšto lygio objektų atvaizdavimo funkcijas, su kuriomis būtų galima atvaizduoti visus reikalingus objektus. Buvo išanalizuotas „3D Orion“ žaidimo modelis ir suprojektuota grafinio varikliuko statinė dalies objektų aukšto lygio realizavimo funkcijų prototipai. / This work is for development of turn-based space strategy game of static graphic engine needed high level visualization objects functions, which shows all needed objects. There was analyzed "3D Orion" game model and design static game graphic engine objects of the high level realization function prototypes.

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The revolutionary advancements in the field of bioinformatics have opened new horizons in biological and pharmaceutical research. However, the existing bioinformatics tools are unable to meet the computational demands, due to the recent exponential growth in biological data. So there is a dire need to build future bioinformatics platforms incorporating modern parallel computation techniques. In this work, we investigate FPGA based acceleration of these applications, using High-Level Synthesis. High-Level Synthesis tools enable automatic translation of abstract specifications to the hardware design, considerably reducing the design efforts. However, the generation of an efficient hardware using these tools is often a challenge for the designers. Our research effort encompasses an exploration of the techniques and practices, that can lead to the generation of an efficient design from these high-level synthesis tools. We illustrate our methodology by accelerating a widely used application -- HMMER -- in bioinformatics community. HMMER is well-known for its compute-intensive kernels and data dependencies that lead to a sequential execution. We propose an original parallelization scheme based on rewriting of its mathematical formulation, followed by an in-depth exploration of hardware mapping techniques of these kernels, and finally show on-board acceleration results. Our research work demonstrates designing flexible hardware accelerators for bioinformatics applications, using design methodologies which are more efficient than the traditional ones, and where resulting designs are scalable enough to meet the future requirements.