The fabrication characteristic of focused ion beam (FIB) for Pyrex glass was investigated. FIB has several advantages such as high sensitivity, high material removal rates, low forward scattering, and direct fabrication in selective area without any etching mask, etc. In this study, FIB etched Pyrex glass was used for fast fabrication of 3-D submicron structures. A high-aspect-ratio (HRA) glass structure of 5 (1.97µm depth/0.39µm width) was fabricated. The experimental results in terms of limiting beam size, ion dose¡]ion/cm2¡^, beam current, etc was discussed. Xenon difluoride (XeF2) was applied to enhance the FIB process. Its influence on glass fabrication is studied and characterized.

This study utilizes a modified LIGA process to fabricate a high aspect ratio aspherical micro lens array, which improves low light output of OLED due to its intrinsic total internal reflection. Presently typical OLED extraction efficiency is not high. How to increase OLED extraction efficiency is a valuable topic to discuss. This study analyzes related parameters that influence the formation of micro lenses, for example, the influence of variation of diametric dimension, dry etching parameters and electroforming rate. The experimental results indicate that the tolerance of dimensional variation of the diameter is about 5% during the thermal reflow and dry etching stage. The oxygen content and the photoresist surface during dry etching influence the result. A high electroforming rate is helpful for covering the surface defects on photoresist. An undercut caused by dry etching will discontinue the initial electroformed layers. A apherical microens array can raise the luminance to a maximum of 15 times higher.

Organic light-emitting diodes (OLEDs) are regarded as next-generation light sources. The enhancement of external quantum efficiency of OLEDs has been investigated widely. It is an effective method of improving the external quantum efficiency, which destroys the phenomenon of total internal reflection inside the OLEDs by attaching microlens array to the surface of the glass substrate of the OLEDs. In this thesis, a multi-level aspherical gapless microlens array was designed and manufactured, and it was applied to OLEDs. In contrast with a spherical microlens array, the multi-level aspherical gapless microlens array can achieve a form of high aspect ratio and high fill factor, and they can enhance the external quantum efficiency of OLEDs. At first, aspherical microlens arrays with different parameters, including shapes of curved surface, layouts and feature dimensions, were simulated by optical simulation software, FRED. The aspherical microlens arrays which were attached to an OLED were simulated with a ray tracing method. Then, an optimal geometry and layout were found out. After simulation, a film with multi-level aspherical microlens array was fabricated by a LIGA-like process, including lithography, electroforming, PDMS (Polydimethylsiloxane) micro-molding and UV (Ultraviolet) -cured techniques. The characteristic in this process was to use multi-lithography to fabricate a microlens array with multi-level and high aspect ratio. The shape of multi-level was similar to the design, and the process can achieve the advantage of batch manufacture. Finally, the films with different multi-level aspherical microlens array were attached to an OLED to measure the optical-electric properties. The measured results were compared with simulation and confirmed them.

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.

Modern communications systems are evolving rapidly to address the demand for data exchange, a fact which imposes stringent requirements on the design process of their RF and antenna front-ends. The most crucial pressure on the antenna front-end is the need for miniaturized design solutions while maintaining the desired radiation performance. To satisfy this need, this thesis presents innovative types of periodic antennas, including electromagnetic bandgap (EBG) antennas, which are distinguished in two respects. First, the periodic cells contain thick metal traces, contrary to the conventional thin-trace cells. Second, such thick traces contain very narrow gaps with very tall sidewalls, referred to as high aspect ratio (HAR) gaps. When such cells are used in the structure of the proposed periodic antennas, the high capacitance of HAR gaps decreases the resonance frequency, mitigates conduction loss, and thus, yields considerably small high efficiency antennas. For instance, one of the sample antenna designs with only two EBG cells offers a very small XYZ volume of 0.25λ×0.28λ×0.037λ with efficiency of 83%. Also, a circularly polarized HAR EBG antenna is presented which has a footprint as small as 0.26λ×0.29λ and efficiency as high as 94%. The main analysis method developed in this thesis is a combination of numerical and mathematical analyses and is referred to as HFSS/Bloch method. The numerical part of this method is conducted using a High Frequency Structure Simulator (HFSS), and the mathematical part is based on the classic Bloch theory. The HFSS/Bloch method acts as the mainstay of the thesis and all designs are built upon the insight provided by this method. A circuit model using transmission line (TL) theory is also developed for some of the unit cells and antennas. The HFSS/Bloch perspective results in a HAR EBG TL with radiation properties, a fragment of which (2 to 6 cells) is introduced as a novel antenna, the self-excited EBG resonator antenna (SE-EBG-RA). Open (OC) and short circuited (SC) versions of this antenna are studied and the inherently smaller size of the SC version is demonstrated. Moreover, the possibility of employing the SE-EBG-RA as the element of a series-fed array structure is investigated and some sample high-efficiency, flat array antennas are rendered. A microstrip antenna is also developed, the structure of which is composed of 3×3 unit cells and shows fast-wave behaviors. Most antenna designs are resonant in nature; however, in one case, a low-profile efficient leaky-wave antenna with scanning radiation pattern is proposed. Several antenna prototypes are fabricated and tested to validate the analyses and designs. As the structures are based on tall metal traces, two relevant fabrication methods are considered, including CNC machining and deep X-ray lithography (DXRL). Hands-on experiments provide an outlook of possible future DXRL fabricated SE-EBG-RAs.

In the recent years, there has been a growing interest in micro- and nano-structured composite systems due to their wide use in microelectronics, optoelectronics, magneto-optical devices, high-density data storage, sensors, biomedical devices, and many other areas. Of particular interest is application in the integrated circuit (IC) industry. Here the need for miniaturization has led to new architectures that combine disparate technologies. This has been achieved through innovations in packaging technologies such as 3D integration for high interconnection density, low power, high data throughput, good signal integrity and reliability, and low cost. One of the key active manufacturing technologies for 3D integration is through silicon vias (TSVs), which involves etching of deep vias in a silicon substrate that are filled with an electrodeposited metal, and subsequent removal of excess metal by chemical mechanical planarization (CMP). Electrodeposition often results in undesired voids in the TSV metal fill as well as a thick overburden layer. These via plating defects can severely degrade interconnect properties and lead to variation in via resistance, electrically open vias, and trapped plating chemicals that present a reliability hazard. Thick overburden layers result in lengthy and expensive CMP processing. We are proposing a technique that pursues a viable method of depositing a high quality metal inside vias with true bottom-up filling, using an additive-free deposition solution. The mechanism is based on a novel concept of electrochemical oxidation of backside silicon that releases electrons, and subsequent chemical etching of silicon dioxide for regeneration of the surface. Electrons are transported through the bulk silicon to the interface of the via bottom and the deposition solution, where the metal ions accept these electrons and electrodeposit resulting in the bottom-up filling of the large aspect ratio vias. With regions outside the vias covered bydielectric, no metal electrodeposition should occur in these regions, which minimizes the metal CMP step and reduces the overall processing times and costs. Hence, inherent bottom-up filling is financially advantageous because it will eliminate a large portion of the metal overburden and associated planarization costs. Additive-free deposition is preferable from both lower production cost and quality management perspectives since it results in higher reliability of deposited metal. Our new bottom-up technique was initially examined and successfully demonstrated on blanket silicon wafers and shown to supply electrons to provide bottom-up filling advantage of through-hole plating and the depth tailorability of blind vias. In order to understand the driving mechanism and limits of this process, we have also conducted a fundamental study that investigated the effect of various process parameters on the characteristics of deposited Cu and Ni and established correlations between metal filling properties and various electrochemical and solution variables. A copper sulfate solution with temperature of about 65 °C was shown to be suitable for achieving stable and high values of current density that translated to copper deposition rates of ~2.4 μm/min with good deposition uniformity. The importance of backside silicon oxidation and subsequent oxide etching on the kinetics of metal deposition on front side silicon has also been highlighted. Further, a process model was also developed to simulate the through silicon via copper filling process using conventional and contactless electrodeposition methods with no additives being used in the electrolyte solution. A series of electrochemical measurements were employed and integrated in the development of the comprehensive process simulator. The experimental data not only provided the necessary parameters for the model but also validated the simulation accuracy. From the simulation results, the “pinch-off” effect was observed for the additive-free conventional deposition process, which further causes partial filling and void formation. By contrast, a void-free filling with higher deposition rates was achieved by the use of the contactless technique. Moreover, experimental results of contactless electrodeposition on patterned wafers showed fast rate bottom-up filling (~3.3 μm/min) in vias of 4 μm diameter and 50 μm depth (aspect ratio = 12.5) without void formation and no copper overburden in the regions outside the vias. Efforts were also made to extend the use of the contactless technique to other applications such as synthesis of porous silicon, which is known to be an excellent material with fascinating physical and chemical properties. We were able to fabricate porous silicon with a morphological gradient using a novel design of the experimental cell. The resulted porous silicon layers show a large distribution in porosity, pore size and depth along the radius of the samples. Symmetrical arrangements were attributed to decreasing current density radially inward on the silicon surface exposed to surfactant containing HF based etchant solution. The formation mechanism as well as morphological properties and their dependence on different process parameters, such as HF concentration, solution pH, surfactant concentration, current density and wafer resistivity, has been investigated in detail. In the presence of surfactants, an increase in the distribution range of porosity, pore diameter and depth was observed by increasing HF concentration or lowering pH of the etchant solution, as the formation of pores was considered to be limited by the etch rates of silicon dioxide. Gradient porous silicon was also found to be successfully formulated both at high and low current densities. Interestingly, the morphological gradient was not developed when dimethyl sulfoxide (instead of surfactants) was used in etchant solution potentially due to limitations in the availability of oxidizing species at the silicon-etchant solution interface. In the last part of the dissertation, we have discussed the gradient bottom up filling of Cu in porous silicon substrates using the contactless electrochemical method. The radially symmetric current that gradually varied across the radius of the sample area was achieved by utilizing the modified cell design, which resulted in gradient filling in the vias. Effect of different deposition parameters such as applied current density, copper sulfate concentration and etching to deposition area ratio has been examined and discussed. Increasing the current density from 10 to 15 mA/cm2 resulted in bottom up deposition with less sharp gradients. Further, the study on the effect of copper sulfate concentration highlighted the importance of mass transfer in this process, as either bottom-up deposition or gradient filling could not be achieved at lower CuSO4 concentrations (0.1 and 0.25 M). Additionally, the filling gradient of deposited Cu was obtained with etching to deposition area ratio of 1.6 and 2.7, while a more uniform deposition was observed when the ratio was increased to 3.8. This suggested that the gradient filling may only be accomplished within a certain range of the etching to deposition area ratios.

Recent technological developments, mostly in the fields of concentrated solar power and microelectronics, have driven heat transfer requirements higher than current heat exchangers are capable of producing. Processing power is increasing, while processor size simultaneously decreases and the heat flux requirements of concentrating solar power plants are being driven up by the high temperatures that produce the best thermal efficiency. Heat transfer in microchannels, specifically when utilising flow boiling, has been shown to produce significantly higher heat fluxes than their macro-scale counterparts and could have a large impact on many industrial fields. This high heat transfer characteristic is caused by a number of factors, including the large difference between the sensible and latent heat of the working fluid and the evaporation of a thin liquid film that forms between the microchannel walls and the vapour bubbles. These phenomena occur at incredibly small scales. Flow visualisations, temperature and pressure measurements are therefore difficult to obtain. Many experiments that cover a wide range of microchannel sizes, shapes and orientations, and utilise different working fluids and heat fluxes have been reported. However, the correlations between confined boiling, heat flux and pressure drop have mostly been produced for macro-scale flow. Many different criteria have been developed to distinguish the macro scale from the micro scale, but the general consensus is that macro-scale heat transfer correlations do not perform well when used in the micro scale. Heat transfer correlations are typically created by performing physical experiments over a wide range of parameters and then quantifying the effect that varying these parameters has on the performance of the system. The small scale and high complexity of microchannel-based heat exchangers make visualising the flow within them difficult and inaccurate because both the working fluid and the microchannel walls distort light. The use of numerical modelling via computational fluid dynamics software allows phenomena that occur within the channel to be simulated, which provides valuable insight into how rapid bubble growth affects the surrounding fluid, which can lead to the design of better heat exchangers. This study focused on numerically modelling the growth of a single bubble during the flow boiling of FC-72 in a microchannel with a hydraulic diameter of 0.9 mm and an aspect ratio of 10. The numerical domain was limited to a 10 mm section of the microchannel where bubble nucleation and detachment were observed in an experimental study on a similar microchannel setup. The high cost of 3D simulations was offset by an interface-tracking mesh refinement method, which refined cells not only at the interface, but also a set distance on either side of the interface. To focus on the effects of gravity, a simplified approach is used, which isolates certain phenomena. Density gradients, material roughness and multiple bubble interaction are ignored so that the effects of buoyancy and bubble detachment can be analysed. Simulations are first performed in a 2D section through the centre of the microchannel, and then in the full 3D domain. In both the 3D numerical and experimental cases (Meyer et al., 2020), the bottom heated case had the lowest maximum temperature and the highest heat transfer characteristics, which were influenced by the detachment of the bubble from the heated surface. This observation indicates that the gravitational orientation of the channel can have a significant effect on the heat transfer characteristics of microchannel-based heat exchangers, and that more investigation is required to characterise the extent of this effect. / Dissertation (MEng)--University of Pretoria, 2019. / Mechanical and Aeronautical Engineering / MEng / Unrestricted

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