Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an improvement in power and performance, interconnect scaling results in a degradation in performance and electromigration reliability. Although graphene potentially has superior transport properties compared to copper, it is shown that several technology improvements like smooth edges, edge doping, good contacts, and good substrates are essential for graphene to outperform copper in high performance on-chip interconnect applications. However, for low power applications, the low capacitance of graphene results in 31\% energy savings compared to copper interconnects, for a fixed performance. Further, for characterization of the circuit parameters of multi-layer graphene, multi-conductor transmission line models that account for an alignment margin and finite width of the contact are developed. Although it is essential to push for an improvement in chip performance by improving on-chip interconnects, devices, and architectures, the system level performance can get severely limited by the bandwidth of off-chip interconnects. As a result, three dimensional integration and airgap interconnects are studied as potential replacements for conventional off-chip interconnects. The key parameters that limit the performance of a 3D IC are identified as the Through Silicon Via (TSV) capacitance, driver resistance, and on-chip wire resistance on the driver side. Further, the impact of on-chip wires on the performance of 3D ICs is shown to be more pronounced at advanced technology nodes and when the TSV diameter is scaled down. Airgap interconnects are shown to improve aggregate bandwidth by 3x to 5x for backplane and Printed Circuit Board (PCB) links, and by 2x for silicon interposer links, at comparable energy consumption.

In this paper, a study of tungsten metallization in advanced BEOL interconnects is presented. A mature 10 nm process is used for comparison between the tungsten and conventional copper metallization. Wafers were processed together till M1 dual-damascene etch then separated for different metallization. Tungsten metal line of 24 nm width is showing a 1.6X wire resistance comparing to the copper metal line. Comparable opens/shorts yield were obtained on a 0.8 M comb serpentine, Kelvin-via and 4K via chains. Similar physical profile were also achieved. This study has demonstrated the feasibility of replacing the copper by tungsten at BEOL using the conventional tungsten metallization tools and processes. This could be a cost- effective solution for the low-power products.

In this thesis, I present a microfluidic platform that enables automated image-based assessment of biological structure and function. My work focuses on assessing intact resistance arteries from the mouse cerebral vascular bed with a diameter of approximately 120µm in vitro. The experimental platform consists of a microfluidic device and a world-to-chip fluidic interconnect that minimizes unwanted dead volumes and eliminates the need for any liquid-filled peripheral equipment. The integrated platform is computer controlled and capable of fully automated operation once a small blood vessel segment is loaded onto the chip. Robust operation of the platform was demonstrated through a series of case studies that assessed small artery function and changes therein induced by incubation with the drug nifedipine, a dihydropyridine calcium channel blocker. In addition artery segments were stained for L-type calcium channels, F-actin and nuclei, from which structural information about cell alignment and shape was quantified.

In this thesis, I present a microfluidic platform that enables automated image-based assessment of biological structure and function. My work focuses on assessing intact resistance arteries from the mouse cerebral vascular bed with a diameter of approximately 120µm in vitro. The experimental platform consists of a microfluidic device and a world-to-chip fluidic interconnect that minimizes unwanted dead volumes and eliminates the need for any liquid-filled peripheral equipment. The integrated platform is computer controlled and capable of fully automated operation once a small blood vessel segment is loaded onto the chip. Robust operation of the platform was demonstrated through a series of case studies that assessed small artery function and changes therein induced by incubation with the drug nifedipine, a dihydropyridine calcium channel blocker. In addition artery segments were stained for L-type calcium channels, F-actin and nuclei, from which structural information about cell alignment and shape was quantified.

FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link.

In this dissertation, the development of an experimental prototype for on-board optical-to-electrical signal broadcasting at 10 Gb/s per channel over an interconnect distance of 10 cm was presented. The optical distribution network was implemented using a polymer-based 1-by-4 multimode interference (MMI) splitter with linearly tapered output facet. A 1-by-8 MMI splitter with input/output waveguides of 10 microns in width was first fabricated using standard photolithography and characterized at 40 Gb/s in NRZ format and PRBS = 2^7-1. The pulse response of MMI devices was further quantified from the time-dependent, pulse-modulated field propagation perspective incorporated with various dispersion mechanisms. The results predict their operating limitations and investigate why and how such devices become non-functional in the ultrashort-pulse limit that is far beyond the most present-day optical systems. The guided-mode attenuation associated with polymer waveguides fabricated on FR-4 printed-circuit boards was also investigated for the first time. The rigorous transmission-line network approach was applied and the FR-4 substrate was treated as a long-period substrate grating with rectangular corrugations. The peaks of attenuation were shown to occur near the Bragg conditions that were recognized as the leaky-wave stop bands. As the buffer layer thickness increases, the attenuation becomes negligibly small that is attributed to the weak grating-induced perturbation to the mode behavior. The prototype was then developed on the basis of both experimental verifications to the devices and theoretical investigations. An improved 1-by-4 MMI splitter at 1550 nm with linearly tapered output facet was heterogeneously integrated with four p-i-n photodetectors (PDs) on a silicon (Si) bench. The Si bench itself was then hybrid integrated onto an FR-4 printed-circuit board with four receiver channels composed of transimpedance amplifiers, limiting amplifiers, and surface-mounted components. The innovative integration approach demonstrated the simultaneous alignment between multiple waveguides and multiple PDs during the MMI fabrication process that is a complete radical departure from the conventional assembly method inherent from the telecommunication industry. The entire system was fully functional at 10 Gb/s per channel.

Novel fabrication technologies for high performance electrical and optical chip-to-substrate input/output (I/O) interconnections were developed. This research is driven by the long term performance and integration requirements of high performance chip-to-substrate I/Os, as well as the package reliability demands from semiconductor manufacturing. An electroless copper plating and annealing process was developed to join copper structures to achieve chip-to-substrate assembly by all copper pillar interconnects. The developed copper pillar interconnects provide much higher current carrying capability for chip-to-substrate power/ground input/output distributions and have low electrical parasitic characteristics for high frequency electrical signal communications. This copper bonding process also demonstrates the capability to compensate for misalignments and height variations of bonded structures. A finite element generalized plane deformation model was employed to design fully compliant copper pillars to eliminate the need of underfill. Electrical parasitics of copper pillar chip-to-substrate interconnects were studied by the derived formulas for low parasitic requirements. An optimized dimension space for all the criteria was provided on the pillar dimension chart. A novel nanoimprint lithography was developed to combine with photolithography in one process to create high quality features on a macrostructure for chip-to-substrate optical I/O applications. This fabrication process also demonstrated the capability to produce off-angle complex structures.

In the multi-core systems, the data transfer between cores becomes a major challenge. The on-chip interconnect networks should be low latency, high throughput, scalability, better router or arbitration strategy, and low power consumption. An asynchronous ring bus, which is 33 bit width, adopting dual-rail single-track data protocol is proposed in this thesis. It provides not only robust but also high-speed asynchronous circuits condition. Owing to asynchronous circuits design, there are different transfer times in different hop counts. The shorter the distance is, the faster the data can be transferred. Unlink the synchronous ring bus, the bus frequency must be limited by the longest hop count latency. On the other hand, the transmission time of asynchronous circuits will not be held up by the longest distance even though the number of core is increased. For providing higher throughput, multiple cores which are able to access the bus simultaneously make a direct connection between each other. In bus arbitration, distribution arbiter is adopted to arbitrate the right to use the bus and solve the collision. Finally, the system performance in different arbitration strategies has been estimated in TSMC 0.18£gm process in this thesis. The transmission time of the shortest distance is 1.5 ns approximately, and the longest distance first has a better performance in different arbitration strategies.

Dr. Paul V. Gratz Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. NoCs implemented with either of these schemes, however, tend to have high latencies as packets must be synchronized at the intermediate nodes between source and destination. In this work, we propose a novel router microarchitecture which offers superior performance versus typical synchroniz- ing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose a new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26 percent at low loads and increases saturation throughput by up to 50 percent.

As integrated circuits (ICs) are scaled down to deep submicron regime, interconnect delay becomes increasingly dominant over intrinsic gate delay. To solve the issue, two realistic methods are accepted popularly. On the one hand we use copper as the conductor for multilevel interconnects to decrease the resistance part of the RC delay. On the other hand we should reduce the coupling capacitance between the metal lines and this requires a low dielectric constant material. However, some difficulties come up in integrating low-k material with copper wires, including dielectric integrity and high diffusivity of copper ions. In order to prevent copper from penetrating into dielectric material under high electric fields and operation temperature, barrier dielectric have been developed to enhance resistance against copper drift. Silicon carbide (SixCy) with lower dielectric constant (k=4~5) is a promising barrier dielectric material to replace typically used silicon nitride (SixNy), (k~8). In this thesis, we will discuss the basic material properties of silicon carbide and the issues which will meet in process integration and actual working such as thermal cycles and operating under an electric field and a high temperature environment simultaneously. We investigated the conduction mechanism of the leakage current and tried to extract the physical parameters among it. In addition, the electrical properties of Silicon carbide at low temperature were also an important part of our research. Finally, we proposed some reasonable models to demonstrate the phenomenon and results we observed.