The interconnect fabric that provides electrical connectivity to active devices is an essential component to modern semiconductor chips. As the dimensions of these devices are scaled to improve performance and keep pace with Moore's Law, the local Cu interconnects must scale in parallel. Intrinsic material properties of Cu result in spiking electrical resistivity with scaling and present a looming bottleneck to chip performance. In this thesis, we introduce graphene as a replacement material to Cu interconnects in support of future chip scaling. In particular we focus on experimentally establishing fundamental mechanisms of chemically doping graphene via the basal plane and edge passivation, with broad contributions that extend beyond the focus of local interconnects.

The way printed circuit board interconnects for high-speed digital signals are designed ultimately determines the performance that can be achieved for a certain interface, thus having a profound impact on whether the complete communication channel will comply with the desired standard specification or not. Good understanding and methods for anticipating and verifying this behaviour through computer simulations and practical measurements are therefore essential. Characterization of an interconnect can be performed either in the time domain or in the frequency domain. Regardless of the domain chosen, a method for unobstrusively connecting to the test object is required. After various different attempts it could be concluded that frequency domain measurements using a vector network analyzer together with microwave probes will provide the best measurement fidelity and ease of use. In turn, this method requires the test object to be prepared for the measurement. Advanced computer simulation software is available, but comes with the drawback of dramatically increasing the requirements on computational resources for improved accuracy. In general, these simulators can be configured to show good agreement with measurements at frequencies as high as ten gigahertz. For ideal interconnects, the simplest and, thus, fastest methods will provide good enough accuracy. These simple methods should be complemented with the results from more accurate simulations in cases where the physical structure is complex or in other ways deviates from the ideal. Several practical routing situations were found to introduce severe signal integrity issues. Through appropriate use of the methods developed in this thesis, these can be identified in the design process and thereby avoided.

This thesis work investigates the effects of crosstalk on on-chip interconnects. We use optimal repeater insertion as a reference and derive analytical expressions for signal latency, maximum data-rate and power consumption. Through calculations and simulations we show that despite large uncertainties in arrival time of a signal that is subject to crosstalk, we are able to make predictions about the maximum data-rate on a bus. We also show that data-rates can exceed the classical limit of the latency inverted by using wave pipelining. To increase the data-rate, we can increase the number of repeaters to a limit, at the cost of additional latency and power. Savings in power consumption can be achieved by using fewer repeaters, paying in latency and data-rate. Through fewer repeaters, the top metal layer shows better performance in all investigated aspects.

With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget. Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).

Environmental stress tests, or accelerated life tests, apply stresses to electronic packages that exceed the stress levels experienced in the field. In theory, these elevated stress levels are used to generate the same failure mechanisms that are seen in the field, only at an accelerated rate. The methods of assessing reliability of electronic packages can be classified into two categories: a statistical failure based approach and a physics of failure based approach. This research uses a statistical based methodology to identify the critical factors in reliability performance of a flip chip on board component level assembly and a physics of failure based approach to develop a low cycle strain based fatigue equation for flip chip component level assemblies. The critical factors in determining reliability performance were established via experimental investigation and their influence quantified via regression analysis. This methodology differs from other strain based fatigue approaches because it is not an empirical fit to experimental data; it utilizes regression analysis and least squares to obtain correction factors, or correction functions, and constants for a strain based fatigue equation, where the total inelastic strain is determined analytically. The end product is a general flip chip on board equation rather than one that is specific to a certain test vehicle or material set.

A new full-wave surface impedance integral equation method is presented for three-dimensional arbitrary-shaped interconnect parasitic extraction in layered media. Various new ways of applying voltage and current excitations for electromagnetic-circuit simulation are introduced. A new algorithm is proposed for matrix formation of electromagnetic-circuit simulation, low frequency solution and layered media so that it can be easily integrated to a Rao-Wilton-Glisson based method of moment code. Two mixed potential integral equation forms of the electric field integral equation are adapted along with the Michalski-Mosig formulations for layered kernels to model electromagnetic interactions of interconnects in layered media over a conducting substrate. The layered kernels are computed directly for controllable accuracy. The proposed methods are validated against existing methods for both electromagnetic and electromagnetic-circuit problems.

With constant miniaturization of integrated circuits, the current densities experienced in interconnects in electronic circuits has been multiplied. Aluminum, which is widely used as an interconnect material, has fast diffusion kinetics under low temperatures. Unfortunately, the combination of high current density and fast diffusion at low temperatures causes the circuit to fail by electromigration (EM), which is the mass transport of atoms due to the momentum transfer between conducting electrons and diffusing atoms. In the present study, the effect of alloying elements in aluminum on the diffusion behavior is investigated using a non equilibrium molecular dynamics method (NEMD) under the effect of electromigration wind force. The electromigration force was computed by the use of a pseudopotential method in which the force depends on the imperfections on the lattice. 1.125 at% of various elements, namely Cu, Mg, Mn, Sn and Ti were added into aluminum. The electromigration force was then calculated on the alloying elements and the surrounding aluminum atoms and these forces incorporated into molecular dynamics using the non-equilibrium formalism. The jump frequencies of aluminum in these systems were then computed. Cu, Mn and Sn impurities were found to be very effective in lowering the kinetics of the diffusion under electromigration conditions. Cu was known experimentally to have such an effect on aluminum for several years, but the Mn and Sn elements are shown here for the first time that they can have a similar effect.

Low-loss off-chip interconnects are required for energy-efficient communication in dense microprocessors. To meet these needs, air cavity parallel plate and microstrip lines with copper conductors were fabricated on an FR-4 epoxy-fiberglass substrate using conventional microelectronics manufacturing techniques. Copper transmission lines were separated by a composite dielectric of air and Avatrel 2000P and by a dielectric layer of air only. The composite dielectric lines were characterized to 10 GHz while the all air dielectric lines were characterized to 40 GHz. The transmission line structures showed loss as low 1.5 dB/cm at 40 GHz with an effective dielectric constant below 1.4. These novel structures show low loss in the dielectric due to the reduced relative permittivity and loss tangent introduced by the air cavity. Transmission line structures with a composite dielectric were built by coating the sacrificial polymer poly(propylene carbonate) (PPC) over a copper signal line, encapsulating with an overcoat polymer, electroplating a ground line, and decomposing PPC to form an air cavity. The signal and ground wires were separated by a layer of 15 µm of air and 20 µm of Avatrel 2000P. Air cavity formation reduced dielectric constant more than 30 percent and loss of less than 0.5 dB/cm was measured at 10 GHz. Residue from PPC decomposition was observed in the cavity of composite dielectric structures and the decomposition characteristics of PPC were evaluated to characterize the residue and understand its formation. Analysis of PPC decomposition based on molecular weight, molecular backbone structure, photoacid concentration and vapor pressure, casting solvent, and decomposition environment was performed using thermogravimetric analysis and extracting kinetic parameters. Novel interaction of copper and PPC was observed and characterized for the self-patterning of PPC on copper. Copper is dissolved from the surface during PPC spincoating and interacts with the polymer chains to improve stability. The improved thermal stability allows selective patterning of PPC on copper. Decomposition characteristics, residual metals analysis, and diffusion profile were analyzed. The unique interaction could simplify air-gap processing for transmission lines. Inorganic-organic hybrid polymers were characterized for use as overcoat materials. Curing characteristics of the monomers and mechanical properties of the polymer films were analyzed and compared with commercially available overcoat materials. The modulus and hardness of these polymers was too low for use as an air-gap overcoat, but may be valuable as a barrier layer for some applications. The knowledge gained from building transmission line structures with a composite dielectric, analyzing PPC decomposition, interaction with copper, and comparison of hybrid polymers with commercial overcoats was used to build air-gap structures with improved electrical design. The ground metal was separated from the signal only by air. The signal wire was supported from above using 60 µm of Avatrel 8000P as an overcoat. Structures showed loss of less than 1.5 dB/cm at 40 GHz, the lowest reported value for a fully encapsulated transmission line structure.

Although copper (Cu) is the preferred interconnect material due to its lower resistivity than aluminum (Al), Cu subtractive etching processes have not been developed at temperatures less than 180 °C, primarily due to the inability to form volatile etch products at low temperature. The conventional damascene technology avoids the need for subtractive etching of Cu by electroplating Cu into previously etched dielectric trenches/vias, followed by a chemical/mechanical planarization (CMP) process. However, a critical "size effect" limitation has arisen for damascene technology as a result of the continuing efforts to adhere to "Moore's Law". The size effect relates to the fact that the resistivity of damascene-generated lines increases dramatically as the line width approaches the sub-100 nm regime, where feature size is similar to the mean free path of electrons in Cu (40 nm). As a result, an alternative Cu patterning process to that of damascene may offer advantages for device speed and thus operation. This thesis describes investigations into the development of novel, fully-plasma based etch processes for Cu at low temperatures (10 °C). Initially, the investigation of a two-step etch process has been studied. This etch approach was based on a previous thermodynamic analysis of the Cu-Cl-H system by investigators at the University of Florida. In the first step, Cu films are exposed to a Cl₂ plasma to preferentially form CuCl₂, which is believed to be volatilized as Cu₃Cl₃ by subsequent exposure to a hydrogen (H₂) plasma (second step). Patterning of Cu films masked with silicon dioxide (SiO₂) layers in an inductively coupled plasma (ICP) reactor indicates that the H₂ plasma step in the two-step process is the limiting step in the etch process. This discovery led to the investigation of a single step Cu etch process using a pure H₂ plasma. Etching of blanket Cu films and Cu film patterning at 10°C, display an etch rate ~ 13 nm/min; anisotropic etched features are also observed. Comparison of H₂ plasma etching to sputtering of Cu films in argon (Ar) plasmas, indicates that both a chemical component and a physical component are involved in the etching mechanism. Additional studies using helium plasmas and variation of power applied to the plasma and etching surface demonstrate that the etch rate is controlled by reactive hydrogen species, ion bombardment flux and likely photon flux. Optical Emission Spectroscopy (OES) of the H₂ plasma during the Cu etching process detects Cu emission lines, but is unable to identify specific Cu etch products that desorb from the etching surface. Variation of Cu etch rates as a function of temperature suggests a change in mechanism for the removal of Cu over the temperature of -150 °C to 150 °C. OES analyses also suggest that the Cl₂ plasma step in the two-step process can inhibit Cu etching, since the subsequent H₂ (second) plasma step shows a time delay in film removal. Preliminary results of the etching of the SiO₂ mask material in H₂ plasmas with various intentionally introduced contaminants demonstrate the robustness of the H₂ plasma Cu etch process.

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