Seal glass is essential and plays a crucial role in solid oxide fuel/electrolyzer cell performance and durability. A seal glass should have a combination of thermal, chemical, mechanical, and electrical properties in order to seal different cell components and stacks and prevent gas leakage. All the desired properties can simultaneously be obtained in a seal glass by suitable compositional design. In this dissertation, SrO-La₂O₃-A₂O₃-B₂O₃3-SiO₂ based seal glasses have been developed and composition-structure-property relationships have been investigated. B₂O₃ free SrO-La₂O₃-Al₂O₃-SiO₂ based seal glass is the most suitable and its compatibility with the metallic interconnects and sealing performances have been evaluated. A seal glass should be stable for 5,000-40,000 hrs in the oxidizing and reducing atmospheres at 600-900°C but both the thermal and chemical stability is a persistent problem. The effect of Al₂O₃ on a SrO-La₂O₃-Al₂O₃-B₂O₃-SiO₂ based seal glass has been studied to improve the thermal properties, such as glass transition temperature, softening temperature and thermal expansion coefficient, and the thermal stability. Al₂O₃ improves the thermal stability but does not significantly affect the thermal properties of the seal glass. Comprehensive understanding of composition-structure-property relationships is needed to design a suitable seal glass. The thermal properties and stability of a borosilicate seal glass depend on the B2O3:SiO2 ratio in the composition. The role of B₂O₃:SiO₂ ratio on the glass network structure of the SrO-La₂O₃-Al₂O₃-B₂O₃-SiO₂ based seal glasses has been studied using Raman spectroscopy and nuclear magneto resonance spectroscopy. The thermal properties and thermal stability were correlated with the glass network structure and the calculated network connectivity. This study shows that the thermal properties degrade with increasing B₂O₃:SiO₂ ratio due to increase in the non-bridging oxygen and decrease in the network connectivity. High B₂O₃:SiO₂ ratio induces BO4 and SiO4 structural unit ordering, increases micro-heterogeneity, and subsequently degrades thermal stability. B₂O₃ free SrO-La₂O₃-Al₂O₃-SiO₂ seal glass shows the best combination of the thermal properties and thermal stability among the studied glasses. Nickel or nickel oxide is added into a seal glass to modify the thermal properties depending on the specific composition. The role of nickel as a network former or modifier and its effect on the thermal properties and thermal stability of the SrO-La₂O₃-Al₂O₃-SiO₂ based seal glasses have been investigated. Nickel is a modifier in this glass system and does not improve the thermal properties but degrades thermal stability by decreasing network connectivity and inducing micro-heterogeneity. The interconnect-seal glass interface stability is the most crucial for solid oxide fuel/electrolyzer cell. Crofer 22 APU and AISI 441 alloys are the preferred interconnects. The interfacial stability of the SrO-La₂O₃-Al₂O₃-SiO₂ based seal glass with these alloys have been studied as a function of time (0-1000 hrs), temperature (700-850°C), atmospheres (air, argon, and H₂O/H₂) using scanning electron microscopy (SEM), energy dispersive spectroscopy (EDS), and X-ray diffraction analysis (XRD). Complementary analytical techniques such as wave length dispersive spectroscopy (WDS) and SEM of thin samples were also carried out for selected samples. This study shows good interfacial stability of the SrO-La₂O₃-Al₂O₃-SiO₂ based seal glass with these alloys for the studied conditions. A suitable seal glass should be hermetic and withstand 100-1000 thermal cycles for practical application. Sealing performances of the SrO-La2O3-Al2O3-SiO2 based seal glass have been evaluated by pressure-leakage method. The seal glass is hermetic for at least 2000 hrs and withstands 100 thermal cycles. Overall, present work shows that the SrO-La₂O₃-Al₂O₃-SiO₂ based glass has all the desired properties and suitable for solid oxide fuel/electrolyzer cell seal. / Ph. D.

Unified Diagnostic Service (UDS), which is an international and not a company-specific standard, is used in almost all new electronic control units (ECUs) by now. Modern vehicles have a diagnostic interface for off-board diagnostics, which makes it possible to connect a diagnostic tool to the vehicle’s bus system like Controller Area Network (CAN) and Local Interconnect Network (LIN). However, as the most commonly used method, sequential method on the UDS data transmission over LIN does not only result in low reliability and flexibility but also fails to meet the standard for LIN development defined in the latest LIN specification published by the consortium. With standard workflow and application interfaces, this Master Thesis will develop and evaluate a database-based method to build a UDS system over LIN, where all the information for the network is defined in the LIN database, and the protocol properties are realized in a reusable model so that it can be easily reconfigured for the future development of other services. As a result, a new method including a layered-structure LIN protocol model and a LIN database has been successfully designed and implemented. The prototype is built on the device PIC32MX795, and the database can be deployed by the configuration tool to specify the UDS communication schedule. Further, several performance evaluations have been performed. The tests indicate that the system is qualified on the limited hardware platform and the configuration flexibility is proved by different databases. / Unified Diagnostic Service (UDS), som är en internationell och inte en företagsspecifik standard, används nu i nästan alla nya elektroniska styrenheter (ECU). Moderna fordon har ett diagnostiskt gränssnitt för diagnostik utanför kortet, vilket gör det möjligt att ansluta ett diagnostiskt verktyg till fordonets bussystem som Controller Area Network (CAN) och Local Interconnect Network (LIN). Som den mest använda metoden resulterar emellertid sekventiell metod på UDS-dataöverföringen via LIN inte bara i låg tillförlitlighet och flexibilitet utan uppfyller också standarden för LINutveckling som definieras i den senaste LIN-specifikationen publicerad av konsortiet. Med standard arbetsflöde och applikationsgränssnitt kommer denna masteruppsats att utveckla och utvärdera en databas-baserad metod för att bygga ett UDS-system över LIN, där all information för nätverket definieras i LIN-databasen, och protokollegenskaperna realiseras i en återanvändbar modell så att den enkelt kan konfigureras för framtida utveckling av andra tjänster. Som ett resultat har en ny metod som inkluderar en LIN-protokollmodell med skiktstruktur och en LIN-databas framgångsrikt designats och implementerats. Prototypen är byggd på enheten PIC32MX795, och databasen kan konfigureras av verktyget för att ange UDSkommunikationsschema. Vidare har flera prestationsutvärderingar genomförts. Testen indikerar att systemet är kvalificerat på den begränsade hårdvaruplattformen och konfigurationsflexibiliteten bevisas av olika databaser.

The global traffic is experiencing an exponential growth posing severe challenges to the communication networks in terms of capacity. As a future-proof technology fiber communication is widely implemented in different network segments, which can be categorized by transmission distance as long-haul and short-reach. This thesis focuses on the short-reach communication networks including fiber access network connecting the end users to the metro/core networks that covering tens of kilometers and optical datacenter network handling the traffic within the datacenter with distance up to a few kilometers. For fiber access networks, wavelength division multiplexing passive optical networks (WDM-PONs) assign a dedicated wavelength channel to each user guaranteeing high data rate. Dense channels enlarges the user count but makes the signals vulnerable to the wavelength drift. In this regard we propose two schemes based on optical frequency comb technique to generate stable carriers for WDM-PONs. Meanwhile, radio-over-fiber techniques allows the transmission of radio signals between central offices and the cells. Millimeter wave (MMW) over fiber, on the other hand, offer high bandwidth for future high capacity mobile access. We propose and experimentally demonstrate a palm-shaped spectrum generation where the high-power central carrier can be used for upstream transmission while multiple MMW bands are capable of transmitting different downstream data simultaneously. Regarding optical datacenter networks, passive optical interconnects (POIs) have been proposed as an energy-efficient solution since only passive optical components are used for server interconnection. However, the high insertion loss may result in a scalability problem. We develop a methodology that considers various physical-layer aspects, e.g., receiver types, modulation formats, to quantify the scalability of POIs. Both theoretical analyses and experimental measurements have been performed to assess the scalability of various coupler-based POIs. / Den globala datatrafiken växer exponentiellt, både på grund av nya bandbreddskrävande applikationer och ökningen av antalet användare. Detta innebär en utmaning för kommunikationsnätens kapacitet. Fiberoptisk kommunikation är en framtidssäker teknik för att möta detta kapacitetsbehov och används redan i stor utsträckning i olika delar av näten. Beroende på överföringsavstånd, kan fibernät kategoriseras som långdistansnät eller nät med kort räckvidd. Denna avhandling behandlar nät med kort räckvidd, innefattande dels 1) accessnät som förbinder slutanvändarna till stadsnätet/ huvudnätet och typiskt omfattar tiotals kilometer, dels 2) optiska datanätverk som hanterar den interna trafiken inom datacenter med överföringsavstånd upp till ett par kilometer.För fiberaccessnät är en av de lovande teknikerna våglängdsmultiplexade passiva optiska nät (WDM-PON), där en dedicerad våglängdskanal tilldelas varje användare vilket garanterar hög datahastighet. Genom ett litet kanalavstånd så kan antalet användare i WDM-PON utökas men det gör samtidigt systemet känsligt för våglängdsdrift hos lasrarna. För att råda bot på detta, föreslår vi två system baserade på optisk frekvenskams-teknik. Vi validerar experimentellt att de kan generera stabila optiska bärvågor för WDM-PON. Radio-över –fiber-tekniken gör samtidigt det möjligt att sända radiosignaler över en lång sträcka och används därför i mobilsystem för överföring mellan centralstationen och radiocellerna. Millimetervågor (MMW) över fiber erbjuder ännu större modulationsbandbredd och är lovande för framtidens mobilradiosystem med hög kapacitet. I denna avhandling föreslår vi, och demonstrerar experimentellt, generation av ett frekvenskams-spektrum som är format som en handflata, där en central bärare med hög effekt (långfingret på handflatan) kan användas i radiocellerna för uppströms överföring, medan multipla MMW band (övriga fingrar) samtidigt kan överföra olika data nedströms. När det gäller nätverk för optiska datacenter, har passiva optiska interconnects (POI) föreslagits som en energieffektiv lösning, där endast passiva optiska komponenter används för ihopkoppling av servrarna. Höga inkopplingsförluster hos passiva optiska komponenter kan emellertid leda till allvarliga skalbarhetsproblem. I denna avhandling presenterar vi en nyutvecklad metod för att kvantifiera skalbarheten, vilken tar hänsyn till olika faktorer i det fysiska lagret som t.ex. mottagartyp och modulationsformat. Både teoretiska analyser och experimentella mätningar har utförts för att utvärdera skalbarheten hos olika kopplarbaserade POI. / <p>QC 20161117</p>

Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main contribution of this dissertation is the development of unified physical and high-level synthesis techniques for the design of ASICs with optimal chip temperatures and interconnect delays. Thermal issues are becoming a serious problem in high-performance VLSI circuits, adversely impacting performance, reliability, power consumption, and cooling costs. To address this, we present a temperature-aware behavioral synthesis (TABS) framework that combines power minimization with temperature-aware task scheduling, resource binding, and floorplanning. Compared to conventional low-power synthesis methods, our approach is effective in synthesizing circuits with lower chip temperatures and more uniform thermal distributions, with temperature reductions up to 23% when compared to low-power synthesis. We propose three techniques to address interconnect delays during high-level synthesis: (1) a simulated annealing (SA) based layout-aware high-level synthesis technique for 3-D integrated circuits, that tightly couples the synthesis tasks of resource binding and 3-D floorplanning. The proposed algorithm significantly outperforms a conventional synthesis flow that separates the binding and floorplanning steps, with improvements in the total wirelength by 29% and of the longest wirelength by 21%; (2) a floorplan-aware high-level synthesis technique that uses the topology of multi-terminal nets to improve interconnect delay estimates during resource binding. Experiments show that the use of accurate wire delay estimates during binding can reduce wire delays by as much as 49% in 70nm technology; (3) an iterative high-level design-space exploration engine that uses a priori stochastic wirelength estimates to guide binding decisions during high-level synthesis. The proposed approach offers a significant speed-up during design space exploration when compared to approaches that use traditional place-and-route to evaluate candidate solutions. Finally, we present a genetic algorithm (GA) based approach for high-level synthesis. We propose novel GA encoding, crossover, and mutation operators for the problem. The quality of the results generated by the GA are superior to those of several other techniques reported in the literature.

Three terminal ‘dotted-I’ interconnect structures, with vias at both ends and an additional via in the middle, were tested under various test conditions. Mortalities (failures) were found in right segments with jL value as low as 1250 A/cm, and the mortality of a dotted-I segment is dependent on the direction and magnitude of the current in the adjacent segment. Some mortalities were also found in the right segments under a test condition where no failure was expected. Cu extrusion along the delaminated Cu/Si₃N₄ interface near the central via region was believed to cause the unexpected failures. From the time-to-failure (TTF), it is possible to quantify the Cu/Si₃N₄ interfacial strength and bonding energy. Hence, the demonstrated test methodology can be used to investigate the integrity of the Cu dual damascene processes. As conventionally determined critical jL values in two-terminal via-terminated lines cannot be directly applied to interconnects with branched segments, this also serves as a good methodology to identify the critical effective jL values for immortality. / Singapore-MIT Alliance (SMA)

In continuation of a successful series of events, the 4th Many-core Applications Research Community (MARC) symposium took place at the HPI in Potsdam on December 8th and 9th 2011. Over 60 researchers from different fields presented their work on many-core hardware architectures, their programming models, and the resulting research questions for the upcoming generation of heterogeneous parallel systems.

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.

Die Entwicklung der Mikroelektronik wird durch eine fortschreitende Miniaturisierung der Bauelemente geprägt. Infolge einer Reduzierung der Querschnittflächen von Leitbahnstrukturen erhöht sich die elektrische Leistungsdichte und das Metallisierungssystem bestimmt zunehmend die Übertragungsgeschwindigkeiten. Kupfer repräsentiert hierbei das verbreitetste Leitbahnmaterial und wird vorwiegend mittels elektrochemischer Abscheidung in vergrabene Damaszen-Strukturen eingebracht. Die vorliegende Dissertation beschreibt Möglichkeiten für eine Optimierung von Kupferleitbahnen für höchstintegrierte Schaltkreise. Von besonderem Interesse sind hierbei die Gefügequalität und der Reinheitsgrad. Es erfolgen umfangreiche werkstoffanalytische und elektrochemische Untersuchungen zur Charakterisierung von Depositionsmechanismen, des Einbaus von Fremdstoffen, des Mikrogefüges nach der Abscheidung und der Mikrogefügeumwandlung. In einem abschließenden Forschungsschwerpunkt werden Kupfer-Damaszen-Teststrukturen mit unterschiedlichen Gehalten nichtmetallischer Verunreinigungen hergestellt und entsprechenden Lebensdauerexperimenten unterzogen. Hierdurch gelingt eine Evaluierung des Einflusses jener Verunreinigungen auf die Elektromigrationsbeständigkeit von Kupferleitbahnen. Die Arbeit umfasst daher das gesamte Spektrum von der Grundlagenforschung bis zur Applikation von elektrochemisch abgeschiedenen Kupferdünnschichtmetallisierungen.

A fast and efficient hierarchical optimization engine was developed to benchmark and optimize various emerging device and interconnect technologies and system-level innovations at the early design stage. As the semiconductor industry approaches sub-20nm technology nodes, both devices and interconnects are facing severe physical challenges. Many novel device and interconnect concepts and system integration techniques are proposed in the past decade to reinforce or even replace the conventional Si CMOS technology and Cu interconnects. To efficiently benchmark and optimize these emerging technologies, a validated system-level design methodology is developed based on the compact models from all hierarchies, starting from the bottom material-level, to the device- and interconnect-level, and to the top system-level models. Multiple design parameters across all hierarchies are co-optimized simultaneously to maximize the overall chip throughput instead of just the intrinsic delay or energy dissipation of the device or interconnect itself. This optimization is performed under various constraints such as the power dissipation, maximum temperature, die size area, power delivery noise, and yield. For the device benchmarking, novel graphen PN junction devices and InAs nanowire FETs are investigated for both high-performance and low-power applications. For the interconnect benchmarking, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed, and emerging multi-layer graphene interconnects are also investigated, and compared with the conventional Cu interconnects. For the system-level analyses, the benefits of the systems implemented with 3D integration and heterogeneous integration are analyzed. In addition, the impact of the power delivery noise and process variation for both devices and interconnects are quantified on the overall chip throughput.

This dissertation focuses on one of the most active research areas in the microelectronics industry: Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs). This study constitutes two parts: 1. Thermal stress measurement on TSVs; 2. Analyses on thermo-mechanical reliability of TSVs. In the first part, a metrology for stress measurement of through-silicon-via (TSV) structures was developed using a bending beam technique. The bending curvature induced by the thermal expansion of a periodic array of Cu TSVs was measured during thermal cycles. The stress components in TSV structures were deduced combining the curvature measurement with a finite-element-analysis (FEA). Temperature-dependent thermal stresses in Cu TSVs and in Si matrix were derived. In the second part, the reliability issues induced by the thermal stresses of TSVs were analyzed from several aspects, including the carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions between TSVs. Among them, the mobility change in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a high mobility change was defined as the keep-out zone (KOZ) for transistors. FEA simulations were carried out to calculate the area of KOZ surrounding TSVs. The area of KOZ was found to be mainly determined by the channel direction of the transistor as a result of anisotropic piezoresistivity effects. FEA simulations also showed that the KOZ can be controlled by TSV geometry, material selection, etc. Interfacial delamination of TSVs was found to be mainly driven by a shear stress concentration at the TSV/Si interface. Crack driving force for TSV delamination was calculated using FEA simulations, which take into account the magnitude of thermal load, TSV geometry, TSV materials, etc. The results provided a design guideline to improve the TSV delamination problem. In the last, the stress interaction among TSV arrays was examined using a bi-TSV model. In the Cartesian coordinate system, thermal stresses can be intensified or suppressed between TSVs, depending on how TSVs are located. Further analyses suggested that the area of KOZ and the TSV-induced Si cracking can both be improved by optimizing the arrangement of the TSV arrays. / text