In this dissertation, a carbon nanotube thin-film transistor is fabricated on a flexible substrate. Combined printing and stamping techniques are used for the fabrication. An ink-jet printing technique is used to form the gate, source, and drain electrodes as well as the dielectric layer. A self aligned carbon nanotube (CNT) thin film is formed by using a new modified dip coat technique before being transferred to the device substrate. This novel modified dip-coat technique utilizes the capillary effect of a liquid solution rising between gaps to coat CNT solution on a large area of the substrate while consuming minimal CNT solution. Several key solutions are addressed to solve the fabrication problems. (1) The source/drain contact with the CNT channel is developed by using droplets of silver ink printed on the source/drain areas prior to applying CNT thin. The wet silver ink droplets allow the silver to "wet" the CNT thin-film area and enable good contact with the source and drain contact after annealing. (2) A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This thin Kapton film is also used as the media for transferring the aligned CNT thin-film on the device substrate. Using this technique, printing the passivation layer can be avoided, and it prevents the inter-diffusion of the liquid dielectric into the CNT porous thin-film. (3) A simple and cost effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior bonding on the first substrate. Ink-jet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the on the bottom layer, followed by an anneal process. High drain current of 0.476mA was obtained when V[subscript G]= -3V and source-drain voltage (V[subscript DS]) was -1.5V. A bending test was performed on the CNT TFT showing less than a 10% variation in performance. A bending test was also performed on via structures, which yielded less than a 5% change in resistance. The developed CNT TFT is used to form a switch in a phase shifter for a flexible phased-array antenna (PAA). Four element 1-dimensional and 2-dimensional phased-array antennae are fabricated and characterized. Multilayer metal interconnects were used to make a complete PAA system. For a 2-bit 1x4 PAA system, by controlling the ON/OFF states of the transistors, beam steering of a 5.3GHz signal from 0° to -27° has been demonstrated. The antenna system also shows good stability and tolerance under different bending radii of curvature. A 2-bit 2x2 PAA system was also fabricated and demonstrated. Two dimensional beam steering of a 5.2GHz signal at an angle of [theta]=20.7° and [phi]=45° has been demonstrated. The total efficiency of the 1-dimensional and 2-dimensional PAA systems are 42% and 46%, respectively. / text

In a System on a Chip (SoC), interconnect is the factor limiting Performance, Power, Area and Schedule (PPAS). Distributed crossbar switches also called as Switching Central Resources (SCR) are often used to implement high performance interconnect in a SoC – Network on a Chip (NoC). Multiple issue bus protocols like AXI (from ARM), VBUSM (from TI) are used in paths critical to the performance of the whole chip. Experimental analysis of effects on PPAS by architectural modifications to the SCRs is carried out, using synthesis tools and Texas Instruments (TI) in house power estimation tools. The effects of scaling of SCR sizes are discussed in this report. These results provide a quick means of estimation for architectural changes in the early design phase. Apart from SCR design, the other major domain, which is a concern, is deadlocks. Deadlocks are situations where the network resources are suspended waiting for each other. In this report various kinds of deadlocks are classified and their respective mitigations in such networks are provided. These analyses are necessary to qualify distributed SCR interconnect, which uses multiple issue protocols, across all scenarios of transactions. The entire analysis in this report is carried out using a flagship product of Texas Instruments. This ASIC SoC is a complex wireless base station developed in 2010- 2011, having 20 major cores. Since the parameters of crossbar switches with multiple issue bus protocols are commonly used in SoCs across the semiconductor industry, this reports provides us a strong basis for architectural/design selection and validation of all such high performance device interconnects. This report can be used as a seed for the development of an interface tool for architects. For a given architecture, the tool suggests architectural modifications, and reports deadlock situations. This new tool will aid architects to close design problems and bring provide a competitive specification very early in the design cycle. A working algorithm for the tool development is included in this report. / text

The proliferation of distributed energy resources (DER)s has prompted interest in the expansion of DC power systems. The technological limitations that hinder the expansion of DC power systems are the absence of DC circuit breakers and high step-up/high step-down DC converters for interconnecting DC systems. This thesis presents a transformerless high step-up DC-DC converter intended for use as an interconnect between DC systems. The converter is required to operate at medium to high voltage (>1kV) and provide high voltage gain (>5). This work details the steady state operation and dynamic model of the proposed converter. The component ratings are identified and converter design limitations are investigated. A 100V:1kV/4kW prototype is produced to verify the analytic steady state model and measure efficiency. An experimental efficiency of 90% was achieved at a step-up ratio of 1:10, however efficiency at low power is limited due to the need to circulate power.

The proliferation of distributed energy resources (DER)s has prompted interest in the expansion of DC power systems. The technological limitations that hinder the expansion of DC power systems are the absence of DC circuit breakers and high step-up/high step-down DC converters for interconnecting DC systems. This thesis presents a transformerless high step-up DC-DC converter intended for use as an interconnect between DC systems. The converter is required to operate at medium to high voltage (>1kV) and provide high voltage gain (>5). This work details the steady state operation and dynamic model of the proposed converter. The component ratings are identified and converter design limitations are investigated. A 100V:1kV/4kW prototype is produced to verify the analytic steady state model and measure efficiency. An experimental efficiency of 90% was achieved at a step-up ratio of 1:10, however efficiency at low power is limited due to the need to circulate power.

<p>Copper (Cu) has been used as the main conductor in interconnects due to its low resistivity. However, because of its high diffusivity, diffusion barriers/liners (tantalum nitride/tantalum; TaN/Ta) must be incorporated to surround Cu wires. Otherwise, Cu ions/atoms will drift/diffuse through the inter-metal dielectric (IMD) that separates two distinct interconnects, resulting in circuit shorting and chip failures. The scaling limit of conventional Cu diffusion barriers/liners has become the bottleneck for interconnect technology, which in turn limits the IC performance. The interconnect half-pitch size will reach ~20 nm in the coming sub-5 nm technology nodes. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be > 4 nm to ensure acceptable liner and diffusion barrier properties. Since TaN/Ta occupy a significant portion of the interconnect cross-section and they are much more resistive than Cu, the effective conductance of an ultra-scaled interconnect will be compromised by the thick bilayer. Therefore, two dimensional (2D) layered materials have been explored as diffusion barrier alternatives owing to their atomically thin body thicknesses. However, many of the proposed 2D barriers are prepared at too high temperatures to be compatible with the back-end-of-line (BEOL) technology. In addition, as important as the diffusion barrier properties, the liner properties of 2D materials must be evaluated, which has not yet been pursued. </p> The objective of the thesis is to develop a 2D barrier/liner that overcomes the issues mentioned. Therefore, we first visit various 2D layered materials to understand their fundamental capability as barrier candidates through theoretical calculations. Among the candidates, hexagonal-boron-nitride (h-BN) and molybdenum disulfide (MoS₂) are selected for experimental studies. In addition to studying their fundamental properties to know their potential, we have also developed techniques that can realize low-temperature-grown 2D layered materials. Metal-organic chemical vapor deposition (MOCVD) is adopted for the synthesis of BEOL-compatible MoS₂. The electrical test results demonstrate the promises of integrating 2D layered materials to the state-of-the-art interconnect technology. Furthermore, by considering not only diffusion barrier properties but also liner properties, we develop another 2D layered material, tantalum sulfide (TaS_x), using plasma-enhanced chemical vapor deposition (PECVD). The TaS_x is promising in both barrier and liner aspects and is BEOL-compatible. Therefore, we believed that the conventional TaN/Ta bilayer stack can be replaced with an ultra-thin TaS_x layer to maximize the Cu volume for ultra-scaled interconnects and improve the performance. Furthermore, Since via resistance has become the bottleneck for overall interconnect performance, we study the vertical conduction of TaS_x. Both the intrinsic and extrinsic properties of this material are investigated and engineering approaches to improve the vertical conduction are also tested. Finally, we explore the possibilities of benefiting from 2D materials in other applications and propose directions for future studies.

Les contraintes économiques actuelles amènent les entreprises d'électronique non seulement à innover à un rythme très soutenu mais aussi à réduire le cycle de conception des nouveaux produits. Afin de rester compétitives, ces entreprises doivent proposer régulièrement de nouveaux produits comportant de nouvelles fonctionnalités, ou améliorant les performances des produits de la génération précédente. Les progrès réalisés peuvent être quantifiés par exemple en terme de vitesse de fonctionnement, encombrement, autonomie et consommation d'énergie. La conception des cartes électroniques incluant ces contraintes est alors délicate. En effet, l'intégration de nouvelles fonctions tout comme la miniaturisation des produits entraînent une densification du circuit imprimé. Le nombre de couches utilisé augmente, l'isolement entre les signaux diminue, l'utilisation de circuits intégrés comportant différentes fonctions comme les SOC ou les SIP entraîne une multiplication du nombre de potentiels d'alimentation. L'augmentation des performances des systèmes impliquent une élévation du taux de débits de données circulant au sein du circuit imprimé et par conséquent l'augmentation des fréquences d'horloge et des signaux. Ces contraintes entraînent l'apparition de problèmes de compatibilité électromagnétique, d'intégrité du signal et d'intégrité de puissance. Il est alors nécessaire de limiter les risques de dysfonctionnement de la carte par une maîtrise des phénomènes qui se produisent d'une part par une analyse de dimensionnement précise afin d'éliminer ou de réduire les problèmes au plus tôt dans la phase de conception et d'autre part en effectuant des simulations de validation une fois la carte terminée. Cette thèse proposée par la société Thales Communications and Security en collaboration avec le laboratoire des Systèmes et Applications des Technologies de l'Information et de l’Énergie (SATIE) de l’École Normale Supérieure de Cachan dans le cadre d'une Convention Industrielle de Formation par la REcherche (CIFRE) a pour but le développement d'une méthodologie d'analyse et de conception du réseau du distribution d'énergie de cartes numériques complexes dans le but de garantir leur fonctionnement sans, ou en réduisant le nombre d'itérations de prototypage. L'introduction au contexte, une description du système étudié et des phénomènes physiques régissant son fonctionnement ainsi qu'un état de l'art des techniques d'analyse d'intégrité de puissance constituent le premier chapitre de ce mémoire. La présentation du véhicule de test, support de tous les résultats de mesure, conçu durant la deuxième année de thèse est l'objet du second chapitre. Ce chapitre dénombre et décrit l'ensemble des scenarii et des réalisations créés pour la mesure des phénomènes propres à l'intégrité de puissance et la corrélation de résultats de simulation avec ceux obtenus en mesure. Dans une troisième partie, les techniques de modélisations de chaque élément constituant le réseau de distribution d'énergie sont décrites. Afin de démontrer la validité des modèles utilisés, les résultats de simulation obtenus pour chaque élément ont été confrontés à des résultats de mesure. Le quatrième chapitre présente la méthodologie de conception et d'analyse de la stabilité des alimentations développée suite aux résultats obtenus des différentes techniques de modélisation. Les outils utilisés sont précisément décrits et les résultats de simulation confrontés à ceux de mesure du système complet du véhicule de test. Dans le chapitre 5, l'intérêt de la modélisation des réseaux de distribution d'énergie sera étendu aux études d'intégrité du signal en démontrant comment son inclusion aux simulations permet d'obtenir, lors de la mise en œuvre de co-simulations, des résultats de simulation plus proches de la réalité. Enfin, la dernière partie de ce document synthétise les travaux de la thèse, porte un regard critique et propose quelques perspectives de travaux futurs. / Today's economical context leads electronics and high-tech corporations not only to innovate with a sustained rhythm but also to reduce the design cycle of new products. In order to remain competitive, these corporations must release regularly new products with new functionalities or enhancing performances of the last generation of this product. The enhancement from one generation of the product to the other can be quantified by the speed of execution of a task, the package size or form factor, the battery life and power consumption.The design methodology following these constraints is thus very tough. Indeed, integration of new functionalities as miniaturization of products imply a densification of the printed circuit board. The number of layer in the stack up is increased, isolation between nets is reduced, the use of integrated circuits embedding different functions as SOC or SIP implies a multiplication of the number of voltages. Moreover the increase of circuit performances implies a increasing data rate exchanged between component of the same printed circuit board and occasioning a widening of the reference clock and signal frequency spectrum. These design constraints are the root cause of the apparition of electromagnetic compatibility, signal integrity and power integrity issues. Failure risks must then be limited by fully understanding phenomenon occurring on the board by, on one side, realizing a precise dimensioning pre layout analysis aiming the elimination or reduction of the issues at the beginning of the design cycle, and on the other side, validating the layout by post layout simulation once the printed circuit board routed.This study proposed by Thales Communication and Security in collaboration with public research laboratory SATIE (System and Application of Energy and Information Technologies) of Ecole Normale Supérieure de Cachan within a industrial convention for development through research aims to develop a design methodology for power delivery network of digital printed circuit board with the goal of ensuring good behavior without or by reducing the number of prototypes.The first chapter of this manuscript include an introduction to the context of the study, a precise description of the studied system and the physical phenomenon ruling its behavior, and finally a state of the art of the power integrity technique analysis. A presentation of the test vehicle, designed during the work and support of all measurement results will constitute the focus of second chapter. This chapter presents and describes all the scenarios and implementations created for the observation and measurement of Power Integrity phenomenon and realise measurement-simulation results correlation. In a third part, modeling techniques of each element of the Power Delivery Network are described. The validity of the models is proven by correlating simulation results of each element with measurement results. The fourth chapter presents the analysis and design methodology developed from the results of the different modeling techniques presented in the previous chapter. Simulation tools and their configuration are precisely described and simulation results are compared with measurement results obtained on the test vehicle for the whole system. In the fifth chapter, the interest of power delivery network model will be extended to signal integrity analysis demonstrating how including this model allows to obtain simulation results closer from measurement results by running Signal Integrity Power aware simulation. Finally, the last part of this document synthetizes the work realized and presented in this document, takes a critical look on it and proposes future works and orientations to extend knowledges and understanding of Power Integrity Phenomenon.

This work deals with COMBO2 card interconnect and memory devices testing. In the beginning of the paper, some existing testing algorithms for interconnect and RAM memories testing are introduced. This work is devoted to proposal of generic architecture for interconnect and memory devices testing. The proposed architecture is optimized for FPGA implementation.

It is expected that nano-scale devices and interconnections will introduce unprecedented level of defects in the substrates, and architectural designs need to accommodate the uncertainty inherent at such scales. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause degradation in reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve a specific level of reliability. Analytical probabilistic models to evaluate such reliability-redundancy trade-offs are error prone and cumbersome, and do not scalewell for complex networks of gates. In this thesiswe develop different tools and techniques that can evaluate the reliability measures of combinational circuits, and can be used to analyze reliability-redundancy trade-offs for different defect-tolerant architectural configurations. In particular, we have developed two tools, one of which is based on probabilistic model checking and is named NANOPRISM, and another MATLAB based tool called NANOLAB. We also illustrate the effectiveness of our reliability analysis tools by pointing out certain anomalies which are counter-intuitive but can be easily discovered by these tools, thereby providing better insight into defecttolerant design decisions. We believe that these tools will help furthering research and pedagogical interests in this area, expedite the reliability analysis process and enhance the accuracy of establishing reliability-redundancy trade-off points. / Master of Science

<p>The aim of the research work presented here, is to contribute to the adaptation of electronic packaging towards the needs of high frequency applications. As the field of electronic packaging stretches over several very different professional areas, it takes an interdisciplinary approach to optimize the technology of electronic packaging. Besides this, an extensive knowledge of industrial engineering should be an essential part of this undertaking to improve electronic packaging. Customary advances in technology are driven by new findings and a continuous development of processes in clearly defined fields. However, in the field of the higher levels of the interconnection hierarchy, that is external to the chip level interconnections and chip packaging, it is supposed that a wide combination of disciplines and technical creativity, instead of advanced technology in a special area should produce most added value.</p><p>The thesis is divided into five areas, interlinked by the overall aim of there advantages to the common goal. These areas are the Printed Wiring Board (PWB) technology, PWB connections using flexible printed circuit boards, multiconductor cable connections, shielded enclosures and the related EMC issues, and finally the cooling of electronics. A central issue was to improve the shielded enclosures to be effective also at very high frequencies; it will be shown that shielded enclosures without apertures can cope with frequencies up to and above 15 GHz. Due to this enclosure without apertures, it was necessary to develop a novel cooling structure. This cooling structure consists of a heat sink where the PCB’s are inserted in close contact to the cooling fins on one side, whereas the other side of the heat sink is cooled by forced ventilation. The heat transfer between these parts is completely inside the same body. Tests carried out on a prototype have shown that the performance of the cooling structure is satisfactory for electronic cooling.</p><p>Another problem area that is addressed are the interconnect problems in high frequency applications. Interconnections between parts of a local electronic system, or as within the telecom and datacom field between subscribers, are commonly accomplished by cable connections. In this research work multiconductor cables are examined and a patented novel cable-connector for high frequency use is presented. Further, an experimental complex soldering method between flexible printed circuits boards and rigid printed circuits boards, as part of connections between PCBs, is shown. Finally, different sectors of the PCB technology for high frequency applications are scrutinized and measurements on microstrip structures are presented.</p>

Plusieurs défis subsistent pour la migration de l’électronique imprimée vers l’industrie, malgré des avancées récentes. Dans ces travaux de thèse, l’optimisation du procédé d’impression d’encres à base de nanoparticules d’argent (<Ø>=25 nm) en fonction de sa rhéologie et des interactions fluide/substrat a permis de réaliser des interconnexions électriques d’une épaisseur de 500 nm. Ces lignes imprimées sur des substrats silicium ou flexibles sont ensuite recuites par des méthodes conventionnelles (étuve ou infrarouge) ou sélectives (micro-onde) à des températures comprises entre 100 et 300°C.Une meilleure compréhension de la relation procédé/microstructure des couches minces imprimées, via plusieurs caractérisations cristallographiques (DRX, EBSD et EDX), a permis d’optimiser la croissance des domaines nanocristallins, activée pour des énergies de l’ordre de 3 à 5 kJ•mol-1. Outre les faibles contraintes résiduelles (70 MPa), cette optimisation permet d’atteindre de faibles résistivités électriques (3.4 µOhm•cm) associées à un accroissement de la cohérence des réseaux cristallins aux joints de grains. La probabilité de réflexion des électrons à ces interfaces peut être davantage réduite, grâce à une approche innovante de croissance orientée des cristallites par interdiffusion atomique à partir du substrat.La faible rigidité mécanique (E<50 GPa) de ces lignes initialement poreuses nécessite une étape de renforcement par texturation ou par croissance electroless pour résister aux étapes de micro-assemblage et de soudure filaire. La réalisation d’un démonstrateur fonctionnel a ainsi permis de valider la technologie d’impression pour la fabrication de composants électroniques. / Several challenges are still holding back the technological transfer of printed electronics to industry in spite of recent progresses. In this thesis work, the printing method of inks based on silver nanoparticles (<Ø>=25 nm) was optimized according to its rheology and to the fluid/substrate interactions for the fabrication of electrical interconnections with a thickness of 500 nm. These lines were printed on silicon or flexible substrates and annealed either by conventional (oven or infrared) or selective methods (microwave) at temperatures comprised between 100 and 300 °C.A better understanding of the relationship between process and microstructure of these printed thin films, based on several crystallographic equipments (XRD, EBSD and EDX), led to the optimization of nanocrystallites growth with an activation energy of about 3 to 5 kJ•mol-1. In addition to the low residual stress (70 MPa), this optimization is used to achieve low electrical resistivity (3.4 μOhm•cm) associated with a greater coherence of the crystal lattices at grain boundaries. The probability of electron scattering at such interfaces can be further reduced using an innovative approach of oriented crystallite growth by atomic interdiffusion from the substrate.The low mechanical stiffness (E<50 GPa) of these porous lines requires a reinforcement step either by crystalline texturation or by electroless growth to withstand the assembly and wire-bonding steps. The fabrication of a functional demonstrator thus validated the printing technology for the manufacture of electronic components.