The rise of superbugs, including antibiotic-resistant bacteria, and virus outbreaks, such as the recent coronavirus scare, illustrate the need for rapid detection of disease pathogens. Widespread availability of rapid disease identification would facilitate outbreak prevention and specific treatment. The ARROW biosensor microchip can directly detect single molecules through fluorescence-based optofluidic interrogation. The nature of the microfluidic channels found on optofluidic sensor platforms sets some of the ultimate sensitivity and accuracy limits and can result in false negative test results. Yet higher sensitivity and specificity is desired through hydrodynamic focusing. Novel 3D hydrodynamic focusing designs were developed and implemented on the ARROW platform, an optofluidic lab-on-a-chip single-molecule detector device. Microchannels with cross-section dimensions smaller than 10 μm were formed using sacrificial etching of photoresist layers covered with plasma-enhanced chemical-vapor-deposited silicon dioxide on a silicon wafer. Buffer fluid carried to the focusing junction enveloped an intersecting sample fluid, resulting in 3D focusing of the sample stream. The designs which operate across a wide range of fluid velocities through pressure-driven flow were integrated with optical waveguides in order to interrogate fluorescing particles and confirm 3D focusing, characterize diffusion, and quantify optofluidic detection enhancement of single viruses on chip.

In this work, an approach for copper atomic layer deposition (ALD) via reduction of CuxO films was investigated regarding applications in ULSI interconnects, like Cu seed layers directly grown on diffusion barriers (e. g. TaN) or possible liner materials (e. g. Ru or Ni) as well as non-ferromagnetic spacer layers between ferromagnetic films in GMR sensor elements, like Ni or Co. The thermal CuxO ALD process is based on the Cu (I) β-diketonate precursor [(nBu3P)2Cu(acac)] and a mixture of water vapor and oxygen ("wet O2") as co-reactant at temperatures between 100 and 130 °C. Highly efficient conversions of the CuxO to metallic Cu films are realized by a vapor phase treatment with formic acid (HCOOH), especially on Ru substrates. Electrochemical deposition (ECD) experiments on Cu ALD seed / Ru liner stacks in typical interconnect patterns are showing nearly perfectly filling behavior. For improving the HCOOH reduction on arbitrary substrates, a catalytic amount of Ru was successful introduced into the CuxO films during the ALD with a precursor mixture of the Cu (I) β-diketonate and an organometallic Ru precursor. Furthermore, molecular and atomic hydrogen were studied as promising alternative reducing agents.

Current electrical systems are faced with the limitation in performance by the electrical interconnect technology determining overall processing speed. In addition, the electrical interconnects containing many long distance interconnects require high power to drive. One of the best ways to overcome these bottlenecks is through the use of optical interconnect to limit interconnect latency and power. This research explores new computer-aided design algorithms for developing optoelectronic systems. These algorithms focus on place and route problems using optical interconnections covering system-on-a-chip design as well as system-on-a-package design. In order to design optoelectronic systems, optical interconnection models are developed at first. The CAD algorithms include optical interconnection models and solve place and route problems for optoelectronic systems. The MCNC and GSRC benchmark circuits are used to evaluate these algorithms.

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

As IC technologies scale to the nanometer regime, efficient and accurate modeling and analysis of VLSI systems with billions of transistors and interconnects becomes increasingly critical and difficult. VLSI systems impacted by the increasingly high dimensional process-voltage-temperature (PVT) variations demand much more modeling and analysis efforts than ever before, while the analysis of large scale on-chip interconnects that requires solving tens of millions of unknowns imposes great challenges in computer aided design areas. This dissertation presents new methodologies for addressing the above two important challenging issues for large scale on-chip interconnect modeling and analysis: In the past, the standard statistical circuit modeling techniques usually employ principal component analysis (PCA) and its variants to reduce the parameter dimensionality. Although widely adopted, these techniques can be very limited since parameter dimension reduction is achieved by merely considering the statistical distributions of the controlling parameters but neglecting the important correspondence between these parameters and the circuit performances (responses) under modeling. This dissertation presents a variety of performance-oriented parameter dimension reduction methods that can lead to more than one order of magnitude parameter reduction for a variety of VLSI circuit modeling and analysis problems. The sheer size of present day power/ground distribution networks makes their analysis and verification tasks extremely runtime and memory inefficient, and at the same time, limits the extent to which these networks can be optimized. Given today?s commodity graphics processing units (GPUs) that can deliver more than 500 GFlops (Flops: floating point operations per second). computing power and 100GB/s memory bandwidth, which are more than 10X greater than offered by modern day general-purpose quad-core microprocessors, it is very desirable to convert the impressive GPU computing power to usable design automation tools for VLSI verification. In this dissertation, for the first time, we show how to exploit recent massively parallel single-instruction multiple-thread (SIMT) based graphics processing unit (GPU) platforms to tackle power grid analysis with very promising performance. Our GPU based network analyzer is capable of solving tens of millions of power grid nodes in just a few seconds. Additionally, with the above GPU based simulation framework, more challenging three-dimensional full-chip thermal analysis can be solved in a much more efficient way than ever before.

Die vorliegende Arbeit verfolgt das Ziel, Cu(Ag)-Dünnschichten als potentiellen Werkstoff für Leiterbahnen in der Mikroelektronik zu untersuchen. Für die Beurteilung dieses Materialsystems wurden vier Schwerpunkte bezüglich der Schichtcharakterisierung definiert: Herstellung, Gefüge, thermomechanische Eigenschaften, Elektromigrationsresistenz. Grundlage sämtlicher Untersuchungen ist eine geeignete Probenpräparation. In Anlehnung an Technologien, die zur Zeit bei der Herstellung von reinen Cu-Leiterbahnen Anwendung finden, erfolgte die Beschichtung der Cu(Ag)-Schichten (Dicke bis 1 µm) galvanisch aus einem schwefelsauren Elektrolyten unter Additiveinsatz auf thermisch oxidierten Siliziumwafern. Hierbei war nicht nur die Abscheidung von ganzflächigen Dünnschichten, sondern auch die Beschichtung auf strukturierte Substrate von Interesse. Die erzeugten Schichtproben werden in ihren Gefügeeigenschaften, vergleichend zu reinen Kupferschichten, charakterisiert. Hierzu zählen Korngrößen und -orientierungen, thermisches Gefügeverhalten, Einbau, Verteilung und Segregation von Silber und Fremdstoffen sowie die elektrischen Eigenschaften. Von grundsätzlicher Bedeutung für das Elektromigrationsverhalten und damit für die Zuverlässigkeit und das Leistungsvermögen sind die thermomechanischen Eigenschaften. Diese werden an ausgedehnten Schichten mit der Substratkrümmungsmessung bis zu Temperaturen von 500°C beschrieben. Die Diskussion des mechanischen Schichtverhaltens umfasst sowohl thermische als auch temporale Charakteristika. Die Untersuchungen geben einen Einblick in die wirkenden Mechanismen des Stofftransports und des Spannungsabbaus. Den Abschluss der Arbeit stellen erste Experimente zum Elektromigrationsverhalten der Cu(Ag)-Dünnschichten dar. Den Kern dieser Analysen bilden Messungen an sog. Blech-Strukturen (Materialdriftexperimente). Hierbei werden geeignete Technologien für die mikrotechnologische Herstellung von derartigen Cu(Ag)-Strukturen vorgestellt. Anhand erster Messungen wird das Elektromigrationsverhalten von Cu(Ag)-Metallisierungen in seinen Grundcharakteristika beschrieben.

La photonique sur silicium constitue une plateforme idéale pour transmettre et distribuer des signaux optiques au sein d'une puce et sur de longues distances sans pertes excessives. L'intégration de semiconducteurs III-V sur des circuits photonique en silicium est un projet excitant mais ambitieux, que nous avons mené en combinant le meilleur de l'optoélectronique des semiconducteurs III-V et des technologies photonique en siliicium-sur-isolant (SOI en anglais). Afin de pouvoir remplacer les interconnexions metalliques existantes par des interconnexion optiques, nous nous sommes efforcés d'utiliser les objets ayant les dimensions les plus petites et consommant les plus petites énergies comme peuvent l'être les nanocavités en Cristaux Photoniques incorporant des matériaux actifs en III-V. Cette thèse visait à conceptualiser, fabriquer et étudier expérimentalement des structures hybrides III-V/circuit photonique SOI, où une couche de III-V, reportée par collage adhésif à quelques centaines de nm du silicium, est gravée en une cavité optique de type cristal photonique " nanobeam " et résonante autour de 1.5 μm. Les principaux résultats de ce travail sont les démonstration 1) d'une efficacité de couplage entre la cavité et le guide d'onde SOI facilement ajustable, pouvant excéder 90% lorsque les conditions d'accord de phase sont remplies, 2) de l'émission laser en régime continue avec des puits quantiques via la passivation des surfaces, et 3) d'une mémoire optique de durée supérieure à 2s avec des énergies de commutations ultrafaibles (~0.4 fJ). Nous présentons aussi un modèle pour fabriquer des cavités " nanobeam " de facteurs Q très élevés, encapsulées dans un matériau bas indice.

(ULSI) causes an increase of the resistance of the wiring system by increased scattering of electrons at side walls and grain boundaries in the state of the art Cu technology, which increases the RC delay of the interconnect system and thus degrades the performance of the device. The outstanding properties of carbon nanotubes (CNT) such as a large mean free path, a high thermal conductance and a large resistance against electromigration make them an ideal candidate to replace Cu in future feature nodes. The present thesis contributes to the preparation and properties of CNT based vertical interconnections (vias). In addition, all processes applied during the fabrication are compatible to ULSI and an interface between CNT based vias and a Cu metallization is studied. The methodology for the evaluation of CNT based vias is improved; it is highlighted that by measuring the resistance of one multiwall CNT and taking into account the CNT density, the performance of the CNT based vias can be predicted accurately. This provides the means for a systematic evaluation of different integration procedures and materials. The lowest contact resistance is obtained for carbide forming metals, as long as oxidation during the integration is avoided. Even though metal-nitrides exhibit an enhanced contact resistance, they are recommended to be used at the bottom metallization in order to minimize the oxidation of the metal-CNT contact during subsequent processing steps. Overall a ranking for the materials from the lowest to the highest contact resistance is obtained: Ta < Ti < TaN < TiN « TiO2 « Ta2O5 Furthermore the impact of post CNT growth procedures as chemical mechanical planarization, HF treatment and annealing procedures after the CNT based via fabrication are evaluated. The conductance of the incorporated CNTs and the applicable electrical transport regime relative to the CNT quality and the CNT length is discussed. In addition, a strong correlation between the temperature coefficient of resistance and the initial resistance of the CNT based vias at room temperature has been observed. / Die kontinuierliche Miniaturisierung der charakteristischen Abmessungen in hochintegrierten Schaltungen (ULSI) verursacht einen Anstieg des Widerstandes im Zuleitungssystem aufgrund der erhöhten Streuung von Elektronen an Seitenwänden und Korngrenzen in der Cu-Technologie, wodurch die Verzögerungszeit des Zuleitungssystems ansteigt. Die herausragenden Eigenschaften von Kohlenstoffnanoröhren (CNT), wie eine große mittlere freie Weglänge, hohe thermische Leitfähigkeit und eine starke Resistenz gegenüber Elektromigration machen diese zu einem idealen Kandidaten, um Cu in zukünftigen Technologiegenerationen zu ersetzen. Die vorliegende Arbeit beschreibt die Herstellung und daraus resultierenden Eigenschaften von Zwischenebenenkontakten (Vias) basierend auf CNTs. Alle verwendeten Prozessierungsschritte sind kompatibel mit der Herstellung von hochintegrierten Schaltkreisen und eine Schnittstelle zwischen den CNT Vias und einer Cu-Metallisierung ist vorhanden. Insbesondere das Verfahren zur Evaluierung von CNT Vias wurde durch den Einsatz verschiedener Methoden verbessert. Insbesondere soll hervorgehoben werden, dass durch die Messung des Widerstandes eines einzelnen CNTs, bei bekannter CNT Dichte, der Via Widerstand sehr genau vorausgesagt werden kann. Dies ermöglicht eine systematische Untersuchung des Einflusses der verschiedenen Prozessschritte und der darin verwendeten Materialien auf den Via Widerstand. Der niedrigste Kontaktwiderstand wird für Karbidformierende Metalle erreicht, solange Oxidationsprozesse ausgeschlossen werden können. Obwohl Metallnitride einen höheren Kontaktwiderstand aufweisen, sind diese für die Unterseitenmetallisierung zu empfehlen, da dadurch die Oxidation der leitfähigen Schicht minimiert wird. Insgesamt kann eine Reihenfolge beginnend mit dem niedrigsten zum höchsten Kontaktwiderstand aufgestellt werden: Ta < Ti < TaN < TiN « TiO2 « Ta2O5 Desweiteren wurde der Einfluss von Verfahren nach dem CNTWachstum wie die chemischmechanische Planarisierung, eine HF Behandlung und einer Temperaturbehandlung evaluiert, sowie deren Einfluss auf die elektrischen Parameter des Vias untersucht. Die Leitfähigkeit der integrierten CNTs und die daraus resultierenden elektrischen Transporteigenschaften in Abhängigkeit der CNT Qualität und Länge werden besprochen. Ebenso wird die starke Korrelation zwischen dem Temperaturkoeffizienten des elektrischen Widerstandes und des Ausgangswiderstandes der CNT basierten Vias bei Raumtemperatur diskutiert.

The deposition of Cu seed layers for electrochemical Cu deposition (ECD) via atomic layer deposition (ALD) of copper oxide and subsequent thermal reduction at temperatures between 110 and 120°C was studied on different diffusion barrier systems. While optimization of the process is required on TaN with respect to reduction and plating, promising results were obtained on blanket PVD Ru. The plating results on layers of ALD Cu with underlying Ru even outperformed the ones achieved on PVD Cu seed layers with respect to morphology and resistivity. Applying the processes to via and line patterns gave similar results, suggesting that a combination of ALD Cu with PVD or ALD-grown Ru could significantly improve the ECD Cu growth.

This dissertation describes the development, design, implementation and evaluation of a data acquisition system, with the main aim of using it for data collection on a laboratory pilot ball mill. An open-source prototype hardware platform was utilised in the implementation of the data acquisition function, however, with limitations. An analogue signal conditioning card has been successfully developed to interface the analogue signals to the dual domain ADC module. Model-based software development was used to design and develop the algorithms to control the DAS acquisition process, but with limited capabilities. A GUI application has been developed and used for the collection and storage of the raw data on the host system. The DAS prototype was calibrated and collected data successfully through all the channels; however, the input signal bandwidth was limited to 2Hz. / Electrical and Mining Engineering / M. Tech. (Electrical Engineering)