The following is the accepted manuscript of the original article: Marcel Melzer, Thomas Waechtler, Steve Müller, Holger Fiedler, Sascha Hermann, Raul D. Rodriguez, Alexander Villabona, Andrea Sendzik, Robert Mothes, Stefan E. Schulz, Dietrich R.T. Zahn, Michael Hietschold, Heinrich Lang and Thomas Gessner “Copper oxide atomic layer deposition on thermally pretreated multi-walled carbon nanotubes for interconnect applications”, Microelectron. Eng. 107, 223-228 (2013). Digital Object Identifier: 10.1016/j.mee.2012.10.026 Available via http://www.sciencedirect.com or http://dx.doi.org/10.1016/j.mee.2012.10.026 © 2013 Elsevier B.V. Carbon nanotubes (CNTs) are a highly promising material for future interconnects. It is expected that a decoration of the CNTs with Cu particles or also the filling of the interspaces between the CNTs with Cu can enhance the performance of CNT-based interconnects. The current work is therefore considered with thermal atomic layer deposition (ALD) of CuxO from the liquid Cu(I) β-diketonate precursor [(nBu3P)2Cu(acac)] and wet oxygen at 135°C. This paper focuses on different thermal in-situ pre-treatments of the CNTs with O2, H2O and wet O2 at temperatures up to 300°C prior to the ALD process. Analyses by transmission electron microscopy show that in most cases the CuxO forms particles on the multi-walled CNTs (MWCNTs). This behavior can be explained by the low affinity of Cu to form carbides. Nevertheless, also the formation of areas with rather layer-like growth was observed in case of an oxidation with wet O2 at 300°C. This growth mode indicates the partial destruction of the MWCNT surface. However, the damages introduced into the MWCNTs during the pre treatment are too low to be detected by Raman spectroscopy.

The objective of this research is to demonstrate the impact of interconnect process variations, line-edge roughness and size effects on interconnect effective resistivity and ultimately chip performance. The investigation is accomplished through five tasks. In Task I, a new closed-form effective resistivity model, which is a function of line-edge roughness (LER), surface specularity and grain boundary reflectivity, is derived. In Task II, a critical path model is enhanced by including interconnect parasitics using the model in Task I. This enhancement also involves an extensive survey of foundry process data to shed light on the device resistance estimation used in the critical path model in Task II. Task III develops a Monte Carlo (MC) simulation framework called the Fast Interconnect Statistical Simulator (FISS). Using the latest International Technology Roadmap for Semiconductors (ITRS) projections, the FISS projects the impact of interconnect process variations and size effects onto high performance microprocessor units (HP-MPUs). Task IV fabricates metallic interconnect test structures with sub-100nm line-widths. The fifth task statistically calibrates the model from Task I using resistivity data measured from the test structures in Task IV.

The impact of physical design characteristics on backend dielectric reliability was modeled. The impact of different interconnect geometries on backend low-k time dependent dielectric breakdown was reported and modeled. Physical design parameters that are crucial to backend dielectric reliability were identified. A methodology was proposed for determining chip reliability but combining the insights gathered by modeling the impact of physical design on backend dielectric breakdown. A methodology to model variation in device parameters and characteristics was proposed. New methods of electrical and physical parameter extraction were proposed. Models that consider systematic and random source of variation in electrical and physical parameters of CMOS devices were proposed, to aid in circuit design and timing analysis.

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, therby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniatrurization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse and limits the usability of clustered architectures in smaller technologies. In the past, study of leakage energy management at the architectural level has mostly focused on storage structures such as cache. Relatively, little work has been done on architecture level leakage energy management in functional units in the context of superscalar processors and energy efficient scheduling in the context of VLIW architectures. In the absence of any high level model for interconnect energy estimation, the primary focus of research in the context of interconnects has been to reduce the latency of communication and evaluation of various inter-cluster communication models. To the best of our knowledge, there has been no such work in the past from the point of view of enegy efficiency targeting clustered VLIW architectures specifically focusing on smaller technologies. Technological advancements now permit design of interconnects and functional units With varying performance and power modes. In thesis we people scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low power modes of interconnects and functional units . We also propose a high level model for estimation of interconnect delay and energy (in contrast to low-level circuit level model proposed earlier) that makes it possible to carry out architectural and compiler optimizations specifically targeting the inter connect, Finally we present synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improve the usability of clustered architectures by archiving better overall energy-performance trade-offs. Our compiler assisted leakage energy management scheme for functional units reduces the energy consumption of functional units approximately by 15% and 17% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively with negligible performance degradation over and above that offered by a hardware-only scheme. The interconnect energy optimization scheme improves the energy consumption of interconnects on an average by 41% and 46% for a 2-clustered and a 4-clustered machine respectively with 2% and 1.5% performance degradation. The combined scheme options slightly better energy benefit in functional units and 37% and 43% energy benefit in interconnect with slightly higher performance degradation. Even with the conservative estimates of contribution of functional unit interconnect to overall processor energy consumption the proposed combined scheme obtains on an average 8% and 10% improvement in overall energy delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine respectively. We present a detailed experimental evaluation of the proposed schemes using the Trimaran compiler infrastructure.

Decades of efforts have pushed the replacement of electrical interconnects by optical links to the interconnects between computers, racks and circuit boards. It may be expected that optical solutions will further be used for inter-chip and intra-chip interconnects with potential benefits in bandwidth, capacity, delay, power consumption and crosstalk. Silicon integration is emerging to be the best candidate nowadays due to not only the dominant status of silicon in microelectronics but also the great advantages brought to the photonic integrated circuits (PICs). Regarding the recent breakthroughs concerning active devices on silicon substrate, the question left is no longer the feasibility of the optical interconnects based on silicon but the competitiveness of the silicon device compared with other alternatives. This thesis focuses on the study of two key components for the optical interconnects, both especially designed and fabricated for silicon platform. One is a high speed electroabsorption modulator (EAM), realized by transferring an InP-based segmented design to the hybrid silicon evanescent platform. The purpose here is to increase the speed of the silicon PICs to over 50  Gb/s or more. The other one is a high performance grating coupler, with the purpose to improve the optical interface between the silicon PICs and the outside fiber-based communication system. An general approach based on the transmission line analysis has been developed to evaluate the modulation response of an EAM with a lumped, traveling-wave, segmented or capacitively-loaded configuration. A genetic algorithm is used to optimize its configuration. This method has been applied to the design of the EAMs on hybrid silicon evanescent platform. Based on the comparison of various electrode design, segmented configuration is adopted for the target of a bandwidth over 40 GHz with as low as possible voltage and high extinction ratio. In addition to the common periodic analysis, the grating coupler is analyzed by the antenna theory assisted with an improved volume-current method, where the directionality of a grating coupler can be obtained analytically. In order to improve the performance of the grating coupler, a direct way is to address its shortcoming by e.g. increasing the coupling efficiency. For this reason, a nonuniform grating coupler with apodized grooves has been developed with a coupling efficiency of 64%, nearly a double of a standard one. Another way is to add more functionalities to the grating coupler. To do this, a polarization beam splitter (PBS) based on a bidirectional grating coupler has been proposed and experimentally demonstrated. An extinction ratio of around -20 dB, as well as a maximum coupling efficiency of over 50% for both polarizations, is achieved by such a PBS with a Bragg reflector underneath. / QC 20100906

Les objectifs de ces travaux de recherche portent sur le développement d'outils d'évaluation des performances électriques des interconnexions de circuits intégrés des générations sub-CMOS 65 nm et sur la proposition de solutions d'optimisation de ces performances, permettant à la fois de maximiser la rapidité des circuits et de minimiser les niveaux de diaphonie. Cette optimisation est obtenue en jouant sur les largeurs et les espacements des interconnexions mais aussi sur le nombre et de taille des répéteurs placés à leurs interfaces. Une attention toute particulière a également été portée sur la réduction de la complexité de ces réseaux d'interconnexions. Pour ce faire, un simulateur basé sur des modèles de propagation des signaux a été construit. Pour les composants passifs les données d'entrée du simulateur sont issues de modélisations fréquentielles électromagnétiques précises ou de résultats de caractérisation hyperfréquences et, pour les composants actifs que sont les répéteurs, de modèles électriques fournis par des partenaires spécialistes des technologies MOS. Le travail de modélisation s'est focalisé tout particulièrement sur cinq points : la modélisation de réseaux couplés complexes, le passage dans le domaine temporel à partir de mesures fréquentielles discrètes limitées, la vérification de la causalité des signaux temporels obtenus, la modélisation de l'environnent diélectrique incluant notamment les pertes et la présence éventuelles de conducteurs flottants et enfin l'intégration de la connaissance des charges aux interfaces des interconnexions. La problématique de la mesure a elle même été adressée puisqu'une procédure dite de « de-embedding » est proposée, spécifiquement dédiée à la caractérisation aux hautes fréquences de dispositifs passifs enfouis dans le BEOL. Sont investiguées enfin des solutions de fonctionnalisation alternatives des interconnexions tirant bénéfice des couplages très forts existant dans le BEOL des technologies sub-CMOS 65 nm. Les résultats de simulations ont souligné un certain nombre de difficultés potentielles notamment le fait que les performances des technologies CMOS sur la voie « more Moore » allait requérir plus que jamais depuis la génération 45 nm une approche globalisée et rationnelle de la réalisation des circuits. / X

La technologie de l’électrolyse de la vapeur d’eau à haute température (EVHT) est unesolution alternative à la production d’hydrogène. Le principe est inversé à celui d’une pile àcombustible de type SOFC : on utilise la vapeur d’eau et de l’électricité afin de produire del’hydrogène. Une difficulté technique majeure repose sur la mise au point d’interconnecteursfonctionnant efficacement sur le long terme. Sur le plan électrique, l’interconnecteur doitprésenter une valeur de résistance de contact aux électrodes la plus faible possible, car elleaffecte directement le rendement de conversion électrochimique (eau en hydrogène) et peutpénaliser le procédé. Il ne doit donc pas présenter une cinétique d’oxydation élevée ni formerdes oxydes isolants électriquement. Sur le plan chimique, l’interconnecteur doit être résistantà l’oxydation sous atmosphère riche en oxygène côté anode et riche en vapeur d’eau côtécathode. De plus, le problème de la volatilisation des oxydes de chrome, qui peuvent diffuseret empoisonner les électrodes, déterminant ainsi une réduction de l’activité électrochimique etdes performances du « stack » sur des longues durées de fonctionnement, doit être réduit. Latempérature de fonctionnement comprise entre 700 et 900°C permet l’utilisationd’interconnecteurs métalliques, qui présentent l’avantage d’une mise en oeuvre plus facile etd’un coût plus faible par rapport aux interconnecteurs céramiques.Dans cette étude, deux matériaux ont été testés en tant qu’interconnecteurs pour lessystèmes EVHT : un acier ferritique chromino-formeur K41X et un alliage Fe-Ni-Co necontenant pas de chrome. Le comportement envers la corrosion à haute température et laconductivité électrique des deux alliages ont été évalués à 800°C sous un mélange 95%O2-5%H2O, pour le côté anodique, et 10%H2-90%H2O, pour le côté cathodique. Pour l’alliageK41X, l’effet de l’état initial de la surface des échantillons sur la nature des oxydes formés àhaute température sous mélange H2-H2O a été pris en compte, à travers une comparaison desalliages bruts de laminage avec des surfaces polies miroir. L’effet d’une pré-oxydation decourte durée à 800°C sur le comportement à haute température de l’alliage K41X brut deréception sous atmosphère H2-H2O a également été évalué. Mais, le travail le plus original decette étude a consisté à effectuer des essais de marquage à l’or et des marquages isotopiquessous mélange H216O-H218O, H2-D2O et D2-H2O. Ces tests ont permis d’étudier lesmécanismes responsables de la croissance de la couche de corrosion de l’alliage K41X brut deréception et poli miroir à 800°C sous atmosphère H2-H2O et d’évaluer le rôle de la vapeurd’eau et de l’hydrogène dans le mécanisme d’oxydation / The high temperature water vapour electrolysis offers a promising method for highlyefficient hydrogen production. It works as an inverse solid oxide fuel cell, using water vapourand electricity in order to produce hydrogen. A major technical difficulty related to hightemperature water vapour electrolysis (HTVE) is the development of interconnects workingefficiently on a long period. From the electrical point of view, the interconnect must have alow contact resistance with the electrodes. Indeed, it directly affects the electrochemicalconversion efficiency (water into hydrogen) and it can penalize the process. The interconnectmust present a slow oxidation kinetics and form as less as possible electrical insulatingoxides. From the chemical point of view, the interconnect has to be resistant against oxidationin an oxygen rich atmosphere (anode side) and water vapour rich atmosphere (cathode side).Moreover, the problem of the volatility of chromium oxide species, which might migrate andpoison the electrodes, leading to a decrease in their electrochemical activity and degradationof stack performance, over long-term operation, needs to be reduced. The operatingtemperature between 700°C and 900°C allows the use of metallic interconnects, which havehigher electrical and thermal conductivities, easier shaping and lower cost, with respect to theceramic materials.In this study, two materials were tested as interconnects for the HTVE systems: a ferriticchromia-forming alloy, the K41X, and a Fe-Ni-Co alloy, which does not contain chromium.High temperature corrosion behaviour and electrical conductivity were tested in both anode(95%O2-5%H2O) and cathode (10%H2-90%H2O) atmospheres at 800°C. Moreover, for theK41X alloy, the effect of the initial surface state of the samples on the chemical nature of theoxides formed at 800°C in H2-H2O atmosphere was evaluated, by comparing as received andmirror polished surfaces. The effect of a short-term air preoxidation at 800°C on the hightemperature behaviour of the K41X as received sample in H2-H2O atmosphere was tested.The most original part of this study consisted in the investigation of the oxidation mechanismsof both as received and mirror polished K41X samples at 800°C in H2-H2O atmosphere bymeans of marking experiments using Au and isotopes (H216O-H218O mixture). Moreover,marking tests using H2-D2O and D2-H2O were carried out, in order to further investigate therole of hydrogen and water vapour in the oxidation mechanism

Single-Walled Carbon Nanotube (SWCNT) based Very Large Scale Integrated circuit (VLSI) interconnect is one of the emerging technologies, and has the potential to overcome the thermal issues persisting even with the advanced copper based interconnect. This is because of it’s promising electrical and thermal transport properties. It can be stated that thermal energy transport in SWCNTs is highly anisotropic due to the quasi one dimensionality, and like in other allotropes of carbon, phonons are the dominant energy carriers of heat conduction. In case of conventional interconnect materials, copper and aluminium, although their thermal conductivity varies over orders of magnitude at temperatures below100 K, near room temperature and above they have almost constant value. On the other hand, the reported experimental studies on suspended metallic SWCNTs illustrate a wide variation of the longitudinal lattice thermal conductivity (κl) with respect to the temperature(T)and the tube length(L)at low, room and high temperatures. Physics based analytical formulation of κl of metallic SWCNT as a function of L and T is essential to efficiently quantify this emerging technology’s impact on the rising thermal management issues of Integrated Circuits. In this work, a physics based diameter independent analytical model for κl of metallic SWCNT is addressed as a function of Lover a wide range of T. Heat conduction in metallic SWCNTs is governed by three resistive phonon scattering processes; second order three phonon Umklapp scattering, mass difference scattering and boundary scattering. For this study, all the above processes are considered, and the effective mode dependent relaxation time is determined by the Matthiessen’s rule. Phonon Boltzmann transport equation under the single mode relaxation time approximation is employed to derive the non-equilibrium distribution function. The heat flux as a function of temperature gradient is obtained from this non-equilibrium distribution function. Based on the Fourier’s definition of thermal conductivity, κl of metallic SWCNT is formulated and the Debye approximations are used to arrive at analytical model. The model developed is validated against both the low and high temperature experimental investigations. At low temperatures, thermal resistance of metallic SWCNT is due to phonon-boundary scattering process, while at high temperatures it is governed by three phonon Umklapp scattering process. It is understood that apart from form factor due to mass difference scattering, boundary scattering also plays the key role in determining the peak value. At room temperature, κl of metallic SWCNT is found to be an order of magnitude higher than that of most of metals. The reason can be attributed to the fact that both sound velocity and Debye temperature which have direct effect on the phonon transport in a solid, are reasonably higher in SWCNTs. Though Umk lapp processes reduce the κl steeper than 1/T beyond room-temperature, it’s magnitude is round1000 W/m/K upto 800 K for various tube lengths, which confirms that this novel material is indeed an efficient conductor of heat also, at room-temperature and above.

This work deals with techniques of time-domain analysis of interconnects. After a studying crucial issue of time-domain analysis of interconnects methods of modeling and simulation simple interconnects in electrotechnics are described. For transient effect analysis two elementary methods can be used: the state variable method and the FDTD (Finite - Difference Time - Domain) method. The FDTD method can be used to solve partial differential equations in time domain, for instance equations of transmission lines. The method is very effective and delivers satisfactory results in case of linear and non-linear lines with a single “live” conductor. The method can be easily programmed in Matlab.

Current trends in electronic industry, such as Internet of Things (IoT) and Cloud Computing call for high interconnect bandwidth, increased number of active devices and high IO count. Hence the integration of on silicon optical waveguides becomes an alternative approach to cope with the performance demands. The application and fabrication of horizontal (planar) and vertical (Through Silicon Vias - TSVs) optical waveguides are discussed here. Coupling elements are used to connect both waveguide structures. Two micro-structuring technologies for integration of coupling elements are investigated: μ-mirror fabrication by nanoimprint (i) and dicing technique (ii). Nanoimprint technology creates highly precise horizontal waveguides with polymer (refractive index nC = 1.56 at 650 nm) as core. The waveguide ends in reflecting facets aligned to the optical TSVs. To achieve Total Internal Reflection (TIR), SiO2 (nCl = 1.46) is used as cladding. TSVs (diameter 20-40μm in 200-380μm interposer) are realized by BOSCH process1, oxidation and SU-8 filling techniques. To carry out the imprint, first a silicon structure is etched using a special plasma etching process. A polymer stamp is then created from the silicon template. Using this polymer stamp, SU-8 is imprinted aligned to vertical TSVs over Si surface.Waveguide dicing is presented as a second technology to create coupling elements on polymer waveguides. The reflecting mirror is created by 45° V-shaped dicing blade. The goal of this work is to develop coupling elements to aid 3D optical interconnect network on silicon interposer, to facilitate the realization of the emerging technologies for the upcoming years.