The last few decades have been a very exciting period in thedevelopment of micro-electronics and brought us to the brink ofimplementing entire systems on a single chip, on a hithertounimagined scale. However an unforeseen challenge has croppedup in the form of managing wires, which have become the mainbottleneck in performance, masking the blinding speed of activedevices. A major problem is that increasingly complicatedeffects need to be modelled, but the computational complexityof any proposed model needs to be low enough to allow manyiterations in a design cycle. This thesis addresses the issue of closed form modelling ofthe response of coupled interconnect systems. Following astrict mathematical approach, second order models for thetransfer functions of coupled RC trees based on the first andsecond moments of the impulse response are developed. The2-pole-1-zero transfer function that is the best possible fromthe available information is obtained for the signal path fromeach driver to the output in multiple aggressor systems. Thisallows the complete response to be estimated accurately bysumming up the individual waveforms. The model represents theminimum complexity for a 2-pole-1-zero estimate, for this classof circuits. Also proposed are new techniques for the optimisation ofwires in on-chip buses. Rather than minimising the delay overeach individual wire, the configuration that maximises thetotal bandwidth over a number of parallel wires isinvestigated. It is shown from simulations that there is aunique optimal solution which does not necessarily translate tothe maximum possible number of wires, and in fact deviatesconsiderably from it when the resources available for repeatersare limited. Analytic guidelines dependent only on processparameters are derived for optimal sizing of wires andrepeaters. Finally regular tiled architectures with a commoncommunication backplane are being proposed as being the mostefficient way to implement systems-on-chip in the deepsubmicron regime. This thesis also considers the feasibility ofimplementing a regular packet-switched network-on-chip in atypical future deep submicron technology. All major physicalissues and challenges are discussed for two differentarchitectures and important limitations are identified.

The aim of the research work presented here, is to contribute to the adaptation of electronic packaging towards the needs of high frequency applications. As the field of electronic packaging stretches over several very different professional areas, it takes an interdisciplinary approach to optimize the technology of electronic packaging. Besides this, an extensive knowledge of industrial engineering should be an essential part of this undertaking to improve electronic packaging. Customary advances in technology are driven by new findings and a continuous development of processes in clearly defined fields. However, in the field of the higher levels of the interconnection hierarchy, that is external to the chip level interconnections and chip packaging, it is supposed that a wide combination of disciplines and technical creativity, instead of advanced technology in a special area should produce most added value. The thesis is divided into five areas, interlinked by the overall aim of there advantages to the common goal. These areas are the Printed Wiring Board (PWB) technology, PWB connections using flexible printed circuit boards, multiconductor cable connections, shielded enclosures and the related EMC issues, and finally the cooling of electronics. A central issue was to improve the shielded enclosures to be effective also at very high frequencies; it will be shown that shielded enclosures without apertures can cope with frequencies up to and above 15 GHz. Due to this enclosure without apertures, it was necessary to develop a novel cooling structure. This cooling structure consists of a heat sink where the PCB’s are inserted in close contact to the cooling fins on one side, whereas the other side of the heat sink is cooled by forced ventilation. The heat transfer between these parts is completely inside the same body. Tests carried out on a prototype have shown that the performance of the cooling structure is satisfactory for electronic cooling. Another problem area that is addressed are the interconnect problems in high frequency applications. Interconnections between parts of a local electronic system, or as within the telecom and datacom field between subscribers, are commonly accomplished by cable connections. In this research work multiconductor cables are examined and a patented novel cable-connector for high frequency use is presented. Further, an experimental complex soldering method between flexible printed circuits boards and rigid printed circuits boards, as part of connections between PCBs, is shown. Finally, different sectors of the PCB technology for high frequency applications are scrutinized and measurements on microstrip structures are presented. / QC 20101006

The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.

Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared medium wired interconnects offering many practical applications in industry. Dynamic Voltage Frequency Scaling (DVFS) is a technique whereby a chip?s voltage-frequency levels are varied at run time, often used to conserve dynamic power. Various DVFSbased NoC optimization techniques have been proposed. However, due to the resources required to validate architectural decisions through prototyping, few are implemented. As a result, designers are faced with a lack of insight into potential power savings or performance gains at early architecture stages. This thesis proposes a DVFS aware NoC simulator with support for per node power-frequency modeling to allow fine-tuning of such optimization techniques early on in the design cycle. The proposed simulator also provides a framework for benchmarking various candidate strategies to allow selective prototyping and optimization. As part of the research, DVFS extensions were built for an existing NoC performance simulator and released for public use. This thesis presents some of the preliminary results from our simulator that show the average power consumed per node for all the benchmarks in SPLASH 2 benchmark suite [74] to be quite similar to each other. This thesis also serves as a technical manual for the simulator extensions. Important links for downloading and using the simulator are provided at the end of this document in Appendix C.

<p>The last few decades have been a very exciting period in thedevelopment of micro-electronics and brought us to the brink ofimplementing entire systems on a single chip, on a hithertounimagined scale. However an unforeseen challenge has croppedup in the form of managing wires, which have become the mainbottleneck in performance, masking the blinding speed of activedevices. A major problem is that increasingly complicatedeffects need to be modelled, but the computational complexityof any proposed model needs to be low enough to allow manyiterations in a design cycle.</p><p>This thesis addresses the issue of closed form modelling ofthe response of coupled interconnect systems. Following astrict mathematical approach, second order models for thetransfer functions of coupled RC trees based on the first andsecond moments of the impulse response are developed. The2-pole-1-zero transfer function that is the best possible fromthe available information is obtained for the signal path fromeach driver to the output in multiple aggressor systems. Thisallows the complete response to be estimated accurately bysumming up the individual waveforms. The model represents theminimum complexity for a 2-pole-1-zero estimate, for this classof circuits.</p><p>Also proposed are new techniques for the optimisation ofwires in on-chip buses. Rather than minimising the delay overeach individual wire, the configuration that maximises thetotal bandwidth over a number of parallel wires isinvestigated. It is shown from simulations that there is aunique optimal solution which does not necessarily translate tothe maximum possible number of wires, and in fact deviatesconsiderably from it when the resources available for repeatersare limited. Analytic guidelines dependent only on processparameters are derived for optimal sizing of wires andrepeaters.</p><p>Finally regular tiled architectures with a commoncommunication backplane are being proposed as being the mostefficient way to implement systems-on-chip in the deepsubmicron regime. This thesis also considers the feasibility ofimplementing a regular packet-switched network-on-chip in atypical future deep submicron technology. All major physicalissues and challenges are discussed for two differentarchitectures and important limitations are identified.</p>

The continuous scaling of interconnect wires in deep submicron (DSM)circuits result in increased interconnect delay, power and crosstalk noise. In this dissertation, we address the problem of multi-metric optimization at post layout level in the design of deep submicron designs and develop a game theoretic framework for its solution. Traditional approaches in the literature can only perform single metric optimization and cannot handle multiple metrics. However, in interconnect optimization, the simultaneous optimization of multiple parameters such as delay, crosstalk noise and power is necessary and critical. Thus, the work described in this dissertation research addressing multi-metric optimization is an important contribution.Specifically, we address the problems of simultaneous optimization of interconnect delay and crosstalk noise during (i) wire sizing (ii) gate sizing (iii) integrated gate and wire sizing, and (iv) gate sizing considering process variations. Game the ory provides a natural framework for handling conflicting situations and allows optimization of multiple parameters. This property is exploited in modeling the simultaneous optimization of various design parameters such as interconnect delay, crosstalk noise and power, which are conflicting in nature. The problem of multi-metric optimization is formulated as a normal form game model and solved using Nash equilibrium theory. In wire sizing formulations, the net segments within a channel are modeled as the players and the range of possible wire sizes forms the set of strategies. The payoff function is modeled as (i) the geometric mean of interconnect delay andcrosstalk noise and (ii) the weighted-sum of interconnect delay, power and crosstalk noise, in order to study the impact of different costfunctions with two and three metrics respectively. In gate sizing formulations, the range of possible gate sizes is modeled as the set of strategies and the payoff function is modeled as the geome tric mean of interconnect delay and crosstalk noise. The gates are modeled as the players while performing gate sizing, whereas, the interconnect delay and crosstalk noise are modeled as players for integrated wire and gate sizing framework as well as for statistical gate sizing under the impact of process variations.The various algorithms proposed in this dissertation (i) perform multi-metric optimization (ii) achieve significantly better optimization and run times than other methods such as simulated annealing, genetic search, and Lagrangian relaxation (iii) have linear time and space complexities, and hence can be applied to very large SOC designs, and (iv) do not require rerouting or incur any area overhead. Thecomputational complexity analysis of the proposed algorithms as well as their software implementations are described, and experimental results are provided that establish the efficacy of the proposed algorithms.

The 2006 International Technology Roadmap for Semiconductors projects that for 2020, interconnects will be as narrow as 14 nm and will operate at frequencies as high as 50GHz. For a wire that operates at ultra-high frequencies, such that skin depth and the mean free path of the electrons are in the same order, skin effect and surface scattering should be considered simultaneously. This is known as the anomalous skin effect (ASE). The objective of this work is to identify the challenges and opportunities for using GSI interconnects in the nanometer and GHz regime. The increase in the resistivity of a thin wire caused by the ASE is studied. The delay of a digital transmission line resulting from this effect is modeled. Compact models are presented for the bit-rate limit of transmission lines using a general form of resistance that for the first time simultaneously considers dc resistance, skin effect, and surface scattering. A conventional low-loss approximation that is only valid for fast rising signals is also relaxed. The impact of size effects on the design of multi-level interconnect networks is studied. For high-performance chips at the 18 nm technology node, it is shown that despite a more than four times increase in the resistivity of copper for minimum-size interconnects, the increase in the number of metal levels is negligible (less than 7%), and interconnects that will be affected most are so short that their impact on chip performance is inconsequential. It is shown that for low-cost applications where very few wiring pitches are normally used, the number of metal levels needed to compensate for the impact of size effects on the average rc delay of a copper interconnect is drastically high. An optimization methodology has been presented for power distribution interconnects at the local level. For a given IR drop budget, compact models are presented for the optimal widths of power and ground lines in the first two metal levels for which the total metal area used for power distribution is minimized.

Made available in DSpace on 2014-12-17T14:06:53Z (GMT). No. of bitstreams: 1 ClawsioRCS_DISSERT.pdf: 4688648 bytes, checksum: dd0d723d2cc3d7de35608b8ed730a95b (MD5) Previous issue date: 2010-03-29 / Conselho Nacional de Desenvolvimento Cient?fico e Tecnol?gico / The cells unitaria of the solid oxide fuel cell are separated by means of interconnects, which serve as electrical contact between the cells. Lanthanum Chromite (LaCrO3) has been the most common material used as interconnect in solid oxide fuel cells. Reducing the operating temperature around 800 ? C of cells to solid oxide fuel make possibilite the use of metallic interconnects as an alternative to ceramic LaCrO3. Metallic interconnects have advantages over ceramic interconnects such as high thermal conductivity, electricity, good ductility, low cost, good physical and mechanical properties. In this work evaluate the thermo-mechanical properties of the metallic substrate and coated metallic substrate with the ceramic LaCrO3 film via spray-pyrolysis, in order to demonstrate the feasibility of using this material as a component of a fuel cell solid oxide. The materials were characterized by X-ray diffraction, oxidation behavior, mechanical strength, optical microscopy (OM) and scanning electron microscopy (SEM). The X-ray diffraction proved the formation phase of the LaCrO3 on the metallic substrate and the identification of the phases formed after the oxidative test and mechanical strength at high temperature. The oxidation behavior showed the increased oxidation resistance of the coated metallic substrate. It was noted that the mechanical resistance to bending of the coated metallic substrate only increases at room temperature. The optical microscopy (OM) has provided an assessment of both the metallic substrate and the LaCrO3 film deposited on the metal substrate that, in comparison with the micrographs obtained from SEM. The SEM one proved the formation of Cr2O3 layer on the metallic substrate and stability of LaCrO3 film after oxidative test, it can also observe the displacement of the ceramic LaCrO3 film after of mechanical testing and mapping of the main elements as chromium, manganese, oxygen, lanthanum in samples after the thermo-mechanical tests. / As pilhas unit?rias de uma pilha a combust?vel de ?xido s?lido s?o separadas por meio de interconectores, que servem como contato el?trico entre as pilhas. A cromita de lant?nio (LaCrO3) tem sido o material mais utilizado como interconector nas pilhas a combust?vel de ?xido s?lido. A redu??o da temperatura de opera??o em torno de 800 ?C das pilhas a combust?vel de ?xido s?lido, tornou poss?vel o uso de interconectores met?licos como alternativa aos LaCrO3 cer?micos. Esses materiais apresentam vantagens em rela??o aos interconectores cer?micos tais como: alta condutividade t?rmica, el?trica, boa ductilidade, baixo custo, boas propriedades f?sicas e mec?nicas. Neste trabalho foram avaliadas as propriedades termomec?nicas do substrato met?lico e substrato met?lico recoberto com o filme de LaCrO3 via spray-pir?lise, com o objetivo de demonstrar a viabilidade da utiliza??o deste materiais como componente de uma pilha a combust?vel de ?xido s?lido. Os materiais foram caracterizados por meio de difra??o de raios-X, comportamento oxidativo, resist?ncia mec?nica, microscopia ?ptica e microscopia eletr?nica de varredura (MEV). A difra??o de raios-X comprovou a forma??o da fase LaCrO3 sobre o substrato met?lico e a identifica??o das fases formadas ap?s o ensaio oxidativo e resist?ncia mec?nica a alta temperatura.O comportamento oxidativo evidenciou o aumento da resist?ncia a oxida??o do substrato met?lico recoberto. Na resist?ncia mec?nica a flex?o do substrato met?lico recoberto, notou-se o aumento apenas na temperatura ambiente. A microscopia ?ptica (MO) fez uma avalia??o pr?via tanto do substrato met?lico e do filme de LaCrO3 recoberto sobre o substrato met?lico,que em compara??o com as micrografias obtidas por MEV. Com aux?lio do MEV comprovou a forma??o da camada de Cr2O3 sobre o substrato met?lico e a estabilidade do filme de LaCrO3 ap?s o ensaio oxidativo. Observando tamb?m o descolamento do filme de LaCrO3 ap?s ensaio mec?nico e a distribui??o dos principais elementos como: cromo, mangan?s, oxig?nio, lant?nio nas amostras que foram submetidas aos ensaios termo-mec?nicos

Dans les systèmes d’Electrolyse Haute Température (EHT), le matériau choisi comme interconnecteur doit avoir une bonne résistance à la corrosion sous air et sous mélange H2/H2O à 800 °C, et maintenir une bonne conductivité sur de longues durées. Dans ce cadre, l’objectif de ce travail était, d’une part, d’évaluer un alliage ferritique commercial (l’alliage K41X) comme matériau d’interconnecteur pour l’application EHT. Dans ce but, ont été mis en place des essais d’oxydation en four et en thermoblance pour accéder aux cinétiques d’oxydation, et des mesures de résistivité pour évaluer le paramètre ASR (Area Specific Resistance) à 800°C. D’autre part, l’étude a permis d’apporter des éléments de compréhension plus fondamentaux sur les mécanismes d’oxydation des alliages chromino-formeurs, en particulier sous mélange H2-H2O, par le biais d’essais et de caractérisations spécifiques (Photoélectrochimie, traçage isotopique, essais de longues durées). Cette double stratégie est également appliquée pour l’étude d’une solution de revêtement (obtenu à l’aide de la MOCVD) basée sur l’oxyde pérovskite LaCrO3 qui présente des propriétés de conductivité élevée particulièrement intéressante en vue de l’application EHT. Ainsi, cette étude amène également des éléments de compréhension sur le rôle du lanthane comme élément réactif dont l’effet est souvent discuté dans la littérature. Pour les deux milieux, à 800°C, la couche d’oxyde formée est une couche duplexe Cr2O3/(Mn,Cr)3O4 , recouverte dans le cas du mélange H2-H2O par une fine couche d’oxyde spinelle Mn2TiO4 . Sous air, le mécanisme de croissance déterminé ici est cationique, en accord avec la littérature. La présence d’un revêtement LaCrO3 ne modifie pas ce mécanisme mais ralentit la cinétique de croissance de la couche sur les premières centaines d’heure. De plus, le revêtement améliore l’adhérence et la conductivité de la couche d’oxyde. Sous mélange H2-H2O, le mécanisme de croissance se révèle anionique. La présence de revêtement ralentit la cinétique d’oxydation. Bien que .d’épaisseurs similaires, les couches d’oxyde présentent sous air une résistivité d’un ordre de grandeur inférieure à celle mesurée sous H2-H2O. Il est mis en évidence que la forte résistivité de l’alliage en milieu H2-H2O est liée à la présence de protons issus de la vapeur d’eau présents dans la couche d’oxyde. Le revêtement ne permet néanmoins pas d améliorer la conductivité sous H2-H2O. / In High Temperature Vapor Electrolysis (HTVE) system, the materials chosen for the interconnectors should have a good corrosion behaviour in air and in H2-H2O mixtures at 800°C, and keep a high electronic conductivity over long durations as well. In this context, the first goal of this study was to evaluate a commercial ferritic alloy (the K41X alloy) as interconnect for HTVE application. Oxidation tests in furnace and in microbalance have therefore been carried out in order to determine oxidation kinetics. Meanwhile, the Area Specific Resistance (ASR) was evaluated by Contact Resistance measurements performed at 800°C. The second objective was to improve our comprehension of chromia-forming alloys oxidation mechanism, in particular in H2/H2O mixtures. For that purpose, some specific tests have been conducted: tracer experiments, coupled with the characterization of the oxide scale by PEC (PhotoElectroChemistry). This approach has also been applied to the study of a LaCrO3 perovskite oxide coating on the K41X alloy. This phase is indeed of high interest for HTVE applications due to its high conductivity properties. This latter study leads to further understanding on the role of lanthanum as reactive element, which effect is still under discussion in literature.In both media at 800°C, the scale is composed of a Cr2O3/(Mn,Cr)3O4 duplex scale, covered in the case of H2-H2O mixture by a thin scale made of Mn2TiO4 spinel. In air, the growth mechanism is found to be cationic, in agreement with literature. The LaCrO3 coating does not modify the direction of scale growth but lowers the growth kinetics during the first hundreds hours. Moreover, with the coating, the scale adherence is favored and the conductivity appears to be slightly higher. In the H2-H2O mixture, the growth mechanism is found to be anionic. The LaCrO3 coating diminishes the oxidation kinetics. Although the scale thickness is about the same in both media, the ASR parameter is one order of magnitude higher in H2/H2O than in air. Specific contact resistance tests show that the higher resistivity in the H2/H2O mixture is closely linked to the presence of protons in the scale. Moreover, tracer experiments show that these protons come from the water molecule dissociation, and not from the H2 molecule. In H2/H2O, the LaCrO3 coating does not increase the conductivity

Due to their inherent BW capacity, optical interconnect (OI) offers a means of replacement to BW limited copper as bottlenecks begin to appear within the various interconnect levels of electronics systems. Low-cost optically enabled printed circuit boards are a key milestone on many electronics roadmaps, e.g. iNEMI. Current OI solutions found in industry are based upon optical fibres and are capable of providing a suitable platform for inter-board applications especially on the backplane. However, to allow component assembly onto high BW interconnects, an integral requirement for intra-board applications, optically enabled printed circuit boards containing waveguides are essential. Major barriers to the deployment of optical printed circuit boards include the compatibility of the technique, the cost of acquiring OI and the optical power budget. The purpose of this PhD research programme is to explore suitable techniques to address these barriers, primarily by means of laser material processing using UV and IR source lasers namely 248 nm KrF Excimer, 355 nm UV Nd:YAG and 10.6 μm IR CO2. The use of these three main lasers, the trio of which dominates most PCB production assembly, provides underpinning drive for the deployment of this technology into the industry at a very low cost without the need for any additional system or system modification. It further provides trade-offs among the suitable candidates in terms of processing speed, cost and quality of waveguides that could be achieved. This thesis presents the context of the research and the underlying governing science, i.e. theoretical analysis, involving laser-matter interactions. Experimental investigation of thermal (or pyrolitic) and bond-breaking (or photolytic) nature of laser ablation was studied in relation to each of the chosen lasers with regression analysis used to explain the experimental results. Optimal parameters necessary for achieving minimum Heat Affected Zone (HAZ) and surface/wall roughness were explored, both of which are key to achieving low loss waveguides. While photochemical dominance - a function of wavelength and pulse duration - is desired in laser ablation of photopolymers, the author has been able to find out that photothermallyprocessed materials, for example at 10.6 μm, can also provide desirable waveguides. Although there are literature information detailing the effect of certain parameters such as fluence, pulse repetition rate, pulse duration and wavelength among others, in relation to the etch rate of different materials, the machining of new materials requires new data to be obtained. In fact various models are available to try to explain the laser-matter interaction in a mathematical way, but these cannot be taken universally as they are deficient to general applications. For this reason, experimental optimisation appears to be the logical way forward at this stage of the research and thus requiring material-system characterisation to be conducted for each case thereby forming an integral achievement of this research. In this work, laser ablation of a single-layer optical polymer (Truemode™) multimode waveguides were successfully demonstrated using the aforementioned chosen lasers, thus providing opportunities for rapid deployment of OI to the PCB manufacturing industry. Truemode™ was chosen as it provides a very low absorption loss value < 0.04 dB/cm at 850 nm datacom wavelength used for VSR interconnections - a key to optical power budget - and its compatibility with current PCB fabrication processes. A wet-Truemode™ formulation was used which required that optical polymer layer on an FR4 substrate be formed using spin coating and then UV-cured in a nitrogen oxygen-free chamber. Layer thickness, chiefly influenced by spinning speed and duration, was studied in order to meet the optical layer thickness requirement for multimode (typically > 9 μm) waveguides. Two alternative polymers, namely polysiloxane-based photopolymer (OE4140 and OE 4141) from Dow Corning and PMMA, were sparingly utilized at some point in the research, mainly during laser machining using UV Nd:YAG and CO2 lasers. While Excimer laser was widely considered for polymer waveguide due to its high quality potential, the successful fabrication at 10.6 μm IR and 355 nm UV wavelengths and at relatively low propagation loss at datacom wavelength of 850 nm (estimated to be < 1.5 dB/cm) were unprecedented. The author considered further reduction in the optical loss by looking at the effect of fluence, power, pulse repetition rate, speed and optical density on the achievable propagation but found no direct relationship between these parameters; it is therefore concluded that process optimisation is the best practice. In addition, a novel in-plane 45-degree coupling mirror fabrication using Excimer laser ablation was demonstrated for the first time, which was considered to be vital for communication between chips (or other suitable components) at board-level.