abstract: In 2022, integrated circuit interconnects will approach 10 nm and the diffusion barrier layers needed to ensure long lasting devices will be at 1 nm. This dimension means the interconnect will be dominated by the interface and it has been shown the interface is currently eroding device performance. The standard interconnect system has three layers - a Copper metal core, a Tantalum Adhesion layer and a Tantalum Nitride Diffusion Barrier Layer. An alternate interconnect schema is a Tantalum Nitride barrier layer and Silver as a metal. The adhesion layer is removed from the system along with changing to an alternate, low resistivity metal. First principles are used to assess the interface of the Silver and Tantalum Nitride. Several stoichiometric 1:1 Tantalum Nitride polymorphs are assessed and it is found that the Fe2P crystal structure is actually the most stable crystal structure which is at odds with the published phase diagram for ambient crystal structure. The surface stability of Fe2P-TaN is assessed and the absorption enthalpy of Silver adatoms is calculated. Finally, the thermodynamic stability of the TaN-Ag interconnect system is assessed. / Dissertation/Thesis / Ph.D. Materials Science and Engineering 2012

L'electromigration est identifiée comme la principale cause de dégradation des interconnexions en cuivre limitant ainsi la fiabilité des produits issus de la microélectronique. Dans ces travaux nous proposons d'approfondir notre connaissance de ce phénomène en étudiant le lien qu'il présente avec les paramètres morphologiques du cuivre. Dans ce but, la technique de diffraction des électrons rétrodiffusés est utilisée. Nous avons d'abord développé les méthodes de préparation et d'acquisition nécessaires afin de pouvoir caractériser les structures issues des technologies 45 nm et au-delà que nous avons choisies pour cette étude. Un lien entre les joints de grains de forte désorientation et la localisation des cavités a alors pu être mis en évidence. Nous avons ensuite tenté de modifier la microstructure du cuivre pour impacter la fiabilité sans succès. Finalement, c'est l'intégration de nouveaux matériaux (Al, Co) renforçant l'interface supérieure, chemin de diffusion du phénomène, qui semble être la voie à adopter pour améliorer la résistance des lignes à l'électromigration. / Electromigration is one of the major cause of copper interconnect degradation which limits reliability of microelectronic products. In these works, link between copper morphological parameters and electromigration is studied to get more knowledge of this phenomenon. For that, copper structures from 45 nm technology node and beyond are characterized by backscattered electron diffraction technique. In a first time, developments of sample preparation and acquisition methodology are performed to be able to characterize small dimensions structures from technology node chosen. A link between high angle grain boundary and void location has been highlighted. Then we tried to improve reliability by copper microstructure change without success. It seems that right way to improve interconnect resistance toward electromigration is the introduction of new materials in copper (Al, Co) to reinforce upper interface which is critical diffusion path of electromigration phenomenon.

Nous assistons aujourd'hui à une explosion des demandes de calcul, de stockage et de transfert de données. Dans ce contexte, le développement des ordinateurs à haute performance est crucial mais il est limité par le débit et la consommation des interconnexions électriques entre puces ou intra-puces. La photonique sur silicium propose de lever ce verrou technologique en utilisant la maturité des procédés de fabrication de microélectronique pour concevoir des interconnexions optiques à très haut débit et à faible énergie par bit. Dans ces travaux, nous nous proposons de dimensionner un lien optique intégré sur silicium pour par exemple adresser le défi technologique des interconnexions intra-puces entre un processeur et une mémoire DRAM de dernière génération. Le lien optique conçu est multiplexé en longueur d’onde et utilise des composants intégrés à faible empreinte appelés anneaux résonants pour les fonctions de modulation et de démultiplexage. Les sources laser dont seront munis ces interconnexions consomment une puissance importante : nous nous attachons à optimiser la performance des composants utilisés en termes de puissance optique. A partir d’une analyse système, nous proposons une architecture de lien et construisons un modèle pour évaluer les pénalités en puissance optique associées au transmetteur et au récepteur du lien de communication à l’aide de simulations statiques et dynamiques. Ce modèle comprend des contributions des modulateurs et des filtres du démultiplexeur considérés individuellement ainsi que des contributions liées au multiplexage en longueur d’onde à l’émission et à la réception. Des modulateurs optiques en anneau sont fabriqués en technologie PIC25G, caractérisés en statique et en dynamique puis comparés au modèle. Enfin, des démonstrateurs multiplexés en longueur d’onde sont conçus et mis en œuvre permettant de valider nos modèles prédictifs et d'en soulever de futurs perfectionnements. / The 21st century is characterized by the explosion of demand for computing power as well as data storage and transfer. In this context, the development of high-performance computers is crucial but it is limited by the bandwidth and the energy efficiency of chip-to-chip and intra-chip electrical interconnects. Silicon photonics is a promising solution that uses microelectronics manufacturing techniques to fabricate optical components dedicated to efficient and high-bit-rate optical communication links.This work aims at designing a silicon photonic intra-chip high-bandwidth interconnect based on the example of latest-generation DRAM specifications. Wavelength division multiplexing (WDM) is used with low-footprint components called optical ring resonators for modulation and filtering.Lasers sources are a non-negligible contributor to overall system power consumption. For this reason, this thesis focuses on the optimization of ring resonators in terms of optical power. We first carry out a system analysis and propose an architecture that consists of parallel WDM links. Then a system model that evaluates optical power penalties related to the transmitter and the receiver is built up using static and dynamic simulations. Individual contributions of modulators, filters as well as the impact of adjacent channels at the transmitter and receiver sides are taken into account. Optical ring modulators are fabricated in PIC25G technology and characterized through static and dynamic measurements in order to validate our model. Finally, wavelength division multiplexed prototypes are designed and demonstrations corresponding to different WDM configurations are carried out which allows for suggestions of future improvements from the comparison with our predictive model.

A Chip Multiprocessor for a Large-scale Neural SimulatorEustace PainkrasA thesis submitted to The University of Manchesterfor the degree of Doctor of Philosophy, 17 December 2012The modelling and simulation of large-scale spiking neural networks in biologicalreal-time places very high demands on computational processing capabilities andcommunications infrastructure. These demands are difficult to satisfy even with powerfulgeneral-purpose high-performance computers. Taking advantage of the remarkableprogress in semiconductor technologies it is now possible to design and buildan application-driven platform to support large-scale spiking neural network simulations.This research investigates the design and implementation of a power-efficientchip multiprocessor (CMP) which constitutes the basic building block of a spikingneural network modelling and simulation platform. The neural modelling requirementsof many processing elements, high-fanout communications and local memoryare addressed in the design and implementation of the low-level modules in the designhierarchy as well as in the CMP. By focusing on a power-efficient design, the energyconsumption and related cost of SpiNNaker, the massively-parallel computation engine,are kept low compared with other state-of-the-art hardware neural simulators.The SpiNNaker CMP is composed of many simple power-efficient processors withsmall local memories, asynchronous networks-on-chip and numerous bespoke modulesspecifically designed to serve the demands of neural computation with a globallyasynchronous, locally synchronous (GALS) architecture.The SpiNNaker CMP, realised as part of this research, fulfills the demands of neuralsimulation in a power-efficient and scalable manner, with added fault-tolerancefeatures. The CMPs have, to date, been incorporated into three versions of SpiNNakersystem PCBs with up to 48 chips onboard. All chips on the PCBs are performing successfully, during both functional testing and their targeted role of neural simulation.

abstract: Miniaturization of microdevices comes at the cost of increased circuit complexity and operating current densities. At high current densities, the resulting electron wind imparts a large momentum to metal ions triggering electromigration which leads to degradation of interconnects and solder, ultimately resulting in circuit failure. Although electromigration-induced defects in electronic materials can manifest in several forms, the formation of voids is a common occurrence. This research aims at understanding the morphological evolution of voids under electromigration by formulating a diffuse interface approach that accounts for anisotropic mobility in the metallic interconnect. Based on an extensive parametric study, this study reports the conditions under which pancaking of voids or the novel void ‘swimming’ regimes are observed. Finally, inferences are drawn to formulate strategies using which the reliability of interconnects can be improved. / Dissertation/Thesis / Masters Thesis Materials Science and Engineering 2020

This dissertation focuses on developing 3D printing as a fabrication method for microfluidic devices. Specifically, I concentrate on the 3D printing approach known as Digital Light Processing stereolithography (DLP-SLA) in which serially projected images are used to sequentially photopolymerize layers to build a microfluidic device. The motivation for this work is to explore a much faster alternative to cleanroom-based microfabrication that additionally offers the opportunity to densely integrate microfluidic elements in compact 3D layouts for dramatic device volume reduction. In the course of my research, an optical approach was used to guide custom resin formulation to help create the interconnected hollow regions that form a microfluidic device. This was based on a new a mathematical model to calculate the optical dose delivered throughout a 3D printed part, which also explains the effect of voids. The model was verified by a series of 3D printed chips fabricated with a commercial 3D printer and a custom resin. Channels as small as 108 µm x 60 µm were repeatably fabricated. Next, highly compact active fluidic components, including valves, pumps, and multiplexers, were fabricated with the same 3D printer and resin. The valves achieved a 10x size reduction compared with previous results, and were the smallest 3D printed valves at the time. Moreover, by adding thermal initiator to thermally cure devices after 3D printing, the durability of 3D printed valves was improved and up to 1 million actuations were demonstrated.To further decrease the 3D printed feature size, I built a custom 3D printer with a 385 nm LED light source and a 7.56 µm pixel pitch in the plane of the projected image. A custom resin was also developed to take advantage of the new 3D printer's features, which necessitated developing a UV absorber screening process which I applied to 20 candidate absorbers. In addition, a new mathematical model was developed to use only the absorber's molar absorptivity measurement to predict the resin optical penetration depth, which is important for determining the z-resolution that can be achieved with a given resin. The final resin formulation uses 2-nitrophenyl phenyl sulfide (NPS) as the UV absorber. With this resin, along with a new channel narrowing technique, I successfully created flow channel cross sections as small as 18 µm x 20 µm.With the custom 3D printer, smaller valves and pumps become possible, which led to the invention of a new method of creating large numbers of high density chip-to-chip microfluidic interconnects based on either simple integrated microgaskets (SIMs) or controlled-compression integrated microgaskets (CCIMs). Since these structures are directly 3D printed as part of a device, they require no additional materials or fabrication steps. As a demonstration of the efficacy of this approach, 121 chip-to-chip interconnects in an 11 x 11 array for both SIMs and CCIMs with an areal density of 53 interconnects per square mm were demonstrated, and tested up to 50 psi without leaking. Finally, these interconnects were used in the development of 3D printed chips with valves having 30x smaller volume than the valves we previously demonstrated. These valves served as a building block for demonstrating the miniaturization potential of an active fluid mixer using our 3D printing tools, materials, and methods. The mixer provided a set of selectable mixing ratios, and was designed in 2 configurations, a linear dilution mixer-pump (LDMP) and a parallelized dilution mixer-pump (PDMP), which occupy volumes of only 1.5 cubic mm and 2.6 cubic mm, respectively.

Améliorer uniquement les performances et l'efficacité énergétique des transistors n'est pas suffisant pour les futurs systèmes sur puce. Les interconnexions sont également essentielles et ont de graves répercussions sur les performances globales du circuit et l'efficacité énergétique. Le cuivre (Cu) est le matériau d'interconnexion conventionnel qui a aujourd’hui atteint ses limites par suite de l’effet de la miniaturisation. Les effets de barrière et de dispersion induisent une résistivité élevée et une forte éléctromigration aggravent la fiabilité d'interconnexion. Les Nanotubes de carbone (CNT) et les composites de Cuivre et Nanotube de carbone (Cu-CNT) sont intéressants grâce à leur transport balistique, à la grande évolutivité, à la conductivité thermique élevée et à la densité de courant élevée. Dans ce travail, nous étudions les propriétés physiques fondamentales et électriques des CNT et des composite de Cu-CNT de l’échelle atomique à l’échelle macroscopique pour les applications d’interconnexions locales et globales. Nous évaluons les différentes sources de variabilité et leurs impacts sur les performances d'interconnexion des CNT et l'efficacité énergétique. Le dopage basé sur le transfert de charge des CNT est également étudié en tant que moyen important de réduire davantage sa résistivité et d’atténuer les variations de chiralité des CNT ainsi que d’alléger les effets sur la résistance de contact. Les résultats des mesures expérimentales sont utilisés pour démontrer la validité et la précision de nos modèles établis. Les modèles d'interconnexion sont enfin appliqués aux études à l’échelle de portes et de circuits en tant qu'interconnexions locales et globales pour évaluer leurs performances. / Improving only the performance and energy efficiency of transistors is not sufficient for future systems-on-chip. On-chip interconnects have become equally critical to transistors and can detriment the system’s performance and energy efficiency. Copper (Cu) is the state-of-the-art interconnect material and is reaching its physical limitations due to scaling. Barrier and scattering effects induce high resistivity and electromigration exacerbates interconnect reliability. Carbon Nanotubes (CNTs) and Copper-Carbon Nanotube (Cu-CNT) composite materials are of interest due to ballistic transport, high scalability, high thermal conductivity, and high current density. We investigate from fundamental atomistic level to macroscopic level the physical understanding and electrical compact modeling on CNT and Cu-CNT composite for on-chip local and global interconnect applications. We evaluate and assess the different sources of variations and their impacts on CNT interconnect performance and energy efficiency. Charge transfer based doping of CNT is also investigated as an alternative method to further reduce its resistivity, mitigate CNT chirality variations and contact resistance drawbacks. Experimental measurement results are used to demonstrate the validity and accuracy of our established models. The interconnect models are finally applied to the gate- and circuit- level studies as local and global interconnects to evaluate their performance.

CMOS is well known for its ability to scale. This fact is reflected in the aggressive scaling on a continual basis from the invention of CMOS up to date. As devices are scaled, device performance improves due to shorter channel lengths and more densely packed functions for the same amount of area. In recent years, however, the performance gain obtained through scaling has begun to suffer under the degradation of the associate interconnect performance. As devices become smaller, interconnects need to follow. Unlike transistors, the scaling of interconnects results in higher capacitances and resistances, thereby limiting overall system performance. Trying to alleviate the delay effects results in increased power consumption, especially in global structures such as clock distribution networks. A possible solution to this problem is the use of optical interconnects, which are fast and much less lossy than the electrical equivalents. This dissertation describes an investigation on what future technology nodes will entail in terms of power consumption of clock networks, and what is required for an optical alternative to become feasible. A common clock configuration is used as a basis for comparison, where both electrical and optical networks are designed to component level. Optimisation is done on both to ensure a reasonable comparison, and the results of the respective power consumption components are then compared in order to find the criteria for a feasible optical clock distribution scheme. Copyright / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted

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In this paper, a study of tungsten metallization in advanced BEOL interconnects is presented. A mature 10 nm process is used for comparison between the tungsten and conventional copper metallization. Wafers were processed together till M1 dual-damascene etch then separated for different metallization. Tungsten metal line of 24 nm width is showing a 1.6X wire resistance comparing to the copper metal line. Comparable opens/shorts yield were obtained on a 0.8 M comb serpentine, Kelvin-via and 4K via chains. Similar physical profile were also achieved. This study has demonstrated the feasibility of replacing the copper by tungsten at BEOL using the conventional tungsten metallization tools and processes. This could be a cost- effective solution for the low-power products.