ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS August 2007 BASAB DATTA B.S., G.G.S. INDRAPRASTHA UNIVERSITY, NEW DELHI M.S.E.C.E, UNIVERSITY OF MASSACHUSETTS AMHERST Directed by: Professor Wayne P. Burleson Aggressive technology scaling and an increasing demand for high performance VLSI circuits has resulted in higher current densities in the interconnect lines and increasingly higher power dissipation in the substrate. Because a significant fraction of this power is converted to heat, an exponential rise in heat density is also experienced. Different activities and sleep modes of the functional blocks in high performance chips cause significant temperature gradients in the substrate and this can be expected to further increase in the GHz frequency regime. The above scenario motivates the need for a large number of lightweight, robust and power-efficient thermal sensors for accurate thermal mapping and thermal management. We propose the use of Differential Ring Oscillators (DRO) for thermal sensing at the substrate level, utilizing the temperature dependence of the oscillation frequency. They are widely used in current VLSI for frequency synthesis and on-die process characterization; hence provide scope of reusability in design. The DRO oscillation frequency decreases linearly with increase in temperature due to the decrease in current in the signal paths. In current starved inverter topology using the 45nm technology node, the DRO based thermal sensor has a resolution of 2°C and a low active power consumption of 25µW, which can be reduced further by 60-80% by power-gating the design. Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density as we move from substrate to higher metal levels. Thus, the deterioration of interconnect performance at extreme temperatures has the capability to offset the degradation in device performance when operating at higher than normal temperatures. We propose using lower-level metal interconnects to perform the thermal sensing. A resolution of ~5°C is achievable for both horizontal and vertical gradient estimation (using current generation time-digitizers). The time-digitization unit is an essential component needed to perform interconnect based thermal sensing in deep nanometer designs but it adds area and power overhead to the sensor design and limits the resolution of the wire-based sensor. We propose a novel sensor design that alleviates complexities associated with time-to-digital conversion in wire-based thermal sensing. The IBOTS or Interconnect Based Oscillator for Thermal Sensing makes use of wire-segments between individual stages of a ring-oscillator to perform thermal sensing using the oscillator frequency value as the mapping to corresponding wire temperature. The frequency output can be used to generate a digital code by interfacing the IBOTS with a digital counter. In 45nm technology, it is capable of providing a resolution of 1°C while consuming an active power of 250-360µW.

Surface and grain boundary electron scattering contribute significantly to resistivity as the dimensions of polycrystalline metallic conductors are reduced to, and below, the electron mean free path. A quantitative measurement of the relative contributions of surface and grain boundary scattering to resistivity is very challenging, requiring not only the preparation of suitably small conductors having independent variation of the two relevant length scales, namely, the sample critical dimension and the grain size, but also independent experimental quantification of these two length scales. In most work to date the sample grain size has been either assumed equal to conductor dimension or measured for only a small number of grains. Thus, the quantification of the classical size effect still suffers from an uncertainty in the relative contributions of surface and grain boundary scattering. In this work, a quantitative analysis of both surface and grain boundary scattering in Cu thin films with independent variation of film thickness (27 nm to 158 nm) and grain size (35 nm to 425 nm) in samples prepared by sub-ambient temperature film deposition followed by annealing is reported. Film resistivities of carefully characterized samples were measured at both room temperature and at 4.2 K and were compared with several scattering models that include the effects of surface and grain boundary scattering. Grain boundary scattering is found to provide the strongest contribution to the resistivity increase. However, a weaker, but significant, role is also observed for surface scattering. Several of the published models for grain boundary and surface scattering are explored and the Matthiessen's rule combination of the Mayadas and Shatzkes' model of grain boundary scattering and Fuchs and Sondheimer's model of surface scattering resistivity contributions is found to be most appropriate. It is found that the experimental data are best described by a grain boundary reflection coefficient of 0.43 and a surface specularity coefficient of 0.52. This analysis finds a significantly lower contribution from surface scattering than has been reported in previous works, which is in part due to the careful quantitative microstructural characterization of samples performed. The data does suggest that there is a roughness dependence to the surface scattering, but this was not conclusively demonstrated. Voids and impurities were found to have negligible impact on the measured resistivities of the carefully prepared films.

Three growing power electronics applications have massive requirements for properly operating their medium-voltage and high-voltage systems: electric transportation, renewable energy, and the power grid. Their needs include dense power systems with higher efficiency and higher voltage and current devices. This requires devices with higher switching frequencies to lower the size of the passives in the converter and devices that can withstand higher operating temperatures as components move closer together to improve power densities. Devices that achieve higher switching speeds and lower specific on-state resistances also reduce losses. Wide bandgap devices (WBG) like silicon carbide (SiC) have a higher bandgap, higher electric field strength, higher thermal conductivity, and lower carrier concentration than silicon (Si). This allows for higher temperature operation, faster switching, higher voltage blocking, and lower power losses, directly meeting the requirements of the previously noted applications. However, the current packaging schemes are limiting the ability of SiC to operate in these applications by applying packaging schemes used for Si. Therefore, it is critical to use and refine advanced packaging techniques so that WBG devices can better operate and meet the growing demands of these power electronic applications. Low-inductance, wirebond-less, high-density, scalable modules are possible due to advanced packaging methods. While beneficial to the operation and design, these techniques introduce new challenges to the fabrication process. This requires refinement to improve the yield of sandwich-structure modules with wirebond-less interconnects. For this module, encapsulated, silver-sintered substrates reduce the peak electric field within the package, improving the partial discharge inception voltage to meet insulation requirements. It is essential to have a uniform bondline between the substrates to achieve all bond connections and improve reliability. Silver sintering is also used to attach the molybdenum (Mo) post interconnects. These interconnects allow for sandwich-structure modules with low inductances; however, they have tolerance variation from manufacturing and bondline thicknesses, which become problematic for multi-chip power modules with an increased number of die and posts. The variation results in tilt, causing some posts to disconnect altogether. Additionally, soldering MCPMs involves a large thermal mass that the soldering reflow profile from a datasheet does not account for. Ultimately, these fabrication concerns can result in misalignment or disconnected post interconnects to the top substrate. Post interconnect planarity and alignment are vital for this multi-chip power module to avoid open or shorted connections that can derate switch positions. This thesis aims to refine each packaging step in assembling a wirebond-less, multi-chip power module. The bond uniformity of silver (Ag) sintering is addressed in dried preform and wet paste cases. The soldering methods are explored and improved by creating a modified reflow profile for large thermal masses and introducing pressure to reduce bondline variation and voiding content. The entire sandwich structure module is analyzed in a statistical tolerance analysis to understand which component introduces the most variation and height mismatch, providing insight as to which packaging techniques need further control to improve the yield of multi-chip power modules. / Master of Science / The electrification of many systems worldwide has increased the need for compact, efficient power electronics. Their applications span electric transportation, renewable energy systems, grid applications, and data centers, to name a few medium-voltage applications. Wide bandgap (WBG) semiconductors can outperform silicon in these applications, offering higher temperature robustness, higher efficiency performance, and higher voltage capabilities. The faster switching will reduce the size and weight of the converters containing these devices. However, using typical packaging schemes such as wirebonds will limit the potential of WBG devices in these applications. Advanced packaging techniques have been developed to increase the electric field strength, reduce the power loop inductances, reduce electromagnetic interference from fast-switching transients, and improve the power densities of multi-chip power modules for medium voltage and current applications. However, these packaging techniques are not trivial to implement and have resulted in a low yield of these modules. This thesis aims to refine each packaging step in assembling a wirebond-less, multi-chip power module. The bond uniformity of silver sintering is addressed in cases of dried preform and wet paste. The soldering methods are explored and improved by creating a modified reflow profile for large thermal masses and introducing pressure to reduce bondline variation and voiding content. The entire sandwich structure module is analyzed in a statistical tolerance analysis to understand which component introduces the most variation and height mismatch, providing insight as to which packaging techniques need further control to improve the yield of multi-chip power modules.

Owing to its excellent scaling potential, low power consumption, high switching speed, and good retention, and endurance properties, Resistive Random Access Memory (RRAM) is one of the prime candidates to supplant current Nonvolatile Memory (NVM) based on the floating gate (FG) MOSFET transistor, which is at the end of its scaling capability. The RRAM technology comprises two subcategories: 1) the resistive phase change memory (PCM), which has been very recently deployed commercially, and 2) the filamentary conductive bridge RAM (CBRAM) which holds the promise of even better scaling potential, less power consumption, and faster access times. This thesis focuses on several aspects of the CBRAM technology. CBRAM devices are based on nanoionics transport and chemo-physical reactions to create filamentary conductive paths across a dielectric sandwiched between two metal electrodes. These nano-size filaments can be formed and ruptured reliably and repeatedly by application of appropriate voltages. Although, there exists a large body of literature on this topic, many aspects of the CBRAM mechanisms and are still poorly understood. In the next paragraph, the aspects of CBRAM studied in this thesis are spelled out in more detail. CBRAM cell is not only an attractive candidate for a memory cell but is also a good implementation of a new circuit element, called memristor, as postulated by Leon Chua. Basically, a memristor, is a resistor with a memory. Such an element holds the promise to mimic neurological switching of neuron and synapses in human brain that are much more efficient than the Neuman computer architecture with its current CMOS logic technology. A memristive circuitry can possibly lead to much more powerful neural computers in the future. In the course of the research undertaken in this thesis, many memristive properties of the resistive cells have been found and used in models to describe the behavior of the resistive switching devices. The research performed in this study has also an immediate commercial application. Currently, the semiconductor industry is faced with so-called latency scaling dilemma. In the past, the bottleneck for the signal propagation was the time delay of the transistor. Today, the transistors became so fast that the bottleneck for the signal propagation is now the RC time delay of the interconnecting metal lines. Scaling drives both, resistance and parasitic capacitance of the metal lines to very high values. In this context, one observes that resistive switching memory does not require a Si substrate. It is therefore an excellent candidate for its implementation as an o n-chip memory above the logic circuits in the CMOS back-end, thus making the signal paths between logic and memory extremely short. In the framework of a Semiconductor Research Corporation (SRC) project with Intel Corporation, this thesis investigated the breakdown and resistive switching properties of currently deployed low k interlayer dielectrics to understand the mechanisms and potential of different material choices for a realization of an RRAM memory to be implemented in the back-end of a CMOS process flow. / Master of Science

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The interactions between different components of solid oxide cells (SOCs) are critical issues for achieving the tens of thousands of hour's goal for long-term performance stability and lifetime. The interactions between the ceramic electrolyte, porous ceramic air electrode, and metallic interconnect materials — including solid state interfacial reactions and vaporization/deposition of some volatile elements — have been investigated in the simulated SOC operating environment. The interactions demonstrate the material degradation mechanisms of the cell components and the effects of different factors such as chemical composition and microstructure of the materials, as well as atmosphere and current load on the air electrode side. In the aspect of materials, this work contributes to the degradation mechanism on the air electrode side and provides practical material design criteria for long-term SOC operation. In this research, an yttria-stabilized zirconia electrolyte (YSZ)/strontium-doped lanthanum manganite electrode (LSM)/AISI 441 stainless steel interconnect tri-layer structure has been fabricated in order to simulate the air electrode working environment of a real cell. The tri-layer samples have been treated in dry/moist air atmospheres at 800°C for up to 500 h. The LSM air electrode shows slight grain growth, but the growth is less in moist atmospheres. The amount of Cr deposition on the LSM surface is slightly more for the samples thermally treated in the moist atmospheres. At the YSZ/LSM interface, La enrichment is significant while Mn depletion occurs. The Cr deposition at the YSZ/LSM interface is observed. The stoichiometry of the air electrode is an important factor for the interactions. The air electrode composition has been varied by changing the x value in (La0.8Sr0.2)xMnO₃ from 0.95 to 1.05 (LSM95, LSM100, and LSM105). The enrichment of La at the YSZ/LSM interface inhibits the Cr deposition. The mechanisms of Cr poisoning and LSM elemental surface segregation are discussed. A 200 mA·cm-2 current load have been applied on the simulated cells. Mn is a key element for Cr deposition under polarization. Excessive Mn in the LSM lessens the formation of La-containing phases at the YSZ/LSM interface and accelerates Cr deposition. Deficient Mn in LSM leads to extensive interfacial reaction with YSZ forming more La-containing phase and inhibiting Cr deposition. / Ph. D.