Photoconductive microwave switches can be used in place of traditional microwave switches to reconfigure antennas and RF circuits. The switch, which consists of a silicon die placed over a gap in transmission line, is controlled by illumination via a fibre optic cable. Hence there is no requirement to design electrical biasing lines which may affect RF performance. This benefit is the main motivation behind further developing and understanding the photoconductive switch. The second motivation is the growing demand for reconfigurable antennas which necessitate certain switching requirements; one specific area of interest is in cognitive radio applications. However, in order to use such a switch in RF circuitry, the photoconductive nature of the switch must be understood. This is addressed in this thesis presenting and applying analytical equations which dictate the material properties in photoconductive silicon. These equations are then used to generate a 3D EM simulation model to investigate transmission loss in the photoconductive switch. The concept of signal planarity is investigated so as to give some insight into the best way to package the switch. In order to potentially reduce loss and facilitate a packaged device, the fabrication of the switch is investigated. Namely, the treatment of the silicon and the addition of contacts on the silicon are discussed as possible methods to improve switch performance. Lastly, linearity, power handing and switching times are presented for the photoconductive switch. This characterisation is important with regards to understanding which types of application the switch can be used in. In particular the single tone and two tone linearity of the switch is measured these values have not previously been reported for this type of photoconductive switch. The results are encouraging and support further development of the switch into a packaged product to be used in reconfigurable antennas and circuitry.

This thesis proposed and demonstrated a new all-polymer based fabrication process for an all-polymer flexible and parallel optical interconnect cable having a vertical light coupler, which can not only cut down the cost by eliminating metallization process for alignment but also facilitate both in production and application. Throughout the process, polyimide was used as the substrate, coated by Epoclad as claddings, then AP2210B and WPR 5100 were used to fabricate waveguides and 45 degree mirror couplers, respectively. In addition, precisely aligned mirror couplers to waveguides are fabricated by using polymer-based, non-metallic, and transparent alignment marks. Conventional and metallic alignment marks are easy to be detected by camera, when a layer of high reflective material, generally Cr metal, is patterned. However, transparent polymer material is used in this process, as alignment marks made of it which are actually buried phase structures. Therefore, it is hardly to be observed by conventional microscopy system. Hence, to increase the contrast of the alignment marks, I proposed and tested a feature specific alignment camera system for which the shape and depth of the alignment marks are optimized for phase-based imaging, such as phase contrast and Schlieren imaging. The results showed a contrast enhancement of alignment marks image compared to that of a conventional microscopy system. By using the fabrication and alignment process, process for adding waveguides to the structure is identified by using the polymer based alignment marks on the WPR 5100 layer. Mask was made by etch down process using fused silica wafer plate, Cr and AZ 3312 photoresist. At last, the developed and proposed process provides means of all-polymer based fabrication process for a flexible and parallel optical interconnect.

Future copper interconnect systems will require replacement of the materials that currently comprise both the liner layer(s) and the capping layer. Ruthenium has previously been considered as a material that could function as a single material liner, however its poor ability to prevent copper diffusion makes it incompatible with liner requirements. A recently described chemical vapor deposition route to amorphous ruthenium-phosphorus alloy films could correct this problem by eliminating the grain boundaries found in pure ruthenium films. Bias-temperature stressing of capacitor structures using 5 nm ruthenium-phosphorus film as a barrier to copper diffusion and analysis of the times-to-failure at accelerated temperature and field conditions implies that ruthenium-phosphorus performs acceptably as a diffusion barrier for temperatures above 165 °C. The future problems associated with the copper capping layer are primarily due to the poor adhesion between copper and the current Si-based capping layers. Cobalt, which adheres well to copper, has been widely proposed to replace the Si-based materials, but its ability to prevent copper diffusion must be improved if it is to be successfully implemented in the interconnect. Using a dual-source chemistry of dicobaltoctacarbonyl and trimethylphosphine at temperatures from 250-350 °C, amorphous cobalt-phosphorus can be deposited by chemical vapor deposition. The films contain elemental cobalt and phosphorus, plus some carbon impurity, which is incorporated in the film as both graphitic and carbidic (bonded to cobalt) carbon. When deposited on copper, the adhesion between the two materials remains strong despite the presence of phosphorus and carbon at the interface, but the selectivity for growth on copper compared to silicon dioxide is poor and must be improved prior to consideration for application in interconnect systems. A single molecule precursor containing both cobalt and phosphorus atoms, tetrakis(trimethylphosphine)cobalt(0), yields cobalt-phosphorus films without any co-reactant. However, the molecule does not contain sufficient amounts of amorphizing agents to fully eliminate grain boundaries, and the resulting film is nanocrystalline. / text

In order to carry out the complicated computation inside the high performance computing (HPC) systems, tens to hundreds of parallel processor chips and physical wires are required to be integrated inside the multi-chip package module (MCM). The physical wires considered as the electrical interconnects between the processor chips, however, have the challenges on placements and routings because of the unequal progress between the semiconductor and I/O size reductions. The primary goal of the research is to overcome package design challenges - providing a hybrid computing architecture with implemented 60 GHz antennas as the high efficient wireless interconnect which could generate over 10 Gbps bandwidth on the data transmissions. The dissertation is divided into three major parts. In the first part, two different performance metrics, power loss required to be recovered (PRE) and wireless link budget, on evaluating the antenna's system performance within the chip to chip wireless interconnect are introduced to address the design challenges and define the design goals. The second part contains the design concept, fabrication procedure and measurements of implemented 60 GHz broadband antenna in the application of multi-chip data transmissions. The developed antenna utilizes the periodically-patched artificial magnetic conductor (AMC) structure associated with the ground-shielded conductor in order to enhance the antenna's impedance matching bandwidth. The validation presents that over 10 GHz -10 dB S11 bandwidth which indicates the antenna's operating bandwidth and the horizontal data transmission capability which is required by planar type chip to chip interconnect can be achieved with the design concept. In order to reduce both PRE and wireless link budget numbers, a 60 GHz two-element array in the multi-chip communication is developed in the third part. The third section includes the combined-field analysis, the design concepts on two-element array and feeding circuitry. The simulation results agree with the predicted field analysis and demonstrate the 5dBi gain enhancement in the horizontal direction over a single 60 GHz AMC antenna to further reduce both PRE and wireless link budget numbers.

Metallic interconnects in intermediate temperature solid oxide fuel cells (IT-SOFC) stacks form Cr2O3 scales on their surface. Such oxide scales can be further oxidized to Cr6+ containing gaseous species that migrate and deposit at the cathode triple phase boundaries, causing significant degradation in the performance of the SOFCs. This phenomenon is termed as ‘Cr-poisoning’. A solution to this problem is the application of coatings on the interconnects that act as a diffusion barrier to Cr migration. Two different Cu/Mn spinel compositions, Cu1.3Mn1.7O4 and CuMn1.8O4, were studied as coating materials. Dense coatings were deposited on both flat plates and meshes by electrophoretic deposition (EPD) followed by subsequent thermo-mechanical or thermal densification steps. At room temperature, Cu1.3Mn1.7O4 coatings were found to have a mixture of CuO and spinel phases, while CuMn1.8O4 coatings were found to have a mixture of Mn3O4 and spinel phases. However, CuMn1.8O4 is a pure spinel phase between 750 °C and 850 °C. After densification processing and high temperature oxidation, a Cr2O3 layer was formed at the coating/alloy interface, which partially reacted with the spinel coatings to form a dense cubic spinel layer of the general composition (Cu,Mn,Cr)3-xO4. In addition, Cr-rich precipitates, formed in the dense layer close to coating/alloy interface. It is believed that these are Cr2O3 precipitates, formed when the solubility of Cr in the spinel phase is reached. Solubility experiments using powders showed that 1 mole of CuMn1.8O4 can effectively getter 1.83 moles of Cr2O3 at 800°C. Electrical conductivity of (Cu,Mn,Cr)3-xO4 was found to be at least two orders of magnitude higher than that of Cr2O3. The coatings acted as an effective Cr getter whose lifetime depends on the oxidation temperature, coating thickness, and the overall porosity in the coating. In-cell electrochemical testing showed that the CuMn1.8O4 coatings on Crofer 22 APU meshes performed significantly better than commercial Cu/Mn spinel coatings. The CuMn1.8O4 coatings gettered Cr effectively for 12 days at 800 ºC, leading to no performance loss of the cell due to Cr-poisoning. Significantly longer lifetime can be achieved at 750 ºC or lower, which is the target operational temperature regime of IT-SOFCs.

L'essor des réseaux de télécommunications à l'échelle mondiale génère un besoin croissant en termes de bande passante et de gestion de l'information. Le traitement de ces données requiert le développement de systèmes complexes, qui associent des fonctionnalités hétérogènes telles que des calculateurs numériques, des fonctions analogiques et des mémoires de stockage. L'approche originale retenue repose sur un degré d'innovation sans précédent dans le domaine de la microélectronique puisqu'elle mêle à la fois des technologies d'intégration 3D et le développement d'une filière photonique sur silicium. Des signaux très rapides (25, 40 ou 60 Gb/s) doivent donc être acheminés à travers les interconnexions 3D que sont le TSV (via traversant le silicium), les µ-bumps (connexions de cuivre entre les puces), les lignes de RDL (redistribution en face arrière) et les bumps qui assurent la communication vers l'extérieur. Il est nécessaire de développer de nouvelles technologies pour interconnecter les circuits à ces vitesses et de les modéliser finement jusqu'à de très hautes fréquences (>50 GHz), au moyen de techniques de caractérisation à développer, pour optimiser leur mode de réalisation. Ce travail de thèse se déroulera dans le cadre d'une collaboration tripartite et sera décomposé en quatre grandes étapes. 1. Spécifications des briques technologiques et de structures de test dédiées à l'évaluation de leurs performances dans le contexte de l'interposer photonique 2. Intégration des circuits de test, composés d'un empilement de puces logiques sur un interposer photonique, et adaptés au domaine fréquentiel visé avec les interconnexions 3D 3. Développement et mise en oeuvre des techniques de caractérisation à très haute fréquence des interconnexions 3D menant à l'extraction des modèles 4. Optimisation des lignes de transmission et des choix technologiques pour un routage efficace dans les architectures photoniques 3D / The worldwide growth of telecommunication networks drives an increasing need in terms of bandwidth and computing management. Data processing requires the development of complex system, which combines both heterogeneous functionalities such as numeric calculator, analog functions and memory storage. The original chosen approach is highly innovative in the field of microelectronics as it combines both 3D technologies and process integration for photonic on silicon. High speed signals (25, 40 or 60 Gb/s) are transmitted within the photonic interposer through 3D interconnects that are TSV (Trough-Silicon-Via), µ-bumps (copper connection in-between dies), RDL (Redistribution Line) and bumps (copper connection to the bottom access). Thereby, it is necessary to develop new technologies and new assemblies to interconnect and route efficiently those high speed circuits. Another challenge is to model them precisely for very high frequencies (>50 GHz), exploiting and developing the best characterization solutions in order to optimize the way to implement them. This PhD work will be performed in the frame of a tripartite collaboration and can be divided into four parts: 1. Specification of the key interconnects building-blocks and their associated test structures required to evaluate their performance in the context of a photonic interposer 2. Integration of the RF test circuits in the context of the stack of high speed logic dies over a photonic interposer using the developed 3D interconnects 3. Characterization of the test structures at very high frequency using dedicated characterization technics and extraction of equivalent models. Comparison with electromagnetic simulation 4. Validation of the technological and integration choices. Optimization of the transmission lines for efficient routing applied to 3D photonic structures

<p>This thesis work investigates the effects of crosstalk on on-chip interconnects. We use optimal repeater insertion as a reference and derive analytical expressions for signal latency, maximum data-rate and power consumption. Through calculations and simulations we show that despite large uncertainties in arrival time of a signal that is subject to crosstalk, we are able to make predictions about the maximum data-rate on a bus. We also show that data-rates can exceed the classical limit of the latency inverted by using wave pipelining. To increase the data-rate, we can increase the number of repeaters to a limit, at the cost of additional latency and power. Savings in power consumption can be achieved by using fewer repeaters, paying in latency and data-rate. Through fewer repeaters, the top metal layer shows better performance in all investigated aspects.</p>

<p>With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget.</p><p>Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).</p>

No description available.

Several challenges are still holding back the technological transfer of printed electronics to industry in spite of recent progresses. In this thesis work, the printing method of inks based on silver nanoparticles (<Ø>=25 nm) was optimized according to its rheology and to the fluid/substrate interactions for the fabrication of electrical interconnections with a thickness of 500 nm. These lines were printed on silicon or flexible substrates and annealed either by conventional (oven or infrared) or selective methods (microwave) at temperatures comprised between 100 and 300 °C.A better understanding of the relationship between process and microstructure of these printed thin films, based on several crystallographic equipments (XRD, EBSD and EDX), led to the optimization of nanocrystallites growth with an activation energy of about 3 to 5 kJ*mol-1. In addition to the low residual stress (70 MPa), this optimization is used to achieve low electrical resistivity (3.4 μOhm*cm) associated with a greater coherence of the crystal lattices at grain boundaries. The probability of electron scattering at such interfaces can be further reduced using an innovative approach of oriented crystallite growth by atomic interdiffusion from the substrate.The low mechanical stiffness (E<50 GPa) of these porous lines requires a reinforcement step either by crystalline texturation or by electroless growth to withstand the assembly and wire-bonding steps. The fabrication of a functional demonstrator thus validated the printing technology for the manufacture of electronic components.