In this dissertation, a predictive (scalable) measurement-based PEEC modeling method for high-frequency interconnects on low-cost FR4 substrates is proposed and demonstrated. The interconnects are modeled with equivalent circuits of scalable building blocks using a rapid and accurate optimization method to fit parameter data up to 10 GHz. The predictive power of the developed scalable models is demonstrated in several extended interconnect structures and the ability to use interpolation to predict the high frequency performance of structures with differently sized building blocks is demonstrated. The usefulness of the proposed modeling method is validated by comparing predictions to measurements both in frequency domain and in time domain. The efficiency and accuracy of the method are also compared with the Advanced Design System (ADS) momentum simulation tool. The results show that this proposed high-frequency interconnect modeling method is very much more efficient in terms of simulation time, while maintaining comparable accuracy, compared to momentum simulations and measured behavior.

The objective of the research is to model the reliability and breakdown mechanism of back-end dielectrics in integrated circuits and to investigate the impact of physical design characteristics on the back-end dielectric reliability. As design and process complexities continue to increase, the reliability of the back-end dielectrics becomes marginal. This is mainly because the power supply voltage is not scaled at a rate comparable to feature size, which results in exponentially increasing electric fields among interconnect lines. Therefore, it is strongly desirable to be able to predict reliability or to detect design weaknesses to reliability failure during the pre-silicon verification stage. It is desirable to enable pre-silicon verification of back-end dielectric reliability based on physical design characteristics. In this research, it is shown that dielectric reliability can be modeled as a function of the critical circuit area based on the yield models. Defect clustering is taken into account by using the negative binomial statistics. The physical design characteristics will be investigated for their impact on back-end dielectric reliability. These characteristics include such factors as layout geometry, pattern density, pattern orientation, and via placement. The physical breakdown mechanism for porous back-end dielectric films is also to be investigated using Monte Carlo simulation. It is shown that the electric field is enhanced by porosity in ultra-low-k dielectric films. The electric field enhancement caused by the porosity is shown to accelerate the charge transport.

Interconnect modeling plays an important role in design and verification of VLSI circuits and packages. For low frequency circuits, great advances for parasitic resistance and capacitance extraction have been achieved and wide varieties of techniques are available. However, for high frequency circuits and packages, parasitic inductance and impedance extraction still poses a tremendous challenge. Existing algorithms, such as FastImp and FastHenry developed by MIT, are slow and inherently unable to handle multiple dielectrics and magnetic materials. In this research, we solve three problems in interconnect modeling for high frequency circuits and packages. 1) Multiple dielectrics are common in integrated circuits and packages. We propose the first Boundary Element Method (BEM) algorithm for impedance extraction of interconnects with multiple dielectrics. The algorithm uses a novel equivalentcharge formulation to model the extraction problem with significantly fewer unknowns. Then fast matrix-vector multiplication and effective preconditioning techniques are applied to speed up the solution of linear systems. Experimental results show that the algorithm is significantly faster than existing methods with sufficient accuracy. 2) Magnetic materials are widely used in MEMS, RFID and MRAM. We present the first BEM algorithm to extract interconnect inductance with magnetic materials. The algorithm models magnetic characteristics by the Landau Lifshitz Gilbert equation and fictitious magnetic charges. The algorithm is accelerated by approximating magnetic charge effects and by modeling currents with solenoidal basis. The relative error of the algorithm with respect to the commercial tool is below 3%, while the speed is up to one magnitude faster. 3) Since traditional interconnect model includes mutual inductances between pairs of segments, the resulting circuit matrix is very dense. This has been the main bottleneck in the use of the interconnect model. Recently, K = L-1 is used. The RKC model is sparse and stable. We study the practical issues of the RKC model. We validate the RKC model and propose an efficient way to achieve high accuracy extraction by circuit simulations of practical examples.

We proposes an efficient algorithm for extracting SPICE-compatible circuits of embedded interconnect structures from FDTD-simulated time-domain reflections. A layer-peeling technique (LPT) is used to obtain the time-domain step response of the interconnects under extract (IUE) itself. A pencil matrix method is then used to get the pole-residue representation of the time-domain step response of the IUE. A pole-reducing procedure is implemented based on a bandwidth criterion to simplify pole-residue representation. Finally, the lumped equivalent models of the IUE are synthesized by an equivalent lumped-model extraction technique, in which four types of equivalent model bases are used. The equivalent circuit can be easily implemented in SPICE-like simulator. Several transmission line structures are presented as examples to demonstrate the validity of the proposed algorithm both in time and frequency domains.

As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multi-million gate ASIC designs it is crucial to have fast algorithms in the design automation tools for many classical problems in the field to shorten time to market of the VLSI chip. This research presents algorithmic techniques and constructive models for two such problems: (1) Fast buffer insertion for delay optimization, (2) Wire sizing for delay optimization and variation minimization on non-tree networks. For the buffer insertion problem, this dissertation proposes several innovative speedup techniques for different problem formulations and the realistic requirement. For the basic buffer insertion problem, an O(n log2 n) optimal algorithm that runs much faster than the previous classical van Ginneken’s O(n2) algorithm is proposed, where n is the number of buffer positions. For modern design libraries that contain hundreds of buffers, this research also proposes an optimal algorithm in O(bn2) time for b buffer types, a significant improvement over the previous O(b2n2) algorithm by Lillis, Cheng and Lin. For nets with small numbers of sinks and large numbers of buffer positions, a simple O(mn) optimal algorithm is proposed, where m is the number of sinks. For the buffer insertion with minimum cost problem, the problem is first proved to be NP-complete. Then several optimal and approximation techniques are proposed to further speed up the buffer insertion algorithm with resource control for big industrial designs. For the wire sizing problem, we propose a systematic method to size the wires of general non-tree RC networks. The new method can be used for delay optimization and variation reduction.

Electromigration (EM) remains a major reliability concern for on-chip Cu interconnects due to the continuing scaling and the introduction of new materials and processes. In Cu interconnects, the atomic diffusion along the Cu/SiCN cap interface dominates the mass transport and thus controls EM reliability. The EM lifetime degrades by half for each new generation due to the scaling of the critical void volume which induces the EM failure. To improve the EM performance, a metal cap such as CoWP was applied to the Cu surface to suppress the interfacial diffusion. By this approach, two orders of magnitude improvement in the EM lifetime was demonstrated. For Cu lines narrower than 90 nm, the Cu grain structure degraded from bamboo-like grains to polycrystalline grains due to the insufficient grain growth in the trench. Such a change in Cu grain structures can increase the mass transport through grain boundaries and thus degrade the EM performance. The objective of this study is to investigate the scaling effect on EM lifetime and Cu microstructure, and more importantly, the grain structure effect on EM behaviors of Cu interconnects with the CoWP cap compared to those with the SiCN cap only. This thesis is organized into three parts. In the first part, the effect of via scaling on EM reliability was studied by examining two types of specially designed test structures. The EM lifetime degraded with the via size scaling because the critical void size that causes the EM failure is the same with the via size. The line scaling effect on Cu grain structures were identified by examining Cu lines down to 60 nm in width using both plan-view and cross-sectional view transmission electron microscopy. In the second part, the effect of grain structure was investigated by examining the EM lifetime, statistics and failure modes for Cu interconnects with different caps. A more significant effect of the grain structure on EM characteristics was observed for the CoWP cap compared to the SiCN cap. For the CoWP cap, the grain structure not only affected the mass transport rate along the Cu line, but also impacted the flux divergence site distribution which determined the voiding location and the lifetime statistics. Finally, the effect of grain structure on EM characteristics of CoWP capped Cu interconnects was examined using a microstructure-based statistical model. In this model, the microstructure of Cu interconnects was simplified as cluster and bamboo grains connected in series. Based on the weakest-link approximation, it was shown that the EM lifetime and statistics could be adequately modeled by combining the measured cluster length distribution with the EM lifetime-cluster length correlation for each individual failure unit. / text

Wires have become a major source of bottleneck in current VLSI designs, and wire length prediction is therefore essential to overcome these bottlenecks. Wire length prediction is broadly classified into two types: macroscopic prediction, which is the prediction of wire length distribution, and microscopic prediction, which is the prediction of individual wire lengths. The objective of this thesis is to develop a clear understanding of limitations to both macroscopic and microscopic a priori, post-placement, pre-routing wire length predictions, and thereby develop better wire length prediction models. Investigations carried out to understand the limitations to macroscopic prediction reveal that, in a given design (i) the variability of the wire length distribution increases with length and (ii) the use of Rent’s rule with a constant Rent’s exponent p, to calculate the terminal count of a given block size, limits the accuracy of the results from a macroscopic model. Therefore, a new model for the parameter p is developed to more accurately reflect the terminal count of a given block size in placement, and using this, a new more accurate macroscopic model is developed. In addition, a model to predict the variability is also incorporated into the macroscopic model. Studies to understand limitations to microscopic prediction reveal that (i) only a fraction of the wires in a given design are predictable, and these are mostly from shorter nets with smaller degrees and (ii) the current microscopic prediction models are built based on the assumption that a single metric could be used to accurately predict the individual length of all the wires in a design. In this thesis, an alternative microscopic model is developed for the predicting the shorter wires based on a hypothesis that there are multiple metrics that influence the length of the wires. Three different metrics are developed and fitted into a heuristic classification tree framework to provide a unified and more accurate microscopic model.

Solid Oxide Fuel Cells have attracted much attention over the past few decades due to their huge potential for clean power generation in stationary, portable and transport applications and our increasing need for sustainable energy resources. The purpose of this research is to develop an interconnect and cathode material for use in solid oxide fuel cells which demonstrates desired properties of high electrical conductivity, excellent chemical stability at high temperatures, desirable thermal expansion characteristics and which can be easily manufactured by sintering in conditions acceptable with other cell components. The present work was initiated to study the synthesis and properties of five different perovskite oxides comprising of Lanthanum in combination with different mol% of Chromium, Ferrum, Cobalt and Nickel. A polymer complexing route with slight modifications was used to prepare the precursor powders. The powder x-ray diffraction patterns at room temperature show that all samples were formed in single phase. The powders in the form of pellets were sintered at 1400°C. The temperature dependent resistivity data was measured and the conductivity data was calculated. This conductivity data have been fitted with the Arrhenius model for entire studied range of temperature (25-800°C) to calculate the activation energy. La based perovskite oxides were characterized using X-ray diffraction (XRD), and scanning electron microscopy (SEM). Electrical properties and microstructural studies show potential applications of the materials as interconnect and cathode for Solid Oxide Fuel Cell. The material which has the above desired properties was proposed and component modifications for tailoring such properties were shown for SOFCs and other similar applications.

Electromigration tests on different Cu dual-damascene interconnect tree structures consisting of various numbers of straight via-to-via lines connected at the common middle terminal have been carried out. Like Al-based interconnects, the reliability of a segment in a Cu-based interconnect tree strongly depends on the stress conditions of connected segments. The analytic model based on a nodal analysis developed for Al trees gives a conservative estimate of the lifetime of Cu-based interconnect trees. However, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are attributed to the variations in the architectural schemes of the two metallization systems. The absence of a conducting electromigration-resistant overlayer in Cu technology and the low critical stress for void nucleation at the Cu/inter-level diffusion barrier (i.e. Si₃N₄) interface leads to different failure modes between Cu and Al interconnects. As a result, the most highly stressed segment in a Cu-based interconnect tree is not always the least reliable. Moreover, the possibility of liner rupture at stressed dual-damascene vias leads to significant differences in tree reliabilities in Cu compared to Al. While an interconnect tree can be treated as a fundamental unit whose reliability is independent of that of other units in Al-based interconnect architectures, interconnect trees can not be treated as fundamental units for circuit-level reliability analyses for Cu-based interconnects. / Singapore-MIT Alliance (SMA)

No description available.