In an effort to lower interconnect time delays and power dissipation in highly integrated logic and memory nanoelectronic products, numerous changes in the materials and processes utilized to fabricate the interconnect have been made in the past decade. Chief among these changes has been the replacement of aluminum (Al) by copper (Cu) as the interconnect metal and the replacement of silicon dioxide (SiO2) by so called low dielectric constant (low-k) materials as the insulating interlayer dielectric (ILD). Cu/low-k structure significantly decreases the RC delay compared with the traditional interconnect (Al/SiO₂). Therefore, the implementation of low-k dielectric in Cu interconnect structures has become one of the key subjects in the microelectronics industry. Incorporation of pores into the existing low-k dielectric is a favorable approach to achieve ultra low-k ILD materials. To bring memory and logic closer together is an effective approach to remove the latency constraints in metal interconnects. The resistive random access memories (RRAM) technology can be integrated into a complementary metal-oxide-semiconductor (CMOS) metal interconnect structure using standard processes employed in back-end-of-line (BEOL) interconnect fabrication. Based on this premise, the study of this thesis aims at assessing a possible co-integration of resistive switching (RS) cells with current BEOL technology. In particular, the issue is whether RS can be realized with porous dielectrics, and if so, what is the electrical characterization of porous low-k/Cu interconnect-RS devices with varying percentages of porosity, and the diffusive and drift transport mechanism of Cu across the porous dielectric under high electric fields. This work addresses following three areas: 1. Suitability of porous dielectrics for resistive switching memory cells. The porous dielectrics of various porosity levels have been supplied for this work by Intel Inc. In course of the study, it has been found that Cu diffusion and Cu+ ion drift in porous materials can be significantly different from the corresponding properties in non-porous materials with the same material matrix. 2. Suitability of ruthenium as an inert electrode in resistive switching memory cells. Current state-of-the-art thin Cobalt (Co)/Tantalum Nitride (TaN) bilayer liner with physical vapor deposited (PVD) Cu-seed layer has been implemented for BEOL Cu/low-k interconnects. TaN is used for the barrier and Co is used to form the liner as well as promoting continuity for the Cu seed. Also, the feasibility of depositing thin CVD ruthenium (Ru) liners in BEOL metallization schemes has been evaluated. For this study, Ru is used as a liner instead of Ta or Co in BEOL interconnects to demonstrate whether it can be a potential candidate for replacing PVD-based TaN/Ta(Co)/Cu low-k technology. In this context, it is of interest to investigate how Ru would perform in well-characterized RS cell, like Cu/TaOx/Ru, given the fact that Cu/TaOx/Pt device have been proven to be good CBRAM device due to its excellent unipolar and bipolar switching characteristics, device performance, retention, reliability. If Cu/TaOx/Ru device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end. 3. Potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells. The BEOL reliability is tied to time dependent failure that occurs inside dielectric between metal lines. Assessing the suitability of covalent dielectrics for back-end metallization is therefore an interesting topic. TDDB measurements have been performed on pure covalent materials, low-k dielectric MIM and MI-semiconductor (MIS) devices supplied by Intel Inc. / Master of Science

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<p>At solid oxide fuel cell (SOFC) operating temperatures (650^oC--800^oC), the chromia scale growth on the interconnect surface and chromium poisoning of cathode can lead to performance degradation of the whole cell. A spinel coating can be effective for blocking chromium outward diffusion to overcome this issue. In this thesis, two spinel-forming systems, Zn-Mn-O and Co-Cu-Mn-O were studied to identify a suitable coating.</p> <p>In-situ high temperature XRD was used to identify the phases in the Zn-Mn-O system between 600^oC and 1300^oC. The results showed that cubic spinel phase was stable only at high temperatures (above 1200^oC) and when the temperature decreases, the cubic phase tends to deform to tetragonal structure. In addition, the conductivity results showed low conductivities (below 3 S/cm) at SOFC operating temperature. Thus, the Zn-Mn-O system is not suitable for SOFC interconnect coatings.</p> <p>Another potential coating material analyzed was the Co-Cu-Mn-O system. This system exhibited promising conductivity values. Electrodeposition was used to apply Co-Cu-Mn-O coatings on both ferritic stainless steel and chromium-based alloy (Cr-5Fe) followed by oxidation in air at 800^oC. The spinel coating formed nicely on the stainless steel substrate. However, on the chromium plate, nitride formation, blistering and metal isolation were the common problems that occurred during the oxidation process. In order to improve the quality of coating on the chromium alloy, different heat treatments were explored, such as annealing in reducing atmosphere, oxidation in pure oxygen / mixed gas and decreasing the oxidation temperature. The objective of modifying the heat treatment was to produce adherent, dense coatings.</p> / Master of Applied Science (MASc)

High performance RF/mixed signal systems require new interconnect strategies to combine high frequency (microwave/mm-wave) circuitry with silicon mixed-signal and baseband digital processing. In such systems, heterogeneous vertical integration, in which circuits in different technologies can be stacked on top of each other within the system architecture, can reduce the overall system size and power consumption. Chip stacking also enables optimally-performing heterogeneous systems, because each level of the stack can consist of components fabricated in their most suited device or substrate technology. Two novel approaches for the vertical interconnection of heterogeneous integrated systems are proposed in this work. These approaches are related to flip-chip bonding techniques used in Radio-Frequency (RF)/microwave integrated circuits. The first proposed approach involves an interlocking mechanical structure that supports flip-chip assembled Monolithic Microwave Integrated Circuits (MMICs). Photolithographically patterned thick-film SU-8 structures are applied to both the chip and the carrier such that the chip self-aligns into place and mates with the carrier. Gold bumps embedded within the structures electrically connect the chip pads to the carrier pads. This method is demonstrated through the assembly of a SiGe power amplifier MMIC onto a high resistivity silicon carrier. The second proposed approach involves vertical interconnects consisting of room temperature liquid-state metals. The fluid nature of the liquid bumps allows them to be robust in the presence of thermo-mechanical stresses, such as Coefficient of Thermal Expansion (CTE) mismatch between the interconnected chips. SU-8 structures are used to form a shaping mold on the bottom carrier that contains the liquid metal. Gold posts are electroplated on the top chip, then mated with the SU-8 mold, thereby making contact with the liquid metal to form the electrical continuity. For each of these proposed methods, design and fabrication considerations are discussed in detail. RF measurements on prototype structures up to Ka band are performed to verify the functionality of the proposed methods. Given the results of these proof-of-concept efforts, electrical characteristics of the materials used in these methods are determined, and recommendations are provided for future improvements and refinements to these two techniques. / Master of Science

With continuous and aggressive scaling in semiconductor technology, there is an increasing gap between design expectation and manufactured silicon data. Research on DFM (Design for manufacturability), MFD (Manufacturing for Design) and statistical analysis have been investigated in recent years to bridge design and manufacturing. Fundamentally, layout is the final output from the design side and the input to the manufacturing side. It is also the last chance to dramatically modify the design efficiently and economically. In this dissertation, I present the modeling and optimization work on bridging the gap between design expectation and reality, improving performance and enhancing manufacturing yield. I investigate several stages of semiconductor design development including manufacturing process, device, interconnect, and circuit level. In the manufacturing process stage, a novel inverse lithography technology (ILT) is proposed for sub-wavelength lithography resolution enhancement. New intuitive transformations enable the method to gradually converge to the optimal solution. A highly efficient method for gradient calculation is derived based on partially coherent optical models. Dose variation is considered within the ILO process with the min-max optimization method and the computation overhead on dose process variation could be omitted. The methods are implemented in state-of-the-art industrial 32nm lithography environment. After the work in the lithography process stage provides both mask optimization and post-layout silicon image simulation, my work on the first non-rectangular device modeling card extends the post-layout lithography to post-litho electrical calibration. Based on the lithography simulation results, the non-rectangular gate shapes are extracted and their effect is investigated by the proposed non-rectangular device modeling card and post-litho circuit simulation flow. This work is not only the first non-rectangular device modeling card but also compatible with industry standard device models and the parameter extraction flow. Interconnect plays a more critical role in the nanometer scale IC design especially because of its impact on delay. The scattering effect that occurs in nanoscale wires is modeled and different methods of wire sizing/shaping are discussed. Based on closed-form resistivity model for nanometer scale Cu interconnect, new interconnect delay model and wire sizing/shaping strategies are developed. Based on the advanced modeling of process, device and interconnect, circuit level investigation is focused on statistical timing analysis with a new latch delay model. For the first time, both combinational logic and clock distribution circuits are integrated together through statistical timing of latch outputs. This dissertation studies the new phenomena of nanometer scale IC design and manufacture. Starting from the designed layout, through modeling, optimization and simulation, the work moves ahead to the mask pattern and silicon image, calibrates electrical properties of devices as well as circuits. Through above process, we can better connect layout with silicon data to reach design and manufacturing closure. / text

As the semiconductor technology roadmap further extends, the development of next generation silicon systems becomes critically challenged. On the one hand, design and manufacturing closures become much more difficult due to the widening gap between the increasing integration density and the limited manufacturing capability. As a result, manufacturability issues become more and more critically challenged in the design of reliable silicon systems. On the other hand, the continuous scaling of feature size imposes critical issues on traditional interconnect materials (Cu/Low-K dielectrics) due to power, delay and bandwidth concerns. As a result, multiple classes of new materials are under research and development for future generation technologies. In this dissertation, we investigate several critical Computer-Aided Design (CAD) challenges under advanced nanolithography and nanophotonics technologies. In addressing these challenges, we propose systematic CAD methodologies and optimization techniques to assist the design of high-yield and high-performance integrated circuits (IC) with low power consumption. In Very Large Scale Integration (VLSI) CAD for nanolithography, we study the manufacturing variability under resolution enhancement techniques (RETs) and explore two important topics: (1) fast and high fidelity lithography hotspot detection; (2) generic and efficient manufacturability aware physical design. For the first topic, we propose a number of CAD optimization and integration techniques to achieve the following goals in detecting lithography hotspots: (a) high hotspot detection accuracy; (b) low false-positive rate (hotspot false-alarms); (c) good capability to trade-off between detection accuracy and false-alarms; (d) fast CPU run-time; and (e) excellent layout coverage and computation scalability as design gets more complex. For the second topic, we explore the routing stage by incorporating post-RET manufacturability models into the mathematical formulation of a detailed router to achieve: (a) significantly reduced lithography-unfriendly patterns; (b) small CPU run-time overhead; and (c) formulation generality and compatibility to all types of RETs and evoling manufacturing conditions. In VLSI CAD for nanophotonics, we focus on three topics: (1) characterization and evaluation of standard on-chip nanophotonics devices; (2) low power planar routing for on-chip opto-electrically interconnected systems; (3) power-efficient and thermal-reliable design of nanophotonics Wavelength Division Multiplexing for ultra-high bandwidth on-chip communication. With simulations and experiments, we demonstrate the critical role and effectiveness of Computer-Aided Design techniques as the semiconductor industry marches forward in the deeper sub-micron (45nm and below) domain. / text

Made available in DSpace on 2014-12-17T14:07:21Z (GMT). No. of bitstreams: 1 ClawsioRCS_TESE.pdf: 6209957 bytes, checksum: 4a85a36be678a5c36d937dd4cb67fe7c (MD5) Previous issue date: 2014-04-28 / Conselho Nacional de Desenvolvimento Cient?fico e Tecnol?gico / Doped lanthanum chromite ( LaCrO3 ) has been the most common material used as interconnect in solid oxide fuel cells for high temperature ( SOFC-HT ) that enabling the stack of SOFCs. The reduction of the operating temperature, to around 800 ? C, of solid oxide fuel cells enabled the use of metallic interconnects as an alternative to ceramic LaCrO3, From the practical point of view, to be a strong candidate for interconnect the material must have good physical and mechanical properties such as resistance to oxidizing and reducing environments, easy manufacture and appropriate thermo-mechanical properties. Thus, a study on the physic-mechanical interconnects La0,8Sr0,2Cr0,92Co0,08O3 ceramics for SOFC -AT obtained by the method of combustion , as well as thermo-mechanical properties of metallic interconnects (AISI 444) covered with La0,8Ca0,2CrO3 by deposition technique by spray-pyrolysis fuel cells for intermediate temperature (IT-SOFCs). The La0,8Sr0,2Cr0,92Co0,08O3 was characterized by X -ray diffraction(XRD) , density and porosity , Vickers hardness (HV) , the flexural strength at room temperature and 900 ?C and scanning electron microscopy (SEM). The X -ray diffraction confirmed the phase formation and LaCrO3 and CoCr2O4, in order 6 GPa hardness and mechanical strength at room temperature was 62 MPa ceramic Interconnector. The coated metal interconnects La0,8Ca0,2CrO3 passed the identification by XRD after deposition of the film after the oxidation test. The oxidative behavior showed increased resistance to oxidation of the metal substrate covered by La0,8Ca0,2CrO3 In flexural strength of the coated metal substrate, it was noticed only in the increased room temperature. The a SEM analysis proved the formation of Cr2O3 and (Cr,Mn)3O4 layers on metal substrate and confirmed the stability of the ceramic La0,8 Ca0,2CrO3 film after oxidative test / A cromita de lant?nio (LaCrO3) dopada tem sido o material mais utilizado como interconector nas pilhas a combust?vel de ?xido s?lido de alta temperatura(PaCOS-AT), possibilitando o empilhamento(stack) da PaCOS. A redu??o da temperatura de opera??o, em torno de 800 ?C, das pilhas a combust?vel de ?xido s?lido, tornou poss?vel o uso de interconectores met?licos como alternativa aos LaCrO3 cer?micos. Do ponto de vista pr?tico para o material ser forte candidato a interconector deve ter boas propriedades f?sicas e mec?nicas, como resist?ncia a ambientes oxidantes e redutores, f?cil fabrica??o e propriedades termo-mec?nicas adequadas. Por este motivo realizou-se um estudo sobre as propriedades fisico-mec?nicas de interconectores de La0,8Sr0,2Cr0,92Co0,08O3 cer?mico para PaCOS-AT obtido pelo m?todo da combust?o, como tamb?m sobre as propriedades termo-mec?nicas de interconectores met?licos (AISI 444) recobertos com La0,8Ca0,2CrO3 pela t?cnica de deposi??o por spray-pir?lise para Pilhas a combust?vel de temperatura intermediaria (PaCOS-TI). A La0,8Sr0,2Cr0,92Co0,08O3 foi caracterizada por meio de difra??o de raios X (DRX), densidade e porosidade, dureza Vickers (HV), resist?ncia mec?nica a flex?o na temperatura ambiente e a 900?C e microscopia eletr?nica de varredura (MEV). A difra??o de raios X comprovou a forma??o das fases LaCrO3 e CoCr2O4, dureza na ordem de 6 GPa e resist?ncia mec?nica a temperatura ambiente de 62 MPa do interconector cer?mico. A avalia??o das fases formadas no interconector met?lico recoberto com La0,8Ca0,2CrO3 tanto na deposi??o quanto ap?s o ensaio oxidativo foi realizado por DRX. O comportamento oxidativo evidenciou o aumento da resist?ncia a oxida??o do substrato met?lico recoberto por La0,8Ca0,2CrO3. Na resist?ncia mec?nica a flex?o do substrato met?lico recoberto, notou-se o aumento apenas na temperatura ambiente. Com aux?lio do MEV comprovou-se a forma??o das camadas de Cr2O3 e (Cr,Mn)3O4 sobre o substrato met?lico e confirmou-se a estabilidade do filme cer?mico de La0,8Ca0,2CrO3 ap?s o ensaio oxidativo

Ce travail de thèse vise la définition et la mise au point de technologies pour l'empilement depuces microélectroniques dans un polymère et connectées électriquement par des viastraversants. Il explore deux voies : l’une de caractère industriel, utilisant une résine époxychargée en billes de silice E2517, l'autre, plus exploratoire, est basée sur l'utilisation de laSU8.Nous avons travaillé sur la mise au point des différentes étapes permettant d'empiler 4niveaux de puces amincies à 80 microns (enrobées) et empilées sur des épaisseurs de l'ordredu millimètre. Le problème du perçage des vias a été abordé et étudié à travers la mise aupoint de procédés d'usinage au laser des résines de type industriel. La métallisation encouches minces de ces trous de facteur de forme élevée (20) a été menée de sorte à atteindredes valeurs de résistance d'accès les plus faibles possibles.Un comparatif des deux voies utilisant la SU8 et la résine E2517 a été effectué et ses résultatscommentés en termes de faisabilité techniques et ses projections dans le domaine industriel.Des tests de fiabilité thermomécaniques ont été menés de concert avec une modélisation paréléments fini afin de valider les résultats des expérimentations réalisées dans le cadre de cetteétude / The subject of this thesis is the definition and development of TPV (Through Polymer Via)technology to stacking chips. The principal objective is to increase the potentialities of thevertical staking (complex IC; multiple I/O...) of Si chips without loss of performance or yield.The technique used consists to surround the IC chips by using particular resin and to fill (withmetallic films) the vertical holes drilled in this material. It explores two ways: one of anindustrial character, using an epoxy resin filled with silica beads E2517, other, moreexploratory, is based on the use of SU8.We worked on the development of different stages to stack four levels of chips thinned to 80microns (coated) and stacked on the thickness of one millimeter. The problem of drilling viashas been discussed and studied through the development of laser drilling processes ofindustrial resins. The thin-film metallization of the holes of high aspect ratio (20) wasconducted in order to reach values of access resistance as low as possible.A comparison of the two channels using SU8 resin and E2517 was carried out and the resultsdiscussed in terms of technical feasibility and its projections in the industrial field.Thermomechanical reliability tests were conducted in conjuction with finite element modelingto validate the results of experiments conducted in this study.