A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Hence, techniques to reduce interconnect power have become a necessity. In this thesis, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. To validate our methodology, we implement the router design in 90 nm technology and measure power for various bus widths and frequency combinations. We find that the experimental results are in good agreement with the predicted theoretical results. Further, we present the scenario of an Application Specific System on Chip (ASSoC), where the throughput requirements are different on different links. We show that our analytical model holds in this case also. Then, we present modified version of the solution considered for Chip Multi Processor (CMP) case that can solve the ASSoC scenario also.

In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results. / I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.

Die Entwicklung der Mikroelektronik wird durch eine fortschreitende Miniaturisierung der Bauelemente geprägt. Infolge einer Reduzierung der Querschnittflächen von Leitbahnstrukturen erhöht sich die elektrische Leistungsdichte und das Metallisierungssystem bestimmt zunehmend die Übertragungsgeschwindigkeiten. Kupfer repräsentiert hierbei das verbreitetste Leitbahnmaterial und wird vorwiegend mittels elektrochemischer Abscheidung in vergrabene Damaszen-Strukturen eingebracht. Die vorliegende Dissertation beschreibt Möglichkeiten für eine Optimierung von Kupferleitbahnen für höchstintegrierte Schaltkreise. Von besonderem Interesse sind hierbei die Gefügequalität und der Reinheitsgrad. Es erfolgen umfangreiche werkstoffanalytische und elektrochemische Untersuchungen zur Charakterisierung von Depositionsmechanismen, des Einbaus von Fremdstoffen, des Mikrogefüges nach der Abscheidung und der Mikrogefügeumwandlung. In einem abschließenden Forschungsschwerpunkt werden Kupfer-Damaszen-Teststrukturen mit unterschiedlichen Gehalten nichtmetallischer Verunreinigungen hergestellt und entsprechenden Lebensdauerexperimenten unterzogen. Hierdurch gelingt eine Evaluierung des Einflusses jener Verunreinigungen auf die Elektromigrationsbeständigkeit von Kupferleitbahnen. Die Arbeit umfasst daher das gesamte Spektrum von der Grundlagenforschung bis zur Applikation von elektrochemisch abgeschiedenen Kupferdünnschichtmetallisierungen.

As current environmental challenges are gaining increased attention, development of clean energy solutions is becoming one of the essential strategies to keep within the boundaries of established environmental policies. Solid oxide cell (SOC) technology can provide clean energy conversion and storage when hydrogen is the energy carrier. The high total energy conversion efficiency resulting from the high operation temperature of SOCs make the technology promising, but material costs must be reduced to make it commercially viable. Therefore, this thesis aims to study the long- term performance of a novel cost-optimized cell interconnect at 650 and 850 °C. At high temperatures, chromium evaporation from the interconnect result in electrode poisoning, which may be mitigated by application of a protective coating. The studied interconnect is an AISI 441 steel with some different pre-oxidized copper and iron spinel coatings. Sample analysis was made mainly with scanning electron microscopy coupled with energy dispersive X-ray spectroscopy and X-ray diffraction. It was found that the most promising pre-oxidation treatment was 24 h at 750 °C and that chromium migration was restrained at 650 °C long-term treatment but not at 850 °C where it wasfound available for evaporation at the surface. / När samtida milljöutmaningar får ökad uppmärksamhet blir gröna energilösningar en av de viktigaste strategierna för att hålla sig inom satta gränser från etablerade miljöriktlinjer. Teknologin bakom fastoxidceller, eller solid oxide cells (SOCs), kan bidra med grön omvandling och lagring av energi när energibäraren är väte. Den höga totala omvandlingseffektiviteten, som kommer med den höga verkningstemperaturen, gör SOC till en lovande teknologi, men materialkostnaderna måste först reduceras innan den blir komersiellt gångbar. Därför syftar detta examensarbete till att undersöka prestandan av en ny, kostnadsoptimerad cellinterkonnektor på lång sikt i 650 och 850 °C. Vid höga temperaturer förångas krom från interkonnektorn, vilket leder till elektrodförgiftning, men kan mildras genom applicering av en skyddande beläggning. Den undersökta interkonnektorn är ett stål som betäcknas AISI 441 belagt med några olika föroxiderade beläggningar av koppar- och järnspinell. Proverna analyserades i huvudsak genom svepelektronmikroskopi kobinerat med energidispersiv röntgenspektroskopi och röntgendiffraktometri. Det visades att den mest lovande föroxideringsbehandlingen var 24 h i 750 °C och att krom förblev återhållet vid 650 °men inte vid 850 °C då det fanns tillgängligt för förångning vidytan.

<p>A wide variety of phase evolution phenomena observed in solids such as intermetallic growth at the junction between two metals subjected to high temperature, growth of oxide on metal surfaces due to atmospheric exposure and void evolution induced by electromigration in microelectronic devices for example, can be classified as being driven by reaction-diffusion processes. These phase evolution phenomena have a significant impact on material reliability for critical applications, and therefore, there is a requirement for modeling such reaction-diffusion driven phase evolution phenomena. It is difficult to analyze these due to the complexity of modeling the evolving interface between solid phases. Additional complexity is  due to the multi-physics nature of the diffusive and reactive processes. Diffusion in solids is driven by a variety of stimuli such as current, temperature and stress, in addition to the chemical potential. Therefore, there is a need for a model that accounts for the influence of such factors on phase evolution. In this thesis,  a generalized continuum based reaction-diffusion theory for phase and void evolution in solid state is developed. The derivation starts off with generalized interface balance laws for mass, momentum and energy. The thermodynamic entropy inequality for irreversible phase growth is derived for arbitrary anisotropic and inhomogeneous surface stress. These interface relations are combined with governing relations in the material bulk for the temperature, stress, electrical and concentration fields, to develop a general model capable of analyzing and describing phase evolution in solids. This theory is then applied to a variety of intermetallic phase and void evolution phenomena observed in microelectronics.</p> <p><br></p> <p>Electromigration induced voiding in thin metal films is an example of phase evolution that is an important reliability concern in microelectronics. Studies have reported that the electromigration induced void growth rate is inversely related to the adhesion of metal thin films with the base and capping layers. Electromigration experiments are performed on fabricated test devices with Cu thin films with SiNx and TiN capping layers. The observations from electromigration experiments on thin Cu metal films at a range of temperatures indicate that the contribution of interface adhesion strength to electromigration resistance decreases with an increase in temperature. The generalized reaction-diffusion theory developed here is modified to develop an expression to account for the effect of base and passivation layer adhesion and temperature on electromigration resistance of metal thin films. The void growth rates measured in the experiments are analyzed with the expression for void growth rate to estimate the interface adhesion strength for the Cu-TiN and Cu-SiNx interfaces. </p> <p><br></p> <p>Demand for increased bandwidth, power efficiency and performance requirements have resulted in a trend of reduction in size and pitch of Cu pillar-Solder micro-bump interconnects used in heterogeneously integrated packages. As the size of micro-bumps reduce, reliability challenges due to voiding in the solder joint and the growth of Cu-Sn intermetallics are observed. The underlying reaction-diffusion mechanisms responsible for Cu-Sn intermetallic growth and voiding in solder joints are unclear at this stage and require further investigation. The current practice of material characterization in micro-bumps involve destructive cross-sectioning and polishing of the micro-bumps after testing. These processes result in loss of continuity in the samples used for the experiments, and material removal due to abrasive polishing might result in a loss of critical information. Therefore, a novel test device capable of non-destructive characterization of Cu-Sn intermetallic growth and voiding in sub-30 micron size micro-bumps is designed and fabricated in this work. The fabricated test devices are subjected to thermal aging for over 1000 h and the underlying reaction-diffusion mechanisms behind the intermetallic phase and void evolution are investigated. </p> <p><br></p> <p>A reaction-diffusion mechanism is proposed explaining the evolution of  various Cu-Sn intermetallic phases and solder joint void observed from experiments. Using the reaction-diffusion mechanism inferred from the thermal aging experiments and the generalized reaction-diffusion theory for phase evolution developed in this thesis, a sharp interface model is developed for the evolution of Cu-Sn intermetallic phases and solder joint void. The diffuse interface phase field equivalent equations for the sharp interface model governing equations are developed using matched formal asymptotic analysis. The evolution of Cu-Sn intermetallic phase and voids in the solder joint are simulated for different temperatures and current density to demonstrate the validity of the phase field and sharp interface models.  </p> <p><br></p>

In this dissertation, we use finite element method together with other numerical techniques to study advanced electron devices. We study the radiation properties in electron waveguide structure with multi-step discontinuities and soft wall lateral confinement. Radiation mechanism and conditions are examined by numerical simulation of dispersion relations and transport properties. The study of geometry variations shows its significant impact on the radiation intensity and direction. In particular, the periodic corrugation structure exhibits strong directional radiation. This interesting feature may be useful to design a nano-scale transmitter, a communication device for future nano-scale system. Non-quasi-static effects in AC characteristics of carbon nanotube field-effect transistors are examined by solving a full time-dependent, open-boundary Schrödinger equation. The non-quasi-static characteristics, such as the finite channel charging time, and the dependence of small signal transconductance and gate capacitance on the frequency, are explored. The validity of the widely used quasi-static approximation is examined. The results show that the quasi-static approximation overestimates the transconductance and gate capacitance at high frequencies, but gives a more accurate value for the intrinsic cut-off frequency over a wide range of bias conditions. The influence of metal interconnect resistance on the performance of vertical and lateral power MOSFETs is studied. Vertical MOSFETs in a D2PAK and DirectFET package, and lateral MOSFETs in power IC and flip chip are investigated as the case studies. The impact of various layout patterns and material properties on RDS(on) will provide useful guidelines for practical vertical and lateral power MOSFETs design.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

With the explosion of the number of compute nodes, the bottleneck of future computing systems lies in the network architecture connecting the nodes. Addressing the bottleneck requires replacing current backplane-based network topologies. We propose to revolutionize computing electronics by realizing embedded optical waveguides for onboard networking and wireless chip-to-chip links at 200-GHz carrier frequency connecting neighboring boards in a rack. The control of novel rate-adaptive optical and mm-wave transceivers needs tight interlinking with the system software for runtime resource management.

<p dir="ltr">Interconnects pose severe performance bottlenecks in advanced technology nodes due to multiple scaling challenges. To understand such problems and explore potential solutions, it is important to develop advanced models. This is particularly relevant for modern interconnects (especially vias) with complex structures with non- trivial current paths. In this dissertation, we develop a comprehensive physics-based interconnect models to capture surface and grain boundary scattering. We further analyze the circuit implications of 2D transition metal dichalcogenide (TMD)-augmented interconnects, which show potential in mitigating some of the scalability concerns of state-of-the-art interconnects. First, we propose a 2D spatially resolved model for surface scattering in rectangular interconnects based on the Fuchs-Sondheimer (FS) theory. The proposed spatially resolved FS (SRFS) model offers both spatial dependence and explicit relation of conductivity to physical parameters. We also couple the SRFS model with grain boundary scattering based on the Mayadas−Shatzkes (MS) theory. The SRFS-MS model is exact for diffusive surface scattering and offers a good approximation for elastic surface scattering. Furthermore, we develop a circuit-compatible version of the SRFS-MS model and show a close match with the physical SRFS-MS model (error < 0.7%). Moreover, we integrate temperature dependency, confirming that surface scattering has a negligible temperature-dependence. Second, we analyze the circuit implications of 2D TMD augmented interconnects and show the effective clock frequency of an AES circuit is boosted by 2%-32%. We also establish that the vertical resistivity of the TMD material must be below 22 kΩ-nm to obtain performance benefits over state-of-the-art interconnects in the worst-case process-temperature corner.</p>

<p dir="ltr">This thesis explores the thermodynamics and mechanics of reaction-diffusion interfaces in solid materials, focusing on configurational forces for bulks and surfaces, which are essential in understanding phenomena like electromigration, phase separation, and void evolution. The work is divided into four themes: bulk and surface configurational mechanics, electromigration in solder joints, and solid mixture theory. The thesis develops theories based on continuum mechanics and configurational forces, deriving Eshelby stress tensors and balance laws for interfaces. Experimental work on electromigration in SnBi solder joints is used to validate the theory. The research contributes to advancing the understanding of solid-state diffusion and phase evolution in engineering materials.</p>