Scope and contents: The static and dynamic electrical characteristics of silicon n-channel MOS FETs are studied down to cryogenic temperatures. Particular emphasis is directed towards the effect of interface states on the temperature dependence of both the pinch-off voltage and 1/f noise. / No abstract included. / Thesis / Master of Engineering (MEngr)

Numerical simulations of current-voltage characteristics of nanowire CdS/CdTe solar cells are performed as a function of temperature using SCAPS-1D. This research compares the experimental current-voltage (I-V) characteristics with the numerical (I-V) simulations obtained from SCAPS-1D at various temperatures. Various device parameters were studied which can affect the efficiency of the nanowire-CdS/CdTe solar cell. It was observed that the present simulated model explains the important effects of these solar cell devices, such as the crossover and the rollover effect. It was shown that the removal of defect in i-SnO2 is responsible for producing the crossover effect. In the past, the rollover effect has been explained by using back to back diode model in the literature. In this work, simulations were performed in order to validate this theory. At the back electrode, the majority carrier barrier height was varied from 0.4 to 0.5 eV, the curve corresponding to the 0.5 eV barrier showed a strong rollover effect, while this effect disappeared when the barrier was reduced to 0.4 eV. Thus, it was shown that the change of barrier height at the contact is a critical parameter in the rollover effect.

L'intégration de diélectriques High-k dans les empilements de grille des transistors a fait naître des problèmes de fiabilité complexes. A cela vient s'ajouter, en vue des technologies sub-32nm planaires, de nouvelles problématiques liées à l'utilisation de substrats silicium sur isolant complètement désertés FDSOI. En effet, l'intégration d'un oxyde enterré sous le film de silicium non seulement va modifier l'électrostatique de la structure mais aussi introduire une nouvelle interface Si/SiO2 sujette à d'éventuelles dégradations. Ce manuscrit présente différentes méthodes de caractérisation électrique ainsi que différentes études de fiabilité des dispositifs FDSOI intégrants des empilements High-κ/ grille métallique. Dans un premier temps, une étude complète du couplage électrostatique dans des structures FDSOI est réalisée, permettant de mieux appréhender l'effet d'une tension en face arrière sur les caractéristiques électriques des dispositifs. Différentes méthodes de caractérisation des pièges d'interface sont ensuite présentées et adaptées, quand cela est possible, au cas spécifique du FDSOI, où les défauts entre le film de silicium et l'oxyde enterré doivent être pris en compte. Enfin, différentes études de fiabilité sont présentées, des phénomènes de PBTI et de NBTI sur des dispositifs à canaux longs aux phénomènes propres aux dispositifs de petite dimension, tels que l'impact des porteurs chauds dans des structures FDSOI à film ultra fins et les effets parasites d'augmentation de la tension de seuil lorsque les largeurs des transistors diminuent. / The integration of High-k dielectrics in recent CMOS technologies lead to new complex reliability issues. Furthermore new concerns appear with the use of fully depleted silicon on insulator (FDSOI) substrates for future sub-32nm planar technologies. Indeed, the integration of a buried oxide underneath the silicon film changes the electrostatic of the structure and create a new Si/SiO2 interface which may be degraded. This thesis presents different electrical characterization techniques and reliability studies on High-κ/metal gate FDSOI transistors. First, a complete electrostatic study of FDSOI structures is done allowing a better understanding of the effects of backgate biases. Different techniques to characterize interface traps are then presented and adapted to FDSOI devices, where traps at the silicon film/buried oxide interface must be considered. Finally, different reliability studies are presented; from NBTI and PBTI issues on long channel devices to specific concerns related to small gate length transistors such as hot carriers degradation on ultra-thin film FDSOI devices and threshold voltage increase with gate width scaling.

No description available.

De nombreuses applications industrielles spécifiques dans les secteurs tels que l’automobile, le médical et le spatial, requièrent un très haut niveau de fiabilité. Dans ce contexte, cette thèse traite de l’étude de la fiabilité des mémoires non-volatiles à grille flottante de type NOR Flash. Après une introduction mêlant l’état de l’art des mémoires non volatiles et la caractérisation électrique des mémoires Flash, une étude sur l’effet des signaux de polarisation a été menée. Un modèle a été développé afin de modéliser la cinétique de la tension de seuil durant un effacement. L’effet de la rampe d’effacement a été montré sur les cinétiques mais aussi sur l’endurance. Une étude sur la durée de vie de l’oxyde tunnel a ensuite montré l’importance de l’utilisation d’un stress dynamique. Nous avons caractérisé cette dépendance en fonction du rapport cyclique et du champ électrique appliqué. Enfin l’endurance de la cellule mémoire Flash a été étudiée et les effets de la relaxation durant le cyclage ont été analysés. / Many specific applications used in automotive, medical and spatial activity domains, require a high reliability level. In this context, this thesis focuses on the study of floating gate non-volatiles memories reliability more precisely in NOR Flash architecture. After an introduction mixing the state of art of non-volatiles memories and the electrical characterization of Flash memories, a study on the polarization signals effect has been led. A model has been developed in order to model the threshold voltage kinetic during an erase operation. The erasing ramp effect has been shown on kinetics and also on cycling. Then, a study on the tunnel oxide lifetime has shown the importance of relaxation during stress. This dependence has been characterized as a function of duty cycle and the electric field applied. Finally, Flash memory cell endurance has been explored and the relaxation effects during the cycling has been analyzed.

Complex oxides are an intriguing field of solid-state research, as they can exhibit a wide variety of functional properties, such as ferroelasticity, ferroelectricity, ferro- and antiferromagnetism or an even more complicated type of magnetic ordering, the combination or interaction of those ferroic properties (multiferroicity), high spin polarization, or high-temperature superconductivity. Thus they are prospective candidates for future materials in microelectronics. It is a matter of fact that the performance of such oxide-based devices depends mainly on transport properties, which in turn depend on the distribution and density of intrinsic or extrinsic electronic interface states across the device structure. The present thesis focuses on the identification and characterization of such electronic properties by two different photoassisted spectroscopy techniques: surface photovoltage spectroscopy and photoelectron spectroscopy. This work especially deals with perovskite oxides, namely with the model perovskite strontium titanate (SrTiO3) as a substrate and three differently doped lanthanum manganite thin films (10-15 nm thickness) grown by pulsed laser deposition (PLD) on the SrTiO3 substrate(La0.7Sr0.3MnO3, La0.7Ca0.3MnO3, La0.7Ce0.3MnO3). The first part aims at the identification of electronic surface and interface states at the free SrTiO3 surface as well as at the three different lanthanum manganite/SrTiO3 interfaces. For that purpose three different experimental realizations of the surface photovoltage spectroscopy technique were implemented and employed: photoelectron spectroscopy under additional optical excitation, the capacitive detection of the photoinduced displacement current in a parallel-plate capacitor geometry under modulated optical excitation, and the classical Kelvin probe technique. The methods are evaluated comparatively with respect to their suitability to analyze the given oxidic interfaces. The main result of this first part is a map of the energetic positions and relaxation time constants of the surface states at the SrTiO3 surface as well as of the interface states at the lanthanum manganite/SrTiO3 interfaces within the SrTiO3 bandgap. The interface states were classified into film- and substrate-induced states and it could be demonstrated that an appropriate annealing procedure can dramatically decrease their densities. The second part tackles the problem of the manganese valence and the doping type of di- and tetravalent-ion-doped LaMnO3. The question whether the insulating parent compound LaMnO3 becomes an electron-doped semiconductor after doping with tetravalent cations such as Ce4+ - which would be in analogy to the well-established hole doping after partial substitution of La3+ by divalent cations such as Sr2+ or Ca2+ - has been discussed controversially in the literature so far. Due to the physics of the manganite crystal lattice the question can also be formulated in a different way: Can part of the manganese ions be driven from the Mn3+ state towards the Mn2+ state without any crystal instabilities or phase separation phenomena? In order to contribute to the clarification of this question, an extensive X-ray- and UV-photoelectron spectroscopy (XPS/UPS) investigation was performed. The three differently doped lanthanum manganite thin films were comparatively studied considering the exchange splitting of the Mn 3s core level line, which is a linear function of the Mn valence, as measured by XPS and the work function as extracted from UPS. All measurements were performed at different states of deoxygenation after heating in ultrahigh vacuum and reoxidation after heating in a pure oxygen atmosphere. Strong evidence for electron doping of the La0.7Ce0.3MnO3 film after deoxygenation was found. Furthermore, the reversible tunability of the Mn valence by variation of the oxygen content could be demonstrated for both tetravalent- and divalent-ion-doped lanthanum manganite films. / Oxidische Komplexverbindungen können eine Vielzahl an funktionellen Eigenschaften, wie z.B. Ferroelastizität, Ferroelektrizität, Ferro- und Antiferromagnetismus sowie kompliziertere magnetische Ordnungen, die Kombination und Interaktion solcher ferroischer Eigenschaften (Multiferroizität), hohe Spinpolarisation oder Hochtemperatursupraleitung aufweisen und gelten daher als aussichtsreiche Materialien für die zukünftige Mikroelektronik. Entscheidend für die Funktionsfähigkeit oxidischer Bauelemente sind deren elektronische Transporteigenschaften, die in äußerst sensibler Weise von der Verteilung und Dichte von ex- oder intrinsischen elektronischen Defektzuständen an Grenz- und Oberflächen innerhalb der Bauelementstruktur abhängen. Die vorliegende Arbeit beschäftigt sich mit der Spektroskopie solcher elektronischer Eigenschaften mittels photonenbasierter Methoden. Im Fokus stehen dabei perowskitische Oxide , speziell das Modellperowskit Strontiumtitanat (SrTiO3) als Substrat und darauf mittels gepulster Laserdeposition (PLD) abgeschiedene dünne Filme (10-15 nm Dicke) dotierter Lanthanmanganate (La0.7Sr0.3MnO, La0.7Ca0.3MnO3, La0.7Ce0.3MnO3). Im Rahmen einer halbleiterphysikalischen Interpretation widmet sich der erste Teilder Identifikation elektronischer Ober- und Grenzflächenzustände an der SrTiO3-Oberfläche sowie an verschiedenen Lanthanmanganat/SrTiO3-Grenzflächen mittels dreier unterschiedlicher experimenteller Methoden zur Vermessung der Oberflächenphotospannung: der Photoelektronenspektroskopie unter zusätzlicher optischer Anregung, einer kapazitiven Detektionsmethode in Plattenkondensatorgeometrie unter modulierter optischer Anregung und der optischen Kelvin-Sonde. Neben einem auf die bei oxidischen Ober- und Grenzflächen auftretenden besonderen Herausforderungen zugeschnittenen Methodenvergleich werden Grenzflächenzustände bezüglich ihrer energetischen Position in der Bandlücke des SrTiO3 und ihres Relaxationsverhaltens analysiert, als substrat- oder filminduziert klassifiziert, und die Verringerung ihrer Dichte nach geeigneter Ausheilprozedur wird nachgewiesen. Der zweite Teil der Arbeit befasst sich mit der in der Literatur bisher kontrovers diskutierten Frage, ob sich die isolierende Stammverbindung LaMnO3 durch Dotierung mit tetravalenten Kationen, wie z.B. Ce4+, in einen elektronendotierten Halbleiter verwandeln lässt - analog zur Herstellung lochdotierter Lanthanmanganate durch Dotierung mit divalenten Kationen, wie z.B. Sr2+ oder Ca2+. Die Frage ist äquivalent zur Betrachtung, ob unter Beibehaltung der Stabilität des Kristallgitters ein Teil der Manganionen vom Mn3+-Zustand in den Mn2+-Zustand übergehen kann. Um einen Beitrag zur Klärung dieses Problems zu leisten, wurden als elektronisch sensitive Methoden die Röntgen- und UV-Photoelektronenspektroskopie (XPS/UPS) gewählt. Die oben genannten Lanthanmanganatfilme wurden dazu hinsichtlich der Austauschaufspaltung der Mangan-3s-Linie im XP-Spektrum, die in linearer Weise von der Manganvalenz abhängt, und der anhand der Breite des UP-Spektrums ermittelten Austrittsarbeit jeweils nach Reinigung der Oberfläche im Ultrahochvakuum (UHV) vergleichend untersucht. Die Messungen wurden nach unterschiedlich starker Desoxidation durch Heizen im UHV und Reoxidierung durch Heizen in Sauerstoffatmosphäre durchgeführt. Es konnte nachgewiesen werden, dass eine Elektronendotierung des La0.7Ce0.3MnO3-Films bei geeigneter Einstellung des Sauerstoffgehalts tatsächlich möglich ist. Außerdem wurde gezeigt, dass sich sowohl in di- als auch in tetravalent dotierten Lanthanmanganatfilmen die Manganvalenz und damit der Dotierungstyp reversibel durchstimmen lässt.

La substitution du canal de silicium par un semi-conducteur III-V est une des voies envisagées pour accroitre la mobilité des électrons dans les transistors n-MOSFET et ainsi réduire la consommation des circuits. Afin de réduire les coûts et de profiter des plateformes industrielles de la microélectronique, les transistors III-V doivent être réalisés sur des substrats de silicium. Cependant, la différence de paramètre de maille entre le Si et les couches III-V induit de nombreux défauts cristallins dans le canal du transistor, diminuant la mobilité des porteurs. L’objectif de cette thèse est la réalisation de transistors à canal III-V sur substrat de silicium au sein de la plateforme microélectronique du CEA Leti. Dans le cadre de ces travaux, deux filières technologiques d’intégration ont été développées pour la réalisation de transistors tri-gate à base d’In0,53Ga0,47As sur substrat de silicium : par un collage moléculaire d’une couche d’InGaAs sur InP et par une épitaxie directe de la couche d’InGaAs sur substrat Si. Les différentes étapes technologiques spécifiques à l’InGaAs ont été mises au point au cours de ces travaux, en prenant en compte les contraintes de contamination des équipements. Le traitement de surface de l’InGaAs et le dépôt du diélectrique de grille à haute permittivité (type high-k) par ALD ont été particulièrement étudiés afin de réduire la quantité d’états d’interface (Dit) et d’optimiser l’EOT. Pour cela, des analyses XPS et des mesures électriques C(V) de capacités MOS ont été réalisées à l’échelle d’un substrat de 300mm de diamètre. / The replacement of the silicon channel by III-V materials is investigated to increase the electron mobility in the channel and reduce the power consumption. In order to decrease the cost and to take advantage of the microelectronic silicon platform, III-V transistors must be built on Silicon substrates. However, the lattice parameter mismatch between Silicon and the III-V layers leads to a high defects density in the channel and reduces the carrier mobility. This thesis aims to realize III-V transistors on silicon substrate in the CEA-Leti microelectronic clean room. In the frame of this PhD, two integration process are elaborated to realize In0,53Ga0,47As tri-gate transistors on silicon: the molecular bonding of an InGaAs layer grown on a InP substrate, and the direct epitaxy of InGaAs on a silicon substrate. The fabrication steps for InGaAs transistors were developed, taking into account the clean room contamination restriction. InGaAs surface treatment and high-permittivity dielectric deposition by ALD are studied in order to reduce the density of interface states (Dit) and to optimize the EOT. XPS analysis and C(V) measurement are performed at the scale of a 300mm Silicon substrate.

O carbeto de silício (SiC) apresenta várias propriedades extremamente interessantes para a fabricação de dispositivos eletrônicos submetidos a condições extremas como alta temperatura (300 a 600 °C), alta frequência e alta potência. Além disso, é o único semicondutor composto que, reagindo com o oxigênio, forma um óxido isolante estável, o SiO2. No entanto, as propriedades elétricas de estruturas de SiO2/SiC são degradadas pela alta concentração de estados eletricamente ativos na interface dielétrico/semicondutor. Tal característica representa uma barreira para a fabricação de dispositivos baseados nesse material. Nesta tese foram comparadas e analisadas as propriedades de estruturas SiO2/4H-SiC obtidas por diferentes processos de oxidação térmica. As estruturas resultantes foram caracterizadas por medidas de corrente-tensão, capacitância-tensão e condutância ac de alta frequência, espectroscopia de fotoelétrons induzidos por raios-X, análise por reação nuclear e microscopia de força atômica. O uso dessas técnicas analíticas visou a correlacionar o comportamento elétrico das estruturas obtidas com suas propriedades físico-químicas como, por exemplo, composição e estrutura química do óxido formado. Os resultados evidenciam diferenças específicas entre os ambientes de oxidação e temperaturas aos quais as amostras foram submetidas, com uma forte distinção entre 4H-SiC tipo-n e tipo-p. Em geral, amostras do substrato tipo-n apresentaram menores quantidades de defeitos na interface SiO2/SiC em comparação com as do tipo-p. Foram identificados comportamentos relacionados a defeitos no óxido, próximos à interface, responsáveis pela captura de portadores majoritários provenientes do semicondutor. Ficou evidente que alguns ambientes e temperaturas de oxidação beneficiam a interface em detrimento da qualidade do filme de óxido e vice-versa. Uma atmosfera de oxidação alternativa, utilizando H2O2 como agente oxidante, foi proposta. Tal processo mostrou-se eficaz na redução da quantidade de estados eletricamente ativos na interface em estruturas tipo-n através da conversão de compostos carbonados em SiO2 no filme dielétrico formado. / Silicon carbide (SiC) presents many advantageous properties for electronic devices designed to work under extreme conditions such as high-temperature (300 ~ 600 °C), high-frequency, and high-power. In addition, the formation of an insulating oxide layer (SiO2) by thermal oxidation is an attractive property for the microelectronics industry. Nevertheless, large densities of interface states at the SiO2/SiC interface degrade electrical properties of the resulting structure. Such states are responsible for undesirable effects which hamper the development of SiC-based devices. In this thesis, the properties of SiO2/4H-SiC structures obtained by distinct oxidation processes where analyzed and compared. The resulting structures where characterized by currentvoltage, high-frequency capacitance-voltage and ac conductance, X-ray photoelectron spectroscopy, nuclear reaction analysis, and atomic force microscopy. Such techniques were employed in order to correlate electrical and physico-chemical properties of the formed structures like composition and chemical bonding of the oxide layer. Results evidence differences among samples prepared under several oxidation atmospheres and temperatures, with a strong distinction among n- and p-type 4H-SiC. Overall, p-type samples presented larger values of interface states densities in comparison with their ntype counterparts. Near-interface traps in the oxide layer, responsible for capture of majority carriers from the semiconductor substrate, were identified. We could evidence that some oxidation conditions improve the bulk properties of the oxide layer, at the same time that they degrade the SiO2/SiC interface quality, and vice versa. An alternative oxidation process using H2O2 as oxidizing agent was proposed. Such process has shown to reduce the amount of electrically active defects at the interface in n-type samples by converting carbonaceous compounds in SiO2 in the formed dielectric layer.

O carbeto de silício (SiC) apresenta várias propriedades extremamente interessantes para a fabricação de dispositivos eletrônicos submetidos a condições extremas como alta temperatura (300 a 600 °C), alta frequência e alta potência. Além disso, é o único semicondutor composto que, reagindo com o oxigênio, forma um óxido isolante estável, o SiO2. No entanto, as propriedades elétricas de estruturas de SiO2/SiC são degradadas pela alta concentração de estados eletricamente ativos na interface dielétrico/semicondutor. Tal característica representa uma barreira para a fabricação de dispositivos baseados nesse material. Nesta tese foram comparadas e analisadas as propriedades de estruturas SiO2/4H-SiC obtidas por diferentes processos de oxidação térmica. As estruturas resultantes foram caracterizadas por medidas de corrente-tensão, capacitância-tensão e condutância ac de alta frequência, espectroscopia de fotoelétrons induzidos por raios-X, análise por reação nuclear e microscopia de força atômica. O uso dessas técnicas analíticas visou a correlacionar o comportamento elétrico das estruturas obtidas com suas propriedades físico-químicas como, por exemplo, composição e estrutura química do óxido formado. Os resultados evidenciam diferenças específicas entre os ambientes de oxidação e temperaturas aos quais as amostras foram submetidas, com uma forte distinção entre 4H-SiC tipo-n e tipo-p. Em geral, amostras do substrato tipo-n apresentaram menores quantidades de defeitos na interface SiO2/SiC em comparação com as do tipo-p. Foram identificados comportamentos relacionados a defeitos no óxido, próximos à interface, responsáveis pela captura de portadores majoritários provenientes do semicondutor. Ficou evidente que alguns ambientes e temperaturas de oxidação beneficiam a interface em detrimento da qualidade do filme de óxido e vice-versa. Uma atmosfera de oxidação alternativa, utilizando H2O2 como agente oxidante, foi proposta. Tal processo mostrou-se eficaz na redução da quantidade de estados eletricamente ativos na interface em estruturas tipo-n através da conversão de compostos carbonados em SiO2 no filme dielétrico formado. / Silicon carbide (SiC) presents many advantageous properties for electronic devices designed to work under extreme conditions such as high-temperature (300 ~ 600 °C), high-frequency, and high-power. In addition, the formation of an insulating oxide layer (SiO2) by thermal oxidation is an attractive property for the microelectronics industry. Nevertheless, large densities of interface states at the SiO2/SiC interface degrade electrical properties of the resulting structure. Such states are responsible for undesirable effects which hamper the development of SiC-based devices. In this thesis, the properties of SiO2/4H-SiC structures obtained by distinct oxidation processes where analyzed and compared. The resulting structures where characterized by currentvoltage, high-frequency capacitance-voltage and ac conductance, X-ray photoelectron spectroscopy, nuclear reaction analysis, and atomic force microscopy. Such techniques were employed in order to correlate electrical and physico-chemical properties of the formed structures like composition and chemical bonding of the oxide layer. Results evidence differences among samples prepared under several oxidation atmospheres and temperatures, with a strong distinction among n- and p-type 4H-SiC. Overall, p-type samples presented larger values of interface states densities in comparison with their ntype counterparts. Near-interface traps in the oxide layer, responsible for capture of majority carriers from the semiconductor substrate, were identified. We could evidence that some oxidation conditions improve the bulk properties of the oxide layer, at the same time that they degrade the SiO2/SiC interface quality, and vice versa. An alternative oxidation process using H2O2 as oxidizing agent was proposed. Such process has shown to reduce the amount of electrically active defects at the interface in n-type samples by converting carbonaceous compounds in SiO2 in the formed dielectric layer.

O carbeto de silício (SiC) apresenta várias propriedades extremamente interessantes para a fabricação de dispositivos eletrônicos submetidos a condições extremas como alta temperatura (300 a 600 °C), alta frequência e alta potência. Além disso, é o único semicondutor composto que, reagindo com o oxigênio, forma um óxido isolante estável, o SiO2. No entanto, as propriedades elétricas de estruturas de SiO2/SiC são degradadas pela alta concentração de estados eletricamente ativos na interface dielétrico/semicondutor. Tal característica representa uma barreira para a fabricação de dispositivos baseados nesse material. Nesta tese foram comparadas e analisadas as propriedades de estruturas SiO2/4H-SiC obtidas por diferentes processos de oxidação térmica. As estruturas resultantes foram caracterizadas por medidas de corrente-tensão, capacitância-tensão e condutância ac de alta frequência, espectroscopia de fotoelétrons induzidos por raios-X, análise por reação nuclear e microscopia de força atômica. O uso dessas técnicas analíticas visou a correlacionar o comportamento elétrico das estruturas obtidas com suas propriedades físico-químicas como, por exemplo, composição e estrutura química do óxido formado. Os resultados evidenciam diferenças específicas entre os ambientes de oxidação e temperaturas aos quais as amostras foram submetidas, com uma forte distinção entre 4H-SiC tipo-n e tipo-p. Em geral, amostras do substrato tipo-n apresentaram menores quantidades de defeitos na interface SiO2/SiC em comparação com as do tipo-p. Foram identificados comportamentos relacionados a defeitos no óxido, próximos à interface, responsáveis pela captura de portadores majoritários provenientes do semicondutor. Ficou evidente que alguns ambientes e temperaturas de oxidação beneficiam a interface em detrimento da qualidade do filme de óxido e vice-versa. Uma atmosfera de oxidação alternativa, utilizando H2O2 como agente oxidante, foi proposta. Tal processo mostrou-se eficaz na redução da quantidade de estados eletricamente ativos na interface em estruturas tipo-n através da conversão de compostos carbonados em SiO2 no filme dielétrico formado. / Silicon carbide (SiC) presents many advantageous properties for electronic devices designed to work under extreme conditions such as high-temperature (300 ~ 600 °C), high-frequency, and high-power. In addition, the formation of an insulating oxide layer (SiO2) by thermal oxidation is an attractive property for the microelectronics industry. Nevertheless, large densities of interface states at the SiO2/SiC interface degrade electrical properties of the resulting structure. Such states are responsible for undesirable effects which hamper the development of SiC-based devices. In this thesis, the properties of SiO2/4H-SiC structures obtained by distinct oxidation processes where analyzed and compared. The resulting structures where characterized by currentvoltage, high-frequency capacitance-voltage and ac conductance, X-ray photoelectron spectroscopy, nuclear reaction analysis, and atomic force microscopy. Such techniques were employed in order to correlate electrical and physico-chemical properties of the formed structures like composition and chemical bonding of the oxide layer. Results evidence differences among samples prepared under several oxidation atmospheres and temperatures, with a strong distinction among n- and p-type 4H-SiC. Overall, p-type samples presented larger values of interface states densities in comparison with their ntype counterparts. Near-interface traps in the oxide layer, responsible for capture of majority carriers from the semiconductor substrate, were identified. We could evidence that some oxidation conditions improve the bulk properties of the oxide layer, at the same time that they degrade the SiO2/SiC interface quality, and vice versa. An alternative oxidation process using H2O2 as oxidizing agent was proposed. Such process has shown to reduce the amount of electrically active defects at the interface in n-type samples by converting carbonaceous compounds in SiO2 in the formed dielectric layer.