Cette thèse adresse le sujet de la génération de suites binaires aléatoires dans les circuits logiques programmables FPGA et plus particulièrement les suites dont l’origine aléatoire est de nature physique et non algorithmique. De telles suites trouvent une utilisation abondante dans la plupart des protocoles cryptographiques. Un état de l’art portant sur les différentes méthodes de génération de vrai aléa dans les circuits logiques programmables est présenté sous forme d’analyse critique d’articles scientifiques. Une synthèse des différentes tendances dans l’extraction et la génération d’aléa est également présentée. Une campagne d’expériences et de mesures est présentée visant à caractériser les différentes sources de signaux aléatoires disponibles à l’intérieur du FPGA. Des phénomènes intéressants tel le verrouillage de plusieurs oscillateurs en anneau, la dépendance de la source d’aléa vis-à-vis de la logique environnante et la méthodologie de mesure du jitter sont analysés. Plusieurs méthodes nouvelles de génération de suites binaires aléatoires sont décrites. Finalement une méthodologie nouvelle de simulation en VHDL de générateurs complets ainsi qu’un modèle mathématique d’un oscillateur en anneau en tant que source d’aléa sont présentés / This thesis addresses the topic of the generation of random binary streams in FPGA and especially random sequences whose origin is physical and not algorithmic. Such sequences find abundant use in most cryptographic protocols. A state of the art regarding the various methods of generating true randomness in programmable logic is presented as a critical analysis of scientific articles. A synthesis of different trends in the extraction and generation of true randomness is presented. A campaign of experiments and measurements is presented to characterize the different sources of random signals available inside the FPGA. Interesting phenomena such as the locking of several ring oscillators and the sensibility of the source of randomness depending to the surrounding logic activity are reported. Several new methods for generating random binary sequences are described and analyzed. Finally a new simulation methodology in VHDL and a mathematical model of a ring oscillator as a source of randomness for TRNG are presented

Mobile cloud gaming (MCG) is an emerging concept which aims to deliver video games on-demand to users with the use of cloud technologies. Cloud technology allows the offloading of computation from a less powerful user device or thin client to more robust cloud servers to minimize power consumption and provide additional cloud services such as storage. MCG is therefore very helpful that can reduce the costs of expensive hardware, but the challenge is that it requires a high Quality of Service (QoS) in order to stream and play the games where the users have a high Quality of Experience (QoE). The goal of the study is to investigate how users' QoE is affected by network conditions while playing MCG and compare the results from a previous study. A testbed was made in order to conduct subjective tests where users are going to play Counter Strike: Global Offensive (CS: GO) on a smartphone using Steam Remote Play. The testbed consists of a router, tablet, smartphone, headset, Xbox controller, USB-C multi-port adapter and four different PC's. Participants on campus, both students and non-students, were invited to participate in the experiment. A total of 24 participants completed the tests; however, results from two participants were excluded due to software issues. There were 23 network conditions that was tested for each user and included factors such as round-trip time (RTT), packet losses, bursty jitter, random jitter or combinations of different factors. A multi-platform tool, ALTRUIST, was used to control the applications and facilitate the data collection from the devices and NetEm changed the network conditions. The results showed that the network condition [bj(rtt200i15)] had the highest mean opinion score (MOS) of the QoE of 4.5 for the users with 200 milliseconds of bursty jitter every 15 seconds. The worst network condition tested with the lowest QoE rating of 1.4 was network condition [rtt25pl12] that had 25 milliseconds of RTT and 12% packet losses. There were differences between the male and female participants where the MOS of the QoE results was significantly higher with up to 1.5 MOS QoE rating differences for the females compared to the males in network conditions with RTT with packet losses. However, the sample size was low with only 5 female participants compared to 18 male participants. The MOS of the QoE results separating play time under 10 hours per week and 10 or more hours per week showed no significant changes, where the largest QoE rating difference was 0.5 points. Network condition [rtt25pl12] and [rtt2pl35] had the largest differences in the MOS QoE ratings compared to the previous study, while both was not compared to the same corresponding network condition. The largest difference comparing the same network condition to the previous study was network condition [bj(rtt200i15)] with a difference of 1.1 points higher in the MOS QoE rating.

Les générateurs de nombres véritablement aléatoires (TRNG) sont des composants cruciaux dans certaines applications cryptographiques sensibles (génération de clés de chiffrement, génération de signatures DSA, etc). Comme il s’agit de composants très bas-niveau, une faille dans le TRNG peut remettre en question la sécurité de tout le système cryptographique qui l’exploite. Alors que beaucoup de principes de TRNG existent dans la littérature, peu de travaux analysent rigoureusement ces architectures en termes de sécurité. L’objectif de cette thèse était d’étudier les avantages des techniques de conception asynchrone pour la conception de générateurs de nombres véritablement aléatoires (TRNG) sûrs et robustes. Nous nous sommes en particulier intéressés à des oscillateurs numériques appelés anneaux auto-séquencés. Ceux-ci exploitent un protocole de requêtes et acquittements pour séquencer les données qui y circulent. En exploitant les propriétés uniques de ces anneaux, nous proposons un nouveau principe de TRNG, avec une étude théorique détaillée sur son fonctionnement, et une évaluation du cœur du générateur dans des cibles ASIC et FPGA. Nous montrons que ce nouveau principe permet non seulement de générer des suites aléatoires de très bonne qualité et avec un très haut débit (>100 Mbit/s), mais il permet aussi une modélisation réaliste de l’entropie des bits de sortie (celle-ci peut être réglée grâce aux paramètres de l’extracteur). Ce travail propose également une méthodologie complète pour concevoir ce générateur, pour le dimensionner en fonction du niveau de bruit dans le circuit, et pour le sécuriser face aux attaques et défaillances / True Random Number Generators (TRNG) are ubiquitous in many critical cryptographic applications (key generation, DSA signatures, etc). While many TRNG designs exist in literature, only a few of them deal with security aspects, which is surprising considering that they are low-level primitives in a cryptographic system (a weak TRNG can jeopardize a whole cryptographic system). The objective of this thesis was to study the advantages of asynchronous design techniques in order to build true random number generators that are secure and robust. We especially focused on digital oscillators called self-timed rings (STR), which use a handshake request and acknowledgement protocol to organize the propagation of data. Using some of the unique properties of STRs, we propose a new TRNG principle, with a detailed theoretical study of its behavior, and an evaluation of the TRNG core in ASICs and FPGAs. We demonstrate that this new principle allows to generate high quality random bit sequences with a very high throughput (> 100 Mbit/s). Moreover, it enables a realistic estimation for the entropy per output bit (this entropy level can be tuned using the entropy extractor parameters). We also present a complete methodology to design the TRNG, to properly set up the architecture with regards to the level of noise in the circuit, and to secure it against attacks and failures

Considere um sistema de comunicação em que um equipamento transmissor envia pacotes de dados, de tamanho fixo e a uma taxa uniforme, a um equipamento receptor. Considere também que esses equipamentos estejam conectados por uma rede de comutação de pacotes, que introduz um atraso aleatório a cada pacote que trafega na rede. Nesta tese, é proposto um modelo de recuperação adaptativa de relógio capaz de sincronizar as frequências e as fases desses dispositivos, dentro de certos limites especificados de precisão. Esse método para atingir sincronização de frequência e de fase é baseado em medições dos tempos de chegada dos pacotes ao receptor, que são usados para controlar a dinâmica de um phase-locked loop (PLL) digital. O desempenho desse modelo é avaliado através de simulações numéricas realizadas considerando valores de parâmetros realistas. Os resultados indicam que esse esquema tem potencial para ser usado em aplicações práticas. / Consider a communication system in which a transmitter equipment sends fixed-size packets of data at a uniform rate to a receiver equipment. Consider also that these equipments are connected by a packet-switched network, which introduces a random delay to each packet. In this thesis, we propose an adaptive clock recovery scheme capable of synchronizing the frequencies and the phases of these devices, within specified limits of precision. This scheme for achieving frequency and phase synchronization is based on measurements of the packet arrival times at the receiver, which are used to control the dynamics of a digital phase-locked loop (PLL). The scheme performance is evaluated via numerical simulations performed by using realistic parameter values. The results suggest that this scheme has potential to be used in practical applications.

Les caméras à balayage de fente sont les instruments de détection directe de la lumière les plus précis en termes de résolution temporelle. Ces instruments sont capables de capturer des évènements de l’ordre de la picoseconde à un taux de répétition d’une centaine de mégahertz. Cependant, les performances de la caméra sont limitées par de nombreux phénomènes propres au fonctionnement de cette dernière mais aussi au système l’implémentant. Plusieurs effets dégradant la résolution temporelle sont étudiés. Le premier axe exploré concerne la synchronisation de la caméra avec l’évènement lumineux capturé. Cette investigation débouche sur le développement d’un discriminateur à fraction constante permettant de déclencher la caméra avec un jitter inférieur à 200 fs RMS. Une autre étude présente l’impact qu’ont le bruit d’amplitude et le bruit de phase des lasers usuellement utilisés avec la caméra sur sa synchronisation. Enfin une analyse des phénomènes intrinsèques à la photocathode de la caméra permet d’évaluer la variation du temps de transit des électrons dans celle-ci. / Streak cameras are the direct light detection instruments that are the best in terms of temporal resolution. Those instruments can capture picosecond light events at a hundred megahertz repetition rate. However their characteristics are limited by various phenomena specific to the camera and the implementing system. Several effects that affect the temporal resolution are studied. The first examined line deals with the synchronization of the camera with the studied light event. This inquiry led to the design of a constant fraction discriminator allowing a sub 200 fs RMS jitter triggering. Another study shows the impact of the usually used laser amplitude noise and phase noise on the system’s synchronization. Finally, an analysis of the camera’s photocathode intrinsic phenomena allows estimating the transit time variation of the electrons within the vacuum tube.

Considere um sistema de comunicação em que um equipamento transmissor envia pacotes de dados, de tamanho fixo e a uma taxa uniforme, a um equipamento receptor. Considere também que esses equipamentos estejam conectados por uma rede de comutação de pacotes, que introduz um atraso aleatório a cada pacote que trafega na rede. Nesta tese, é proposto um modelo de recuperação adaptativa de relógio capaz de sincronizar as frequências e as fases desses dispositivos, dentro de certos limites especificados de precisão. Esse método para atingir sincronização de frequência e de fase é baseado em medições dos tempos de chegada dos pacotes ao receptor, que são usados para controlar a dinâmica de um phase-locked loop (PLL) digital. O desempenho desse modelo é avaliado através de simulações numéricas realizadas considerando valores de parâmetros realistas. Os resultados indicam que esse esquema tem potencial para ser usado em aplicações práticas. / Consider a communication system in which a transmitter equipment sends fixed-size packets of data at a uniform rate to a receiver equipment. Consider also that these equipments are connected by a packet-switched network, which introduces a random delay to each packet. In this thesis, we propose an adaptive clock recovery scheme capable of synchronizing the frequencies and the phases of these devices, within specified limits of precision. This scheme for achieving frequency and phase synchronization is based on measurements of the packet arrival times at the receiver, which are used to control the dynamics of a digital phase-locked loop (PLL). The scheme performance is evaluated via numerical simulations performed by using realistic parameter values. The results suggest that this scheme has potential to be used in practical applications.

No description available.

Cette thèse porte sur l’étude de paramètres acoustiques dans parole fluente chez des locuteurs bègues (SB) et des non-bègues (SNB), tunisiens.Les paramètres acoustiques comparés entre SB et SNB incluent le temps d’établissement du voisement (ou V.O.T), la fréquence du fondamental (F0), des mesures du Jitter et du Shimmer, l’étendue et la direction de la transition du second formant (F2), et également les trois premiers formants (F1, F2 et F3) des trois voyelles /a, i, u/. Les résultats sont en accord avec les études antérieures en ce qui concerne le V.O.T, qui serait aussi plus long chez les bègues américains et français. Concernant les valeurs du F0, des différences significatives entre les deux groupes sont obtenues pour /u/. Les mesures du Jitter et du Shimmer ne montrent pas de différences significatives, contrairement aux résultats recueillis chez les bègues américains où la signification est obtenue pour les mesures du Shimmer. Enfin,en ce qui concerne l’étude des variations formantiques, il y a des tendances sans atteindre la signification pour F1, F2 et F3. Les mesures de F2 sont moins élevées chez les bègues avec quelques résultats significatifs obtenus pour les séquences du type C-u. Le triangle vocalique des trois voyelles /a i u/ chez les enfants bègues tunisiens n’est totalement centralisé contrairement aux triangles obtenus chez les locuteurs bègues français et américains, selon la littérature. / This thesis concerns the comparison of acoustic parameters in fluent speech in Tunisian stutterers’ speakers (SB) and non-stutterers (SNB), Tunisians.The acoustic parameters which are compared between SB and SNB include the Voice Onset Time (VOT), the fundamental frequency (F0), the measurements of jitter and shimmer, the scope and direction of the transition of the second formant (F2), and the first three formants (F1, F2 and F3) of the three vowels /a, i, u/. The results are consistent with previous studies regarding the V.O.T, which has been found also be longer for American and French stutterers. Concerning F0values, significant differences between the two groups are obtained for /u/. Measurements of jitter and shimmer show no significant differences, contrary to the results found from American concerning the shimmer. Finally, as regards the study of formant variations, there are tendencies without reaching significance for F1, F2 and F3. F2 values are lower in stutterers with significant results obtained for sequences of C-u. The vowel triangle of the three vowels /a, u, i/ in Tunisian children who stutter, is not centralized, unlike triangles obtained for French and American stuttering speakers, according to the literature.

Jitter requirements have become more stringent with higher speed serial communication links. Reducing jitter, with the main focus on reducing data dependant jitter (DDJ), is presented by employing adaptive finite impulse response (FIR) filter pre-emphasis. The adaptive FIR pre-emphasis is implemented in the IBM 7WL 0.18 µm SiGe BiCMOS process. SiGe heterojunction bipolar transistors (HBTs) provide high bandwidth, low noise devices which could reduce the total system jitter. The trade-offs between utilising metal oxide semiconductor (MOS) current mode logic (CML) and SiGe bipolar CML are also discussed in comparison with a very high fT (IBM 8HP process with fT = 200 GHz) process. A reduction in total system jitter can be achieved by keeping the sub-components of the system jitter constant while optimising the DDJ. High speed CML circuits have been employed to allow data rates in excess of 5 Gb/s to be transmitted whilst still maintaining an internal voltage swing of at least 300 mV. This allows the final FIR filter adaptation scheme to minimise the DDJ within 12.5 % of a unit interval, at a data rate of 5 Gb/s implementing 6 FIR pre-emphasis filter taps, for a worst case copper backplane channel (30" FR-4 channel). The implemented integrated circuit (IC) designed as part of the verification process takes up less than 1 mm2 of silicon real estate. In this dissertation, SPICE simulation results are presented, as well as the novel IC implementation of the proposed FIR filter adaptation technique as part of the hypothesis verification procedure. The implemented transmitter and receiver were tested for functionality, and showed the successful functional behaviour of all the implemented CML gates associated with the first filter tap. However, due to the slow charge and discharge rate of the pulse generation circuit in both the transmitter and receiver, only the main operational state of the transmitter could be experimentally validated. As a result of the adaptation scheme implemented, the contribution in this research lies in that a designer utilising such an IC can optimise the DDJ, reducing the total system jitter, and hence increasing the data fidelity with minimal effort. / Dissertation (MEng)--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

Master of Science / Department of Electrical and Computer Engineering / Andrew Rys / Clock and data recovery (CDR) circuits form the backbone of high speed receivers. These receivers are used in various applications such as chip to chip interconnects, optical communications and backplane routing. The received data in CDR circuits are potentially noisy and asynchronous, i.e. they are not accompanied by a clock. The CDR circuit has to generate a clock from the data and then retime the data. The CDR circuit that recovers the clock and retimes the data has to remove the jitter that is accumulated during its transport through channels due to inter symbol interference (ISI). There are stringent jitter specifications defined by various communication standards that must be addressed by CDR circuits. These make the design of CDR circuits more difficult for system designers as well the circuit designer. Many parameters have to be taken into consideration while designing a CDR circuit. The problem becomes even more interesting as there are various tradeoffs in the design. As speeds of communications increase, the maximum allowable jitter decreases. Jitter in CDR circuits arises due to a lot of factors and is also dependent on the method used for clock and data recovery. In CDR circuits that use phase locked loops to recover the clock and retime the data, jitter may be caused by the metastability of sequential elements used in phase detectors. Jitter is also caused by the phase noise of the VCO used in the PLL. In CDR circuits that use the delay locked loop to recover the clock and data, jitter may be caused by the metastability of sequential elements in phase detectors as well as the quality of reference clock that is used to re-time the data. Additional effects that can cause jitter in CDR circuits include the use of spread spectrum clocking, delta sigma noise shaping performance, etc. In this thesis a non-sequential linear phase detector has been proposed which does not use any sequential elements to avoid metastability issues in phase detectors. The output jitter in a CDR circuit that uses the proposed phase detector is measured and compared to a Hogge Phase Detector [5].