International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / In this paper, a small-sized low-noise integrated block downconverter (LNB) used for Ku-band direct reception from broadcasting satellites (DBS) is proposed. The operating frequency of the LNB is from 11.7 to 12.2GHz. The outlook dimension is 41 X 41 X 110mm^3. Measured results show that the average gain of the LNB is 57dB, and noise figures are less than 1.7dB. It has been found that clear TV pictures have been received using the LNB for the experiment of receiving the "BS-2b" (Japanese broadcasting satellite) at Harbin region, Heilongjiang Province, P. R. China.

This thesis is composed of three parts. The first part is devoted to introducing the various noise sources in transistors and their equivalent noise models. Based on the equivalent noise models, the theory of noise cancellation in a low-noise amplifier is derived in detail. The second part is to perform an experiment to validate the theory of low-noise amplifier using common-gate noise cancellation technique. By adjusting the transconductance of individual transistor, the simulated and measured noise figures are compared under different noise cancellation conditions. The third part is to design a low-noise amplifier RFIC using common-source noise cancellation technique for DVB-H applications. This RFIC was implemented in a TSMC 0.18£gm process and measured to show successful noise cancellation capability in a wide frequency range.

Design of the next generation (4G) systems is one of the most active and important area of research and development in wireless communications. The 2G and 3G technologies will still co-exist with the 4G for a certain period of time. Other applications such as wireless LAN (Local Area Network) and RFID are also widely used. As a result, there emerges a trend towards integrating multiple wireless functionalities into a single mobile device. Low noise amplifier (LNA), the most critical component of the receiver front-end, determines the sensitivity and noise figure of the receiver and is indispensable for the complete system. To satisfy the need for higher performance and diversity of wireless communication systems, three LNAs with different structures and techniques are proposed in the thesis based on the 4G applications. The first LNA is designed and optimized specifically for LTE applications, which could be easily added to the existing system to support different standards. In this cascode LNA, the nonlinearity coming from the common source (CS) and common gate (CG) stages are analyzed in detail, and a novel linear structure is proposed to enhance the linearity in a relatively wide bandwidth. The LNA has a bandwidth of 900MHz with the linearity of greater than 7.5dBm at the central frequency of 1.2GHz. Testing results show that the proposed structure effectively increases and maintains linearity of the LNA in a wide bandwidth. However, a broadband LNA that covers multiple frequency ranges appears more attractive due to system simplicity and low cost. The second design, a wideband LNA, is proposed to cover multiple wireless standards, such as LTE, RFID, GSM, and CDMA. A novel input-matching network is proposed to relax the tradeoff among noise figure and bandwidth. A high gain (>10dB) in a wide frequency range (1-3GHz) and a minimum NF of 2.5dB are achieved. The LNA consumes only 7mW on a 1.2V supply. The first and second LNAs are designed mainly for the LTE standard because it is the most widely used standard in the 4G communication systems. However, WiMAX, another 4G standard, is also being widely used in many applications. The third design targets on covering both the LTE and the WiMAX. An improved noise cancelling technique with gain enhancing structure is proposed in this design and the bandwidth is enlarged to 8GHz. In this frequency range, a maximum power gain of 14.5dB and a NF of 2.6-4.3dB are achieved. The core area of this LNA is 0.46x0.67mm2 and it consumes 17mW from a 1.2V supply. The three designs in the thesis work are proposed for the multi-standard applications based on the realization of the 4G technologies. The performance tradeoff among noise, linearity, and broadband impedance matching are explored and three new techniques are proposed for the tradeoff relaxation. The measurement results indicate the techniques effectively extend the bandwidth and suppress the increase of the NF and nonlinearity at high frequencies. The three proposed structures can be easily applied to the wideband and multi-standard LNA design.

The first part of this thesis studies the wire-bonding technology for use in an integrated design of transformer balun and RF front-end receiver, which is realized by IPD and CMOS technology, respectively. In this part, the RF front-end receiver and the balun were designed separately, and the bondwire model was established based on electromagnetic simulation. For the maximum power transfer and optimal noise performance, the input impedance between the CMOS RF front-end receiver and the IPD balun was conjugate-matched. The IPD balun, placed in front of the differential LNA of a direct-conversion receiver, is designed using the IPD technology, thereby reducing the insertion loss, and subsequently improving the noise figure of the CMOS receiver. The second part of this thesis uses a vertically coupled transformer balun with a primary coil made by IPD technology and a secondary coil made by CMOS technology. This balun has a low-loss advantage when integrated with a posterior differential LNA. Finally, the magnetic resonance coupling for use in signal transmission is studied and experimented on a printed circuit board.

Different wireless communication systems utilizing different standards and for multiple applications have penetrated the normal people's life, such as Cell phone, Wireless LAN, Bluetooth, Ultra wideband (UWB) and WiMAX systems. The wireless receiver normally serves as the primary part of the system, which heavily influences the system performance. This research concentrates on the designs of several important blocks of the receiver; multi-stage amplifier and low noise amplifier. Two novel multi-stage amplifier typologies are proposed to improve the bandwidth and reduce the silicon area for the application where a large capacitive load exists. They were designed using AMI 0.5 m µ CMOS technology. The simulation and measurement results show they have the best Figure-of-Merits (FOMs) in terms of small signal and large signal performances, with 4.6MHz and 9MHz bandwidth while consuming 0.38mW and 0.4mW power from a 2V power supply. Two Low Noise Amplifiers (LNAs) are proposed, with one designed for narrowband application and the other for UWB application. A noise reduction technique is proposed for the differential cascode Common Source LNA (CS-LNA), which reduces the LNA Noise Figure (NF), increases the LNA gain, and improves the LNA linearity. At the same time, a novel Common Gate LNA (CG-LNA) is proposed for UWB application, which has better linearity, lower power consumption, and reasonable noise performance. Finally a novel practical current injection built-in-test (BIT) technique is proposed for the RF Front-end circuits. If the off-chip component Lg and Rs values are well controlled, the proposed technique can estimate the voltage gain of the LNA with less than 1dB (8%) error.

The contents of this thesis is a realization of a low noise amplifier for the band from 137MHz to 138MHz and a antenna for the recieving of the signal from NOAA satellites. The proper function of the low niose amplifier is verified by Ansoft Desinger simulation and the proper function of the antenna is verified by HFSS simulation. Both devices are realizated like prototypes and their parametres are measured.

This thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the HCE phenomenon is one of the serious reliability issues in the aggressively scaled RF CMOS design, especially for long-term operation of these devices. The predicted degradation from simulation results can be used design reliable CMOS RF circuits.

Esta dissertação apresenta o projeto de um amplificador de baixo ruído (LNA) para aplicação em 2,4 GHz na tecnologia CMOS 0,35 µm. A metodologia baseia-se na obtenção das dimensões dos dispositivos do circuito considerando o consumo de potência e o desempenho em relação ao ruído. Os resultados mostram que a metodologia implementada é eficaz no projeto de um LNA quando se comparam os resultados obtidos nos cálculos com os resultados obtidos no simulador. A expressão de corrente que considera canal curto impõe maior precisão nos resultados, pois se aplica o ajuste de curva com a curva de corrente obtida pelo simulador. Isto permite maior precisão nos resultados dos cálculos de ruído. O fluxo do projeto baseia-se na implementação de dispositivos ideais obtidos de projeto com o propósito de fazer-se comparações dos resultados de cálculos com as simulações, então, usa-se dispositivos reais e ajusta-se o circuito para encontrar melhores desempenhos quanto às especificações. Os resultados mostram a necessidade de ajuste do circuito quando inserido o modelo do indutor para que se consiga desempenhos próximos dos obtidos inicialmente. Em seguida, realiza-se o layout do circuito e sua extração parasitária para fins de fabricação. Verifica-se que a metodologia apresentada é capaz de direcionar a um projeto de um LNA na tecnologia com resultados finais satisfatórios de ganho, ruído e consumo. Assim os resultados esperados são 14,66 dB de ganho, 1,9 dB de fator de ruído e 2,99 mA de consumo de corrente (9,87 mW em 3,3 V de alimentação) ambos no primeiro estágio. / This work presents the design of a low-noise amplifier (LNA) for application at 2.4 GHz using CMOS 0.35 µm technology. The methodology is based on obtaining the dimensions of the devices taking into account of power consumption and performance on noise. Results show that the implemented methodology is efficient in the design of LNAs when it compares results obtained by calculation and simulation. The expression of current that considers short-channel effects increases the precision of results because curve fitting is applied with the current of the simulator. This permits precision on the results of the noise calculation. The design-flow firstly bases on implementation of ideal devices obtained by design on purposes of doing comparisons between calculated and simulated results, then real devices is used and the circuit is fixed to find better performance regarding the specifications. The results showed the necessity of adjusts in the circuit when the inductor is inserted to reach a closer initial performance. Afterwards, the layout of the circuit and its parasitic extraction are worked out for purposes of fabrication. It is verified that this methodology is capable of directing to the design of LNAs using the proposed technology with satisfactory final results of gain, noise and power consumption. Therefore, the expected results are 14,66 dB of gain, 1,9 dB of noise figure, 2,99 mA of current consumption (9,87 mW within 3.3 V of supply voltage) both of them at first stage.

<p>In this master degree work, a digital attenuator and a low noise amplifier (LNA) have been designed and integrated with the RF front-end receiver for IEEE 802.11b Wireless LAN standard. Firstly, the 4-bit digitally controlled attenuator has been designed with theattenuation range of 50 to 80 dB and reflection coefficient less than -25 dB. Next, the single stage wide band low noise amplifier with voltage gain larger than 14 dB and noise figure below 4 dB has been designed to operate at frequency 2.4 GHz. Finally, the integration with a down-conversion mixer has been done and evaluated its performance.</p><p>The attenuator and low noise amplifier desired in this thesis have been implemented using standard CMOS 0.35µm technology and validated by the simulation tools Cadence Spectre-RF.</p>

In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components. Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach. The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.