In cities around the world, public water systems have increasingly come to be operated by private companies. Along with an internationally funded investment program to refurbish the dilapidated water infrastructure, private operations were tested also in Dar es Salaam, Tanzania. Only about a third of the households, however, are reached by the piped water system there; most households purchase water from those with pipe-connections or private boreholes. Thus, water distribution was informally privatized by way of water vending long before formal private sector participation began. This thesis explores individual and collective endeavors in water development, distribution, and access, along with the global and local influences that shaped the privatization exercise. With regard to the lease of Dar es Salaam’s water system, the institutional set-up has been found to mix the British and French models, having influenced the local situation through development assistance and conditionalities tied to loans. The institutional contradictions may have contributed to the conflictive cancellation of the lease arrangement. Due to the public utility company’s lack of operating capital and investment planning, infrastructure development has responded mainly to immediate individual demands, resulting in a spaghetti-like network and structural leakage. The long-standing under-performance and low coverage of the piped water system have forced many people to devise their own ways to access water. This thesis argues that the individually-devised artisan ways of water provisioning constitute the life-line of Dar es Salaam’s water system. Yet, they also undermine and divert resources away from the collectively-devised industrial form of piped water provision.

Semiconductor lasers based on gallium arsenide and relatedmaterials are widely used in applications such as opticalcommunication systems, sensing, compact disc players, distancemeasurement, etc. The performance of these lasers can beimproved using a buried heterostructure offering lateralcarrier and optical confinement. In particular, if theconfinement (burying) layer is implemented by epitaxialregrowth of an appropriate aluminium-free semi-insulating (SI)material, passivation of etched surfaces, reduced tendency tooxidation, low capacitance and integration feasibility areadditional advantages. The major impediment in the fabrication of GaAs/AlGaAsburied-heterostructure lasers is the spontaneous oxidation ofaluminium on the etched walls of the structure. Al-oxide actsas a mask and makes the regrowth process extremely challenging.In this work, a HCl gas-basedin-situcleaning technique is employed successfully toremove Al-oxide prior to regrowth of SI-GaInP:Fe and SI-GaAs:Fearound Al-containing laser mesas by Hydride Vapour PhaseEpitaxy. Excellent regrowth interfaces, without voids, areobtained, even around AlAs layers. Consequences of usinginadequate cleaning treatments are also presented. Regrowthmorphology aspects are discussed in terms of different growthmechanisms. Time-resolved photoluminescence characterisation indicates auniform Fe trap distribution throughout the regrown GaInP:Fe.Scanning capacitance microscopy measurements demonstrate thesemi-insulating nature of the regrown GaInP:Fe layer. Thepresence of EL2 defects in regrown GaAs:Fe makes more difficultthe interpretation of the characterisation results in the nearvicinity of the laser mesa. GaAs/AlGaAs buried-heterostructure lasers, both in-planelasers and vertical-cavity surface-emitting lasers, withGaInP:Fe as burying layer are demonstrated for the first time.The lasers exhibit good performance demonstrating thatSI-GaInP:Fe is an appropriate material to be used for thispurpose and the suitability of our cleaning and regrowth methodfor the fabrication of this type of semiconductor lasers.Device characterisation indicates negligible leakage currentalong the etched mesa sidewalls confirming a smooth regrowthinterface. Nevertheless, experimental and simulation resultsreveal that a significant part of the injected current is lostas leakage through the burying material. This is attributed todouble carrier injection into the SI-GaInP:Fe layer.Simulations also predict that the function of GaInP:Fe ascurrent blocking layer should be markedly improved in the caseof GaAs-based longer wavelength lasers. <b>Keywords:</b>semiconductor lasers, in-plane lasers, VCSELs,GaAs, GaInP, semi-insulating materials, hydride vapour phaseepitaxy, regrowth, buried heterostructure, leakage current,simulation.

This thesis deals with the integral motor of tomorrow, and particularly with a variable speed, sensorless permanent magnet synchronous motor with an integrated converter. The rated power is 15 kW at 1500 r/min. The outer dimensions are approximately the same as for the equivalent standard induction motor. Control strategies for pumps and fans, i.e. suitable loads for variable speed motors, are briefly described. The huge energy savings that can be made by reducing the speed instead of throttling/choking the flow are pointed out. Compared to installing an induction motor with a separate converter, a PM integral motor will probably pay-off in less than a year. A totally analytical expression for calculating the airgap flux density of permanent magnet motors with buried magnets is derived. The analytical expression includes axial leakage, and iron saturation of the most narrow part of the magnetic circuit of the machine. A computer program for optimization of PM motors with buried magnets has been developed. It was used to design the manufactured prototype PM integral motor, and the parameters are investigated with analytical and/or FEM calculations. The optimization program is also used to suggest nearoptimum pole numbers for desired powers (4-37 kW) and speeds (750- 3000 r/min) of inverter-fed PM motors. Results show that compact buried PM motors should have relatively large airgaps and high NdFeB-magnet masses to improve the efficiency. Ferrite magnets are unsuitable. Measurements on the manufactured PM motor, the novel concept of stator integrated filter coils, and the complete PM integral motor are presented. Special attention was given to temperature and overall efficiency measurements. The rotor cage losses were investigated by time-stepping FEM. Four short circuit fault conditions were also examined in order to evaluate the risks of demagnetization of the buried magnets.

The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This thesis presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The thesis also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings.

Advancement in cryptography over the past few decades has enabled a spectrum of security mechanisms and protocols for many applications. Despite the algorithmic security of classic cryptography, there are limitations in application and implementation of standard security methods in ultra-low energy and resource constrained systems. In addition, implementations of standard cryptographic methods can be prone to physical attacks that involve hardware level invasive or non-invasive attacks. Physical unclonable functions (PUFs) provide a complimentary security paradigm for a number of application spaces where classic cryptography has shown to be inefficient or inadequate for the above reasons. PUFs rely on intrinsic device-dependent physical variation at the microscopic scale. Physical variation results from imperfection and random fluctuations during the manufacturing process which impact each device’s characteristics in a unique way. PUFs at the circuit level amplify and capture variation in electrical characteristics to derive and establish a unique device-dependent challenge-response mapping. Prior to this work, PUF implementations were unsuitable for low power applications and vulnerable to wide range of security attacks. This doctoral thesis presents a coherent framework to derive formal requirements to design architectures and protocols for PUFs. To the best of our knowledge, this is the first comprehensive work that introduces and integrates these pieces together. The contributions include an introduction of structural requirements and metrics to classify and evaluate PUFs, design of novel architectures to fulfill these requirements, implementation and evaluation of the proposed architectures, and integration into real-world security protocols. First, I formally define and derive a new set of fundamental requirements and properties for PUFs. This work is the first attempt to provide structural requirements and guideline for design of PUF architectures. Moreover, a suite of statistical properties of PUF responses and metrics are introduced to evaluate PUFs. Second, using the proposed requirements, new and efficient PUF architectures are designed and implemented on both analog and digital platforms. In this work, the most power efficient and smallest PUF known to date is designed and implemented on ASICs that exploits analog variation in sub-threshold leakage currents of MOS devices. On the digital platform, the first successful implementation of Arbiter-PUF on FPGA was accomplished in this work after years of unsuccessful attempts by the research community. I introduced a programmable delay tuning mechanism with pico-second resolution which serves as a key component in implementation of the Arbiter-PUF on FPGA. Full performance analysis and comparison is carried out through comprehensive device simulations as well as measurements performed on a population of FPGA devices. Finally, I present the design of low-overhead and secure protocols using PUFs for integration in lightweight identification and authentication applications. The new protocols are designed with elegant simplicity to avoid the use of heavy hash operations or any error correction. The first protocol uses a time bound on the authentication process while second uses a pattern-matching index-based method to thwart reverseengineering and machine learning attacks. Using machine learning methods during the commissioning phase, a compact representation of PUF is derived and stored in a database for authentication.

The aim of this report was to investigate the potential effects of sulfide oxidation in sediments of an arctic lake, N Luossajärvi, induced by lowered water level. Lake water, potentially contaminated by metals, was pumped into a mine tailings impoundment. The water quality in the receiving water was evaluated to see if the drainage have had an effect on the water quality. Six sediment profiles were sampled. Each profile were divided into 5 cm sections and analyzed for major elements and trace metals. Water chemistry were analyzed at six sites. As, Ni and Cu had high concentrations within undrained sediments, where As levels were classified as highly contaminated (&gt; 27 mg kg-1 dw). Trace metals had strong statistical correlation to each other indicating a common source. The PCA analyzes performed suggests that trace metals are controlled by a common factor and drained sediments showed two additional factors controlling the variance of metals. Water chemistry had overall good status, but As, Cd, Ni and Cu exceeded natural background values. Historical data on the other hand showed no statistical difference from measured values. No effects on water quality could therefore be seen after draining of the lake, proposing high precipitation of metals within the tailing or that metals is still prevailing in the drained sediments. Metal mobility were seen within the drained sediments, where only As and Cd were presumed connected to chemical weathering and where erosion and soil properties seems to be responsible for most metal mobility.

Interactive handheld electronic displays use hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) as a backplane and a Touch Screen Panel (TSP) on top as an input device. The low mobility and instability of a-Si:H TFT threshold voltage are major two issues for driving constant current as required for Active Matrix Organic Light Emitting Ddiode (AMOLED) displays. Low mobility is compensated by increasing transistor width or resorting to more expensive material TFTs. On the other hand, the ever increasing threshold voltage shift degrades the drain current under electrical operation causing OLED display to dim. Mutual capacitive TSP, the current cell phone standard, requires two layers of metals and a dielectric to be put in front of the display, further dimming the device and adding to visual noise due to sun reflection, not to mention increased integration cost and decreased yield. This thesis focuses on the aforementioned technological hurdles of a handheld electronic display by proposing a dual-gate TFT used as an OLED current driving TFT and a novel phase response readout scheme that can be applied to a one metal track TSP. Our dual-gate TFT has shown on average 20% increase in drive current over a single gate TFT fabricated in the same batch, attributed to the aid of a top channel to the convention bottom channel TFT. Furthermore the dual gate TFT shows three times the Poole-Frenkel current than the single gate TFT attributed to the increase in gate to drain overlap. The dual-gate TFT shows a 50% improvement in threshold voltage shift over a single gate TFT at room temperature, but only ~8% improvement under 75ºC. This is an important observation as it shows an accelerated threshold voltage shift in the dual-gate. This difference in the rate of threshold voltage change under varying temperature is attributed to the difference in interface states, supporting Libsch and Kanicki’s multi-level temperature dependant dielectric trapping model. The phase response TSP readout scheme requires IC only on one side of the display. Cadence Spectre simulation results showed that both touch occurrence and touch position can be obtained using only one metal layer.

Fuel cells represent a promising energy alternative to the traditional combustion of fossil fuels. In particular, solid oxide fuel cells (SOFCs) have been of interest due to their high energy densities and potential for stationary power applications. One of the key obstacles precluding the maturation and commercialization of planar SOFCs has been the absence of a robust sealant. A leakage computational model has been developed and refined in conjunction with leakage experiments and material characterization tests at Oak Ridge National Laboratory to predict leakage in a single interface metal-metal compressive seal assembly as well as multi-interface mica compressive seal assemblies. The composite model is applied as a predictive tool for assessing how certain parameters (i.e., temperature, applied compressive stress, surface finish, and elastic thermo physical properties) affect seal leakage rates.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are major devices inintegrated circuit, extensively used in various electronic products. In order to improve the electrical characteristics, scaling channel width and length, using high-£e gate dielectric insulator, and strained silicon may be utilized to increase the driving current and circuit speed. Nevertheless, the scaling of the channel width and length must overcome the limitation of the photolithographytechnology and cost. Once the method is employed, the MOSFETs will face a serious short-channel effect and gate leakage current. In the aspect of high-£e gate dielectric insulator, there still have problems, containing the trap states, phonon scattering, dipole-induced threshold voltage variation, needed to be solved. This dissertation focuses on the properties of MOSFETs experienced an external-mechanical strain, where the channel will be strained. Hence, the mobility, driving current, and circuit speed will increase. Our research can be divided into three topics: fabricating process-induced strained Si, external mechanical stress-induced strained Si, and the properties of strained Si MOSFETs at different temperatures. Except the electrical measurement, we also used the ISE-TCAD to simulate the electrical characteristic of MOSFETs under stress. Firstly, we apply the stress on n-MOSFETs by utilizing the nitride-capping layer. Once the lattice is strained, the mobility will increase, hence resulting in the operating speed. Secondly, the electrical characteristics under external stress is explored by introduced the external mechanical stress along the channel length of nMOSFETs. In addition to the fabricating process-induced strain, the fabricating process condition will also influence the device characteristics. As a result, we propose a new strain technology for our following research. Thirdly, the device performance of strained Si under different temperatures is investigated. Finally, we discuss the gate leakage current in strained Si depending on the ultra-thin gate oxide layer.

Technology scaling has been the most obvious choice of designers and chip manufacturing companies to improve the performance of analog and digital circuits. With the ever shrinking technological node, process variations can no longer be ignored and play a significant role in determining the performance of nanoscaled devices. By choosing a worst case design methodology, circuit designers have been very munificent with the design parameters chosen, often manifesting in pessimistic designs with significant area overheads. Significant work has been done in estimating the impact of intra-die process variations on circuit performance, pertinently, noise margin and standby leakage power, for fixed transistor channel dimensions. However, for an optimal, high yield, SRAM cell design, it is absolutely imperative to analyze the impact of process variations at every design point, especially, since the distribution of process variations is a statistically varying parameter and has an inverse correlation with the area of the MOS transistor. Furthermore, the first order analytical models used for optimization of SRAM memories are not as accurate and the impact of voltage and its inclusion as an input, along with other design parameters, is often ignored. In this thesis, the performance parameters of a nano-scaled 6-T SRAM cell are modeled as an accurate, yield aware, empirical polynomial predictor, in the presence of intra-die process variations. The estimated empirical models are used in a constrained non-linear, robust optimization framework to design an SRAM cell, for a 45 nm CMOS technology, having optimal performance, according to bounds specified for the circuit performance parameters, with the objective of minimizing on-chip area. This statistically aware technique provides a more realistic design methodology to study the trade off between performance parameters of the SRAM. Furthermore, a dual optimization approach is followed by considering SRAM power supply and wordline voltages as additional input parameters, to simultaneously tune the design parameters, ensuring a high yield and considerable area reduction. In addition, the cell level optimization framework is extended to the system level optimization of caches, under both cell level and system level performance constraints.