As redes de distribuição de sinais de tempo - ou redes de sincronismo - têm a tarefa de distribuir os sinais de fase e freqüência ao longo de relógios geograficamente dispersos. Este tipo de rede é parte integrante de inúmeras aplicações e sistemas em Engenharia, tais como sistemas de comunicação e transmissão de dados, navegação e rastreamento, sistemas de monitoração e controle de processos, etc. Devido ao baixo custo e facilidade de implementação, a topologia mestre-escravo tem sido predominante na implementação das redes. Recentemente, devido ao surgimento das redes sem fio - wireless - de conexões dinâmicas, e ao aumento da freqüência de operação dos circuitos integrados, topologias complexas, tais como as redes mutuamente conectadas e small world têm ganhado importância. Essencialmente cada nó da rede é composto por um PLL - Phase-Locked Loop - cuja função é sincronizar um oscilador local a um sinal de entrada. Devido ao seu comportamentamento não-linear, o PLL apresenta um jitter com o dobro da freqüência de livre curso dos osciladores, prejudicando o desempenho das redes. Dessa forma, este trabalho tem como objetivo o estudo analítico e por simulação das condições que garantam a existência de estados síncronos, e do comportamento do jitter de fase nas redes de sincronismo. São analisadas as topologias mestre-escravo e mutuamente conectada para o PLL analógico clássico. / Network synchronization deals with the problem of distributing time and fre- quency among spatially remote locations. This kind of network is a constituent element of countless aplications and systems in Engineering, such as communication and data transmission systems, navigation and position determination, monitoring and process control systems, etc. Due to its low cost and simplicity, the master-slave architec- ture has been widely used. In the last few years, with the growth of the dynamically connected wireless networks and the rising operational frequencies of the integrated cir- cuits, the study of the mutually connected and small world architectures are becoming relevant. Essentially, each node of a synchronization network is constituted by a PLL - Phase-Locked Loop - circuit that must automatically adjust the phase of a local oscillator to the phase of an incoming signal. Because of its nonlinear behavior the PLL presents a phase jitter with the double of the free running frequency of the oscillators, impairing the network performance. Thus, this work aims to study, both analytically and by simulation, the existence conditions of the synchronous states and the behavior of the double frequency jitter in the synchronization networks. Specifically the One Way Master Slave (OWMS) and Mutually Connected (MC) network architectures for classical analogical PLLs are analyzed.

Este trabalho apresenta o projeto de uma portadora que opera na frequência de 8.300 MHz para ser utilizado em moduladores vetoriais diretos com aplicação em sistemas embarcados de satélites. Foram realizados estudos sistêmicos de arquiteturas que operam nesta faixa de frequência com as características necessárias para atender as especificações da European Cooperation for Space Standardization, ECSS - Space Engineering Radio Frequency and Modulation da agência espacial europeia -ESA, que regulamenta as frequências e características para sistemas de transmissão para enlace de descida. A partir dos conhecimentos adquiridos nos estudos, é apresentada uma metodologia de projeto visando o atendimento das especificações definidas pela ECSS e a escolha de uma topologia de projeto. Foram realizadas simulações a nível sistêmico, utilizando o software Advanced Design System-ADS da fabricante Keysight Technologies, para definir as especificações de projeto dos circuitos que compõem o sistema de geração da portadora na banda X. O circuito da malha de sincronismo de fase - PLL opera na frequência de 2.075 MHz, onde seu sinal é amplificado e filtrado pela cadeia de amplificação na banda S cuja função é aumentar a isolação para minimizar os efeitos de pulling do oscilador controlado por tensão - VCO, devido à alta velocidade nas transições de tempo de subida e de descida dos sinais digitais I e Q. O filtro também é responsável por aumentar a rejeição de espúrios e harmônicos gerados pelos efeitos não lineares dos amplificadores. O sinal é enviado ao circuito multiplicador de frequências que gera o sinal na banda X e é filtrado por um filtro passa-faixas de linhas acopladas, rejeitando os sinais espúrios provenientes da saída do multiplicador de frequência. Na saída, o sinal passa por uma cadeia de amplificação na banda X para adequar o nível de potência à entrada dos moduladores vetoriais. Os circuitos projetados foram desenvolvidos utilizando tecnologia de microfita de linha. Os protótipos foram caracterizados, apresentando boa concordância com os resultados simulados, comprovando experimentalmente a metodologia de projeto utilizada neste trabalho assim como o atendimento das especificações sugeridas pela ECSS. / This work presents the project of an carrier that works in the frequency of 8,300 MHz to be used in direct vector modulator for embedded system application in satellites. It were realized system level studies of PLL topologies that work in this frequency range with the necessary features to provide the requirements from European Cooperation for Space Standardization, ECSS - Space Engineering Radio Frequency and Modulation of the European Space Agency - ESA, which is responsible for the frequencies and features regulation for downlink transmission system. With the knowledge acquired from the studies, it is presented a project method intending to the meet the requirements defined by the ECSS and the definition of a topology to the project. It were performed system level simulation, using the Advanced Design System - ADS tool, from Keysight Technologies, in order to define the design specifications in the project of the circuits of the X band carrier generator developed. The PLL circuit works in the frequency of 2,075 MHz, in which its signal is amplified and filtered for amplifier chain in S band, increasing the isolation to reduce the pulling effects in the voltage controlled oscillator, due to the high-speed transitions in the rise time and fall time of the digital signal I and Q. The filter is also responsible for increasing the rejection of spurious and harmonics generated by non-linear amplifiers effects. The signal is conducted to the frequency multiplier circuit that generates the X band signal and it is filtered by a coupled line bandpass filter, rejecting the spurious from the frequency multiplier output. At the output stage, the signal passes through a X band amplification chain in order to adequate the power level of the vector modulators input level. The specified circuits were designed and developed using microstrip line technology. The prototypes were characterized, presenting adequate results according to the data obtained by the simulations, experimentally reinforcing the project method used in this work as well as the meeting of the requirements suggested by the ECSS.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-03-21T18:37:34Z No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-03-22T12:40:06Z (GMT) No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5) / Made available in DSpace on 2017-03-22T12:40:06Z (GMT). No. of bitstreams: 1 pedrohenriquedecastrogomes.pdf: 1205999 bytes, checksum: b3d28e019c29c4bb978f107c4b25c3ef (MD5) Previous issue date: 2007-08-22 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / A crescente demanda pelos consumidores por índices de qualidade de energia cada vez mais elevados e a recente desregulamentação do setor elétrico, vem exigindo uma demanda cada vez maior pelo monitoramento da qualidade da energia elétrica pelas concessionárias de uma maneira descentralizada. Aliado a esse fato, a alta proliferação de cargas não lineares conectadas à rede elétrica, entre outros, têm tornado a estimação de parâmetros dos sinais elétricos da rede uma tarefa cada vez mais desafiadora. Assim, o desenvolvimento de algoritmos de estimação eficientes e com baixa complexidade computacional, ou passíveis de implementação em sistemas (hardwares) de baixo custo, têm-se tornando uma prerrogativa importante. Nesse escopo, essa dissertação apresenta a descrição de uma malha de PLL (Phase-Locked-Loop) robusta (ER-QPLL), capaz de estimar os parâmetros (fase, freqüência e amplitude) da componente fundamental de um sinal de entrada qualquer. O desenvolvimento da estrutura baseou-se no aprimoramento de uma malha de PLL do tipo quadratura (QPLL), que estima os parâmetros da componente fundamental de um sinal de entrada através da aquisição das suas componentes em fase e em quadratura. As modificações da malha foram a introdução de um filtro notch adaptativo em sua entrada e a implementação de toda a estrutura utilizando o operador delta (δ), relacionado à Transformada Gama (γ). A introdução do filtro notch adaptativo na entrada da malha garante uma significativa melhoria na relação SNR do sinal de entrada, sem prejudicar demasiadamente a resposta dinâmica da estrutura. A característica adaptativa do filtro garante uma performance satisfatória da malha para sinais de entrada com parâmetros variantes no tempo. A implementação da malha utilizando o operador delta (δ) assegura uma performance ideal quando a mesma é implementada em sistemas de precisão limitada de, no mínimo, 16 bits. De acordo com os resultados demonstrados nesse trabalho, a performance da malha é satisfatória mesmo ao se utilizar altas taxas de amostragem relativas à freqüência de operação da malha. Finalmente, foi proposta uma implementação da malha em um microprocessador (DSP) da família TMS320, o que comprova a viabilidade de implementação da mesma em sistemas (hardware) de ponto fixo. / The always more restrictive energy quality benchmarks, pushed on by consumers, associated with the electric sector deregulamentation has been imposing the necessity, for the concessionaries, of a better and decentralized monitoring of energy electric quality. At the same time, the increase of nonlinear loads connected to the electric network, among other facts, has been increasing the complexities associated with this electric signals parameters estimation. So, the synthesis of efficient parameters estimation algorithms, with low computational effort and with easy implementation on low-cost hardware systems has becoming a priority for the energy quality area. Based on these assumptions, this work deals with the design and synthesis of a robust Phase-Locked-Loop (PLL) structure, more specifically an Enhanced Quadrature Phase-Locked-Loop (ER-QPLL) with capacity of estimate several parameters, more specifically phase, frequency and amplitude, from any input signal. The synthesis of this ER-QPLL structure was based on the enhancement of a Quadrature Phase-Locked-Loop (QPLL) that can estimate the parameters of the fundamental component of any input signal thought the information acquired with the acquisition of its phase and quadrature components. The enhancements of this QPLL structure were, basically, the introduction of a adaptive notch filter on its input, associated with an delta operator (δ), a tool of the gamma transformer (γ), for modeling the whole structure. A significant improvement in the SNR of the input signal, without degradation of the dynamic structure output, was achieved with the introduction of the notch filter. The adaptive characteristics of this notch filter can deal, in a very good way, with the non-stationery properties of the input signals. The structure implementation based on delta operator (δ) can assure an almost ideal performance for limited precision systems of, at least, 16 bits. According to the results obtained in this work, the performance of the proposed structure can be considered very good, even when dealing with high sampling rates relative to the network frequency operation. Finally, a structure based on a microprocessor DSP from TMS320 family was proposed and implemented showing its feasibility for fixed-point hardware.

In recent years, neuromorphic architectures have been an increasingly effective tool used to solve big data problems. Hardware neural networks have not been able to fully exploit the power efficient properties of the neural paradigm, however, due to limitations in standard CMOS. One of the largest challenges is the quadratic scaling of the synapses in a neural network. There has been some work in using post CMOS technology as synapses to overcome this limitation, but systems to date have not been scalable due to the design of their neurons. This dissertation aims to design and build scalable neural network architectures that can use emerging resistive memory technology as synapses. Using analog computing techniques to build networks is promising, especially due to the development of dense, CMOS compatible analog resistive memories. Building functional analog networks in advanced technology nodes, however, is challenging due to the relatively poor performance of analog components in these nodes. This work explores oscillatory neural networks (ONNs), which use phase as the analog state variable instead of voltage or current, reducing the number of traditional analog components required and making the networks better-suited for advanced nodes. This thesis develops additional ONN theory with regard to hardware networks, since previous work did not consider the effect of transmission delay on network dynamics. Transmission delay is proven to cause desynchronization in unmodified ONNs, and the theoretical analysis suggests ways to build networks which do synchronize. Conclusions from the theoretical development are used to build a PLL-based ONN in hardware. The PLL-based ONN is more energy efficient than comparable systems implemented in digital CMOS, although the neuron area is somewhat larger. The measurement of the PLL-based ONN also reveals additional poorly-studied facets of ONN dynamics. Using the knowledge gained from the PLL-based ONN, a larger, PLL-free ONN is built in the same technology. Removing the PLL in each neuron reduces the power and area consumption without sacrificing any functionality.This dissertation demonstrates that ONNs are well-suited to take advantage of emerging resistive memory technology to build efficient hardware neural networks.

Vertical external-cavity surface-emitting lasers are ideal testbeds for studying the influence of the non-equilibrium many-body dynamics on mode locking. As we will show in this thesis, ultra short pulse generation involves a marked departure from Fermi carrier distributions assumed in prior theoretical studies. A quantitative model of the mode locking dynamics is presented, where the semiconductor Bloch equations with Maxwell’s equation are coupled, in order to study the influences of quantum well carrier scattering on mode locking dynamics. This is the first work where the full model is solved without adiabatically eliminating the microscopic polarizations. In many instances we find that higher order correlation contributions (e.g. polarization dephasing, carrier scattering, and screening) can be represented by rate models, with the effective rates extracted at the level of second Born-Markov approximations. In other circumstances, such as continuous wave multi-wavelength lasing, we are forced to fully include these higher correlation terms. In this thesis we identify the key contributors that control mode locking dynamics, the stability of single pulse mode-locking, and the influence of higher order correlation in sustaining multi-wavelength continuous wave operation.

La demande croissante de toujours plus de débit pour les télécommunications entraine une augmentation de la fréquence de fonctionnement des liaisons séries. Cette demande se retrouve aussi dans les systèmes embarqués du fait de l'augmentation des performances des composants et périphériques. Afin de s'assurer que le train de données est bien réceptionné, un circuit de restitution d'horloge et de données est placé avant tout traitement du coté du récepteur. Dans ce contexte, les activités de recherche présentées dans cette thèse se concentrent sur la conception d'une CDR (Clock and Data Recovery). Nous détaillerons le comparateur de phase qui joue un rôle critique dans un tel système. Cette thèse présente un comparateur de phase ayant comme avantage d'avoir une mode de fenêtrage et une fréquence de fonctionnement réduite. La topologie spéciale utilisée pour la CDR est décrite, et la théorie relative aux oscillateurs verrouillés en injection est expliquée. L'essentiel du travail de recherche s'est concentrée sur la conception et le layout d'une restitution d'horloge dans le domaine millimétrique, à 80 Gbps. Pour cela plusieurs prototypes ont été réalisés en technologie BiCMOS 130 nm de STMicrolectronics. / The increasing bandwidth demand for telecommunication leads to an important rise of serial link operating frequencies. This demand is also present in embedded systems with the growth of devices and peripherals performances. To ensure the data stream is well recovered, a clock and data recovery (CDR) circuit is placed before any logical blocks on the receiver side. The research activities presented in this thesis are related to the design of such a CDR. The phase detector plays a critical role in the CDR circuit and is specially studied. This thesis presents a phase comparator that provides an enhancement by introducing a windowed mode and reducing its operating frequency. The used CDR has a special topology, which is described, and the injection locked oscillator theory is explained. Most of the research of this study has focused on the design and layout of a 80 Gbps CDR. Several prototypes are realized in 130 nm SiGe process from STMicroelectronics.

This thesis investigates issues affecting grid synchronisation of VSC-HVDC systems with particular regard to, but not limited to, offshore wind power generation during the complex but potentially serious behaviours following solar storms. An averaged value model (AVM) for the contemporary modular multilevel converter (MMC) based VSC-HVDC system is developed and is used in combination with different phase-locked loop (PLL) models and the unified magnetic equivalent circuit (UMEC) transformer model to assess the impacts of geomagnetically induced current (GIC) on grid synchronisation of an offshore VSC-HVDC system. GIC is DC current flowing in the earth caused by strong geomagnetic disturbance events. GIC enters the electric utility grid via the grounded transformer neutral and can cause severe saturation to transformers. This in turn causes disruptions to grid synchronisation. The main contribution of this thesis is that effects of GIC are studied using the UMEC transformer model, which can model saturation. The assessment leads to the development of enhanced fundamental positive sequence control (EFPSC) which is capable of reducing the stress on the system during GIC events. The methods developed can also be applied to other non-symmetrical AC events occurring in VSC-HVDC such as single-phase faults. Additional contributions of the thesis are:A mathematical model of the MMC is derived and forms the foundation of the AVM. The AVM is verified against a detailed equivalent-circuit-based model and shows good accuracy. The PLL is the essential component for grid synchronisation of VSC-HVDC system. Different PLLs are studied in detail. Their performance is compared both qualitatively and quantitatively. This appears to have been done for the first time systematically in the public literature. The UMEC model is verified using hand calculation. Its saturation characteristic is matched to a predefined B-H curve and is also verified. The verifications show that this model is capable of modelling transformer saturation and thus is suitable for this study. The consolidation of the AVM, PLL, UMEC, GIC and EFPSC provides an insight into the how the MMC based VSC-HVDC system behaves under severe geomagnetic disturbances and the possible methods to mitigate the risks and impacts to the power grid.

My diploma thesis focuses on the M&A transaction closing mechanisms. Their function is to reflect the value changes of the target company into the purchase price. Value change occurs during the time lag between the date of the financial statements and the date of the transaction closing. Throughout history, there have been two major approaches developed. The "Completion Accounts Mechanism" uses post-completion price adjustments to reflect the change of the net working capital and net debt during the interim period. The "Locked Box Mechanism", using fixed price, assures non-fluctuation of target value in the interim period by imposing strict restrictions on the seller's activities. In this research, I have analyzed 44 transactions closed in the Czech Republic. I have challenged the theoretical foundations and described the application of the mechanisms in practice. At the end, I have compared the Czech and European practices. Thesis findings: 1. All the theoretical features of the mechanisms were proven by an analyzed sample of closed transactions. The completion accounts mechanism is buyer-friendly, while the locked box is a seller-friendly mechanism. 2. The main driver in mechanism selection is bargaining power. Buyers were in a better negotiating position in 69% of the completion account transactions. On the contrary, the sellers had bargaining power in 100% of the locked box transactions. 3. The Czech Republic is an environment where buyers (big multinational companies) dominate. They have preferred the completion account mechanism that provides them with higher protection from value leakage or other risks associated with small CEE economies. A total of 91% of analyzed transactions were executed by the completion account mechanism in the Czech Republic between 2011 and 2012.

Time-to-digital converters (TDC) are widely used in light-detection-and-ranging (LIDAR) systems to measure the time-of-flight. Conventional TDCs are sensitivity to process, voltage, and temperature (PVT) variations. Recent work utilizing the stochastic delay-line TDC architecture has demonstrated excellent robustness against PVT variations. But important issues affecting the linearity of a stochastic delay-line TDC has yet to be recognized and addressed.This thesis rigorously analyzes the problem of linearity of a stochastic delay-line TDC and formulates an intuitive theory to predict the linearity performance. Apolarvisualization of the phase distribution of a delay line is proposed to aid the analysis. Based on the results of this study, this thesis proposes a stochastic delay-line TDC employing a delay-locked loop (DLL) to guarantee linearity over PVT variations and to reduce the number of redundant bits. The proposed TDC is implemented in a 0.18 µm CMOS process to validate the linearity theory and the proposed solution. The 8-bit TDC samples at 60 MHz and demonstrates a linear-number-of-bit of 6.36 with only 2-bit redundancy. Consuming 25 mW from a 1.8 V supply, the TDC yields a figure-of-merit of 5.04 pJ/conversion-step. With the DLL turned off, the integral nonlinearity (INL) degrades by about a factor of two, verifying the effectiveness of the proposed solution. The TDC is measured at different temperatures and supply voltages to demonstrate robustness against PVT variations. The measurement results show excellent agreement with the behavioral simulations.

Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1976 / Includes bibliographical references. / M.S. / M.S. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science