<p>In wireless communication there is commonly much unnecessary communication made in directions not pointing towards the recipient. Normally omni directional antennas are being used which sends the same amount of energy in all directions equally. This waste of energy reduces the lifetime of battery powered units and causes more traffic collisions than necessary. One way of minimizing this wasted energy and traffic collisions, is to use another type of antenna called “smart antenna”. These antennas can use selectable radiation patterns depending on the situation and thus drastically minimize the unnecessary energy waste. Smart antennas also provide the ability to sense the direction of incoming signals which is favorable for physical layout mapping such as orientation.</p><p>This thesis presents the prototyping of a new type of smart antenna called the SPIDA smart antenna. This antenna is a cheap to produce smart antenna designed for the 2.4 GHz frequency band. The SPIDA smart antenna can use sixty-four different signal patterns with the control of six separate directional modes, amongst these patterns are six single direction patterns, an omni-directional signal pattern and fifty-six combi-direction patterns. The thesis presents complete building instructions, evaluation data and functional drivers for the SPIDA smart antenna.</p>

<p>In this thesis, a Static Random Access Memory generator has been designed and implemented. The tool can generate memories of different sizes. The number of words that can be stored can be chosen among powers of 2 and the number of bits per word can be up to 48. </p><p>The focus of the thesis was to find an adequate structure for the generated memories depending on the size, and develop a memory generator that implements the structures, which has been thoroughly done. The single circuits used in the generated memories can be substituted with better circuits as well as adapted to other processes. </p><p>All circuits apart from a block decoder circuit have been developed. The memory generator was not supposed to automatically produce a complete layout, and some manual interventions on the memories generated by the tool are necessary. The tool requires to be developed further to minimise this manual intervention on the generated memories. The complete memories generated have not been tested because of their complexity, but tests on circuits as well as many parts of the memories have been carried out. </p><p>During the thesis work, a large amount of tasks had to be carried out and a lot of issues had to be dealt with, which has been a problem. The tool used for the implementation has powerful features for both analog and digital electronic design, but has stability problems with large designs, which has been a big obstacle in this work.</p>

<p>Significant advanced development in the field of communication has led many designers and healthcare professionals to look towards wireless communication for the treatment of dreadful diseases. Implant medical device offers many benefits, but design of implantable device at very low power combines with high data rate is still a challenge. However, this device does not rely on external source of power. So, it is important to conserve every joule of energy to maximize the lifetime of a device. Choice of modulation technique, frequency band and data rate can be analyzed to maximize battery life.</p><p>In this thesis work, system level design of FSK and QPSK transmitter is presented. The proposed transmitter is based on direct conversion to RF architecture, which is known for low power application. Both the transmitters are designed and compared in terms of their performance and efficiency. The simulation results show the BER and constellation plots for both FSK and QPSK transmitter.</p>

<p>In this master thesis, a behavioral VHDL model of a 1k Fast Fourier Transform (FFT) algorithm has been improved, first to make it synthesizable and second to obtain a low power consumption. The purpose of the thesis has not been to focus on the FFT algorithm itself or the theory behind it. Instead the aim has been to document and motivate the necessary modifications, to reach the stated requirements, and to discuss the results. The thesis is divided into sections so that the design flow closely can be followed from the initial FFT, down to the final architecture. The two major design steps covered are synthesis and power simulation. The synthesis process has been the most time consuming part of the thesis. </p><p>The synthesis tool Cadence Ambit PKS was used. Throughout the synthesis, the modifications and solutions will be discussed and comparisons are continuously made between the different solutions and the initial FFT. The best solution will then be the starting point in the next design step, which is simulation of the design with respect to power consumption. This is done by using a simulation tool from Synopsys called NanoSim. Also here, every solution is tested and compared to each other, followed by a concluding discussion. The technology used to implement the design is a 0.35um CMOS process.</p>

<p>Phase locked loop (PLLs) are the keystone for the electronic as well as for the communication circuits. Without any exaggeration, PLLs are found almost in every electronic and communication devices. Countless research has been performed, for the modification and enhancement of the PLLs circuit. While, due to the numerous advantage of the digital circuitry, the recent research is focusing on the all digital implementation of the PLLs. Therefore, it was competitive to touch with burning research.</p><p>Low power and wide range all digital phase locked loop (ADPLL), for video applications is presented. ADPLL has an operating input frequency between 10kHz to 150 kHz and output frequency between 10 MHz to 300 MHz. The phase frequency detector (PFD) is based on D-flip flops, having two output error and direction signal. The traditional charge pump (CP) is replaced by time-to-digital converters (TDC) and analog low pass filter (LPF) by digital low pass filter (digital-LPF). For completely digital architecture, voltage controlled oscillator (VCO) is replaced by the digitally controlled oscillator (DCO). In DCO, eleven bits are dedicated for controlling bits, two bits for biasing and one bit for enable the DCO. The designed steps for ADPLL were almost similar to the designed steps of a second order analog PLL. The ADPLL is implemented on a CMOS 65-nm technology.</p>

Since integration technology is approaching the nanoelectronics range, some practical limits are being reached. Leakage power is increasing more and more with the continuous scaling, and design of clock distribution systems needs to be reconsidered as it becomes difficult to deal with performance and power consumption specifications while keeping a correct synchronisation in modern multi-GHz systems. The ongoing technology trend will become difficult to maintain unless dedicated library cells, new logic styles and circuit methods are emerging to prevent the drawbacks of future nanoscale circuits. In this thesis we investigate a new class of dynamic differential logic family that features a self-timed operation and low output logic swing. The latter contributes to reduce dynamic power, while the self-timing scheme alleviates the drawbacks of synchronous circuits and systems. Furthermore, the dynamic and differential nature of LSCML class brings advantages in terms of reduction of the power consumption variation and thus gives LSCML an additional potential for implementation of secure encryption devices against attacks based on power analysis. We investigate dynamic and leakage power reduction at the cell level through the application of low-power low-voltage techniques to a new hybrid full adder structure. The 8b RCA circuit based on the ULPFA (ultra low power full adder) version of this full adder, achieves a total power and a leakage power, which are both reduced by 50% compared to the 8b RCA implemented with conventional static CMOS full adder, while featuring better power delay product.

Since integration technology is approaching the nanoelectronics range, some practical limits are being reached. Leakage power is increasing more and more with the continuous scaling, and design of clock distribution systems needs to be reconsidered as it becomes difficult to deal with performance and power consumption specifications while keeping a correct synchronisation in modern multi-GHz systems. The ongoing technology trend will become difficult to maintain unless dedicated library cells, new logic styles and circuit methods are emerging to prevent the drawbacks of future nanoscale circuits. In this thesis we investigate a new class of dynamic differential logic family that features a self-timed operation and low output logic swing. The latter contributes to reduce dynamic power, while the self-timing scheme alleviates the drawbacks of synchronous circuits and systems. Furthermore, the dynamic and differential nature of LSCML class brings advantages in terms of reduction of the power consumption variation and thus gives LSCML an additional potential for implementation of secure encryption devices against attacks based on power analysis. We investigate dynamic and leakage power reduction at the cell level through the application of low-power low-voltage techniques to a new hybrid full adder structure. The 8b RCA circuit based on the ULPFA (ultra low power full adder) version of this full adder, achieves a total power and a leakage power, which are both reduced by 50% compared to the 8b RCA implemented with conventional static CMOS full adder, while featuring better power delay product.

The digital product increases widely and vastly. Because we live in the analog world, we require a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed and low power analog to digital converter. In this thesis, the circuits are designing with TSMC.18 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit.

In large controller-datapath systems, the switching activity of datapath is administered by controller. The unnecessary switching activity will cause more power consumption, and therefore the design of controllers (i.e. Finite State Machines, FSMs) will influence the whole power consumption of the systems. The state assignment and output encoding are the two major factors influencing the power of system under the hardware implementation of controllers. In this paper, we present an integer linear programming (ILP) method to solve the state assignment and output encoding problems. The purpose is to reduce switching activity such that the goal of power optimization can be achieved. It has not to reschedule the operations of datapath under timing and resource constraints and has no extra area overhead. In order to verify the effectiveness of our proposed ILP approach, we use this approach to implement several controller-datapath systems. Experimental results show that our proposed approach achieves an average of 30.513% power savings compared to the traditional area optimal synthesis tool, SIS, where power is not considered. Our proposed approach does not cause extra area overhead while achieving a significant power saving of systems.

The revolutionary progress that happened recently in the micro-electro mechanicalsystems (MEMS) field and the complementary metal-oxide-semiconductor(CMOS) integrated circuits has made it possible to produce low-cost, low-powerand small size processing circuits. Utilizing wireless communication theory allowsthose circuits to send their data over a network. This wireless sensor network isknown as "Smart Dust". Each wireless sensor node in the network is indicated as "mote". It consistsof several components: sensors, micro-processors, radio transceivers and a powermanagement unit. The power management unit can be divided into several partsincluding battery, power control and regulator. The purpose of the regulator is tosupply a constant reliable voltage to the other parts in the mote as most of thedevices have voltage limits that need to be considered to guarantee producing arobust long-life mote. In this thesis designing a low-power regulator is investigated. The goal of thethesis is to design a regulator that can handle the high-voltage acquired froman energy harvest unit using only 65-nm core transistors. This allows an easierproduction process that results in a low-cost fully-integrated chip. The regulatorarchitecture to be used is a simple linear regulator. The report highlights the theoretical background, the challenges of the analogdesign and presents the results of the simulation that were ran using cadence designsystem software on schematic level.