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A design of low power wearable system for pre-fall detectionRathi, Neeraj R. 08 March 2018 (has links)
Indiana University-Purdue University Indianapolis (IUPUI) / Fall in recent years have become a potential threat to elder generation. It occurs because of side effects of medication, lack of physical activities, limited vision, and poor mobility. Looking at the problems faced by people and cost of treatment after falling, it is of high importance to develop a system that will help in detecting the fall before it occurs. Over the year's, this has influenced researchers to pursue the development to automatic fall detection system. However, much of existing work achieved a hardware system to detect pre and post fall patterns, the existing systems deficient in achieving low power consumption, user-friendly hardware implementation and high precision. Growth in medical devices can be seen in recent years. Today's medical devices aim to increase the life expectancy and comfort of human being. The systems are designed to be made reliable by improving the performance, optimizing the size and minimizing the energy consumption. For wearable technologies, power consumption is an important factor to be considered during system design. High power consumption decreases the battery life, which leads to poor comfortability. The purpose of this research is to develop a system with low power consumption to detect human falls before they happen. This research points towards the development of dependable and low power embedded system device with easy to wear capabilities and optimal sensor structure. In this work, we have developed a device using motion sensor to sense the subjects linear and angular velocity, communication sensor to send the fall related information to caretaker, and signal sensors to communicate and update user about device information. The designed system is triggered on interrupts from motion sensor. As soon as the system is triggered by an interrupt signal, users balanced and unbalanced states gets monitored. Once the unbalanced state is designated, the system signifies it as fall by setting a fall flag. The fall decision parameters; pitch, roll, complementary pitch, complementary roll, Signal Vector Magnitude (SVM), and Signal Magnitude Area (SMA) are layered to classify subject's different body posture. This helps the system to differentiate between activity of daily living (ADL) and fall. When the fall flag is set, the device sends important information like GPS location and fall type to caretaker. Early fall detection gives milliseconds of time to initiates the preventive measures.
The system was designed, developed, and constructed. Near 100% sensitivity, 96% accuracy, and 95% specificity for fall detection were measured. The system can detect Front, Back, Side and Stair fall with consumption of 100_A (650_A with BLE consumption) in deep sleep mode, 6.5mA in active mode with no fall, and 14.5mA, of which 8.5 mA is consumed via the BLE when fall is declared in active mode. The power consumption was reduced because the integrated wireless communication devices consumed power only when the fall is triggered, giving the device a potential to communicate wirelessly.
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Design Automation Flow for Voltage Adaptive Light Vth Hopping for Leakage Minimization in Sequential CircuitsBalasubramanian, Venkat Krishnan January 2012 (has links)
No description available.
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Software Techniques to Reduce the Energy Consumption of Low-Power Devices at the Limits of Digital AbstractionsSalajegheh, Mastooreh 01 February 2013 (has links)
My thesis explores the effectiveness of software techniques that bend digital abstractions in order to allow embedded systems to do more with less energy. Recent years have witnessed a proliferation of low-power embedded devices with power ranges of few milliwatts to microwatts. The capabilities and size of the embedded systems continue to improve dramatically; however, improvements in battery density and energy harvesting have failed to mimic a Moore's law. Thus, energy remains a formidable bottleneck for low-power embedded systems.
Instead of trying to create hardware with ideal energy proportionality, my dissertation evaluates how to use unconventional and probabilistic computing that bends traditional abstractions and interfaces in order to reduce energy consumption while protecting program semantics. My thesis considers four methods that unleash energy otherwise squandered on communication, storage, time keeping, or sensing: 1) CCCP, which provides an energy-efficient storage alternative to local non-volatile storage by relying on cryptographic backscatter radio communication, 2) Half-Wits, which reduces energy consumption by 30% by allowing operation of embedded systems at below-spec supply voltages and implementing NOR flash memory error recovery in firmware rather than strictly in hardware, 3) TARDIS, which exploits the decay properties of SRAM to estimate the duration of a power failure ranging from seconds to several hours depending on hardware parameters, and 4) Nonsensors, which allow operation of analog to digital converters at low voltages without any hardware modifications to the existing circuitry.
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A Highly Efficient CMOS Rectifier for Ultra-Low-Power Ambient RF Energy HarvestingWang, Ruiyan January 2021 (has links)
No description available.
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Low Power Hybrid CMOS-NEMS for Microelectronics: Implementation in Implantable PacemakerArora, Samarth 19 September 2011 (has links)
No description available.
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SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DACZHANG, GUANGLEI, ZHANG 11 June 2018 (has links)
No description available.
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LOW POWER FPGA DESIGN TECHNIQUES FOR EMBEDDED SYSTEMSTIWARI, ANURAG 31 May 2005 (has links)
No description available.
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COMPLIANCE AND EVALUATION OF CODE FOR LOW ENERGY POWER OPERATED HANDICAP ACCESSIBLE DOORSWIGGERMANN, NEAL 09 October 2007 (has links)
No description available.
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Micromachined On-Chip Fluxgate Magnetometers with Low Power ConsumptionWu, Pei-Ming 09 August 2010 (has links)
No description available.
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Ultra-Wideband, Low Power, Silicon Germanium Distributed AmplifiersEl-Badry, Ehab 09 1900 (has links)
<p> As modern digital communications evolve, the requirements imposed on the
systems than are required to transmit/receive the signals involved become more stringent.
Amplifiers are required to provide gain from low frequencies, sometimes down to DC, up
to high frequencies in the order of few to tens of gigahertz. Not only is the gainbandwidth
product to be enhanced, but also the amplifier should introduce minimal distortion to the signal and consume as low power as possible. </p> <p> Distributed amplification is a multi-stage broadband circuit technique that may provide such a function. In distributed amplifiers, inter-stage transmission lines provide the capability to reach higher operational frequencies by absorbing the parasitic capacitances of the transistors used. Unlike other broadband topologies that trade-off gain and bandwidth, distributed amplifiers do not, but rather, the trade-off is between gain and delay. As gain stages are added, the gain increases as the bandwidth remains the same but the signal delay is increased. </p> <p> This work considers the silicon germanium (SiGe) heterojunction bipolar transistor (HBT) implementation of distributed amplifiers. SiGe HBTs incorporate a thin SiGe base with Ge profiling to achieve high cut-off frequencies. SiGe BiCMOS
processes are silicon based and hence have the major advantage of integrability to the low
cost CMOS process unlike ill-V compound semiconductors. Hence, SiGe is a promising
technology capable of bridging the performance gap between silicon and m-v
semiconductors. </p> <p> The proposed amplifier achieves an approximately flat gain of 6.5 dB and a noise figure of 5.8-9 dB throughout the -3 dB passband of 10.5 GHz. The power consumed is
12.2 mW, significantly lower than previously published results by up to an order of
magnitude is some cases. The group delay of the amplifier was found to be
approximately constant in the passband at -60 ps. </p> <p> For the first time, temperature measurements are preformed on SiGe HBT DAs. Analysis show that the gain falls drastically with temperature increase due to deterioration in input matching caused by the significant change in the transistors input impedance with temperature. Similarly the NF, increases with temperature due to the decrease in gain. Moreover, noise analysis of SiGe HBT DAs is investigated, producing
simulations predicting the NF of the proposed amplifier giving insight as to how noise
may be reduced in future designs. </p> / Thesis / Master of Applied Science (MASc)
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