The state assignment is one of the most important problems in hardware implementation of controllers (finite state machines, FSMs). Traditional heuristics include simulated annealing (SA), greedy approach, and recursive Min-Cut partitioning. Since these methods can¡¦t reduce both area and power, thus we propose a new approach which using integer linear programming (ILP) to solve the state assignment. The proposed of ILP approach can set the weight and reach best solution between less area and low power. The approach can find out the best state assignment for both low-area and low power consumption. In addition, we also use ILP to solve the output encoding of controller in order to reduce the power consumption of datapath. Finally, to verify the effectiveness of our proposed approach, we do some experiments on several MCNC FSM benchmarks and controller-datapath systems. The experimental results show that a significant power and area savings can be achieved.

In this thesis, we propose a low voltage low power wide-tuning 4th-order butterworth low-pass OTA-C channel selection filter. It is implemented by using TSMC 0.35£gm 2P4M CMOS technology. The drain voltage of triode-biased input transistors of the OTA is regulated through an active-cascode loop for low power and wide-tuning range. The Gm-C channel selection filter can be programmed from 0.5 to 12MHz. The OTA also employs a circuit to reduce the OTA output current in a high transconductance mode and the total power consumption of filter is suppressed below 3mW.

Three improved operational amplifiers with low voltage and rail-to-rail constant are proposed. Two of the amplifiers are modified from the amplifier with a level shifting circuit. One improved amplifier has fewer devices, higher speed, and reduced area and the other improved amplifier is added an additional adjustable gain. The third amplifier is a floating voltage controlled voltage source (FVCVS) amplifier, which has reduced area and improved frequency response. The first two level shifting operational amplifiers are designed in a 0.5£gm UMC CMOS process. They use about half number of devices. The supply voltage is 1.3V, and the current consumes just only 22.6¢H of the original circuits. The unity gain frequency increases 56.8%. The slew rate, CMRR and PSRR are higher. The 2nd amplifier still has a rail-to-rail constant gm; however, the gm can be adjusted. The third amplifier uses the 0.35£gm UMC CMOS process with 1.2V operating voltage. The gain-bandwidth product is 53.8¢H larger than the original circuits. No frequency compensation is used and the devices are fewer. The results are obtained in HSPICE simulation.

In this thesis, we develop an automatic hardware synthesizer for multiplier-based arithmetic functions such as parallel multipliers/multiplier-accumulator/inner-product calculator. The synthesizer is divided into two major phases. In the first phase called pre-layout netlist generation, the synthesizer generates the gate-level verilog codes and the corresponding test fixture file for pre-layout simulation. The second phase, called layout-generation, is to produce the CIF file of final physical layout based on the gate-level netlist generated in the first phase. The thesis focuses on the first phase. The irregular connection of the Wallace tree in the parallel multiplier is optimized in order to reduce the overall delay and power. In addition to the conventional 3:2 couter that is usually included in standard cell library, our synthesizer can select other different compression elements that are full-custom designed using pass-transistor logic. We also propose several methods to partition the final addition part of the parallel multiplier into several regions in order to further reduce the critical path delay and the area cost. Thus, our multiplier generator combines the advantages of three basic design approaches: high-level synthesis, cell-based design and full-custom design along with area and power optimization.

This thesis includes two topics. The first topic is a data dispatcher design of a digital image processor for plasma display panels, which can be used in a 42-inch plasma display panel (PDP). The second one is a low-power small-area digital I/O cell design. The data dispatcher is applied to a 42-inch panel, which is produced by AUO corporation, as a test platform. It comprises FPGAs and RAMs to carry out data dispatching. The solution is verified to provide a better image quality, while the cost is also reduced. Regarding the low-power small-area digital I/O cell, we propose a totally different concept in contrast to traditional I/O cells. It is focused on low power consumption and small area. The proposed design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The power consumption is measured to be at least 51.4% less than prior works. The area is proven to be at least 44% more efficient.

Microprocessors are used in a variety of systems ranging from high-performance super computers running scientific applications to battery powered cell phones performing realtime tasks. Due to the large disparity between processor clock speed and main memory access time, most modern processors include several caches, which consume more than half of the total chip area and power budget. As the performance gap between processors and memory has increased, the trend has been to increase the size of the on-chip caches. However, increasing the cache size also increases its access time and energy consumptions. This growing power dissipation problem is making traditional cooling and packaging techniques less effective thus requiring cache designers to focus more on architectural level energy efficiency than performance alone. The goal of this thesis is to propose a new cache architecture and to evaluate its efficiency in terms of miss rate, system performance, energy consumption, and area overhead. The proposed architecture employs the use of a few Ternary-CAM (TCAM) cells in the tag array to enable dynamic compression of tag entries containing contiguous values. By dynamically compressing tag entries, the number of entries in the tag array can be reduced by 2N, where N is the number of tag bits that can be compressed. The architecture described in this thesis is applicable to any cache structure that uses Content Addressable Memory (CAM) cells to store tag bits. To evaluate the effectiveness of the TCAM Enhanced Cache Architecture for a wide scope of applications, two case studies were performed ?? the L2 Data-TLB (DTLB) of a high-performance processor and the L1 instruction and data caches of a low-power embedded processor. Results indicate that a L2 DTLB implementing 3-bit tag compression can achieve 93% of the performance of a conventional L2 DTLB of the same size while reducing the on-chip energy consumption by 74% and the total area by 50%. Similarly, an embedded processor cache implementing 2-bit tag compression achieves 99% of the performance of a conventional cache while reducing the on-chip energy consumption by 33% and the total area by 10%.

A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate with very low duty cycle due to limited energy. Ideally these sensor networks will be massive in size and dense in order to promote redundancy. In addition the networks will be collectively intelligent and adaptive. To achieve these goals, distributed sensor networks will require very small,inexpensive nodes that run for long periods of time on very little energy. One component of such network nodes is an A/D converter. An ADC acts as a crucial interface between the sensed environment and the sensor network as a whole. The work presented here focuses on moderate resolution, and moderate speed, but ultra-low-power ADCs. The 6 bit current-mode algorithmic pipelined ADC reported here consumes 8 pJ/bit samples at 0.65V supply and 130 kS/s. The current was chosen as the information carrying quantity instead of voltage as it is more favorable for low-voltage and low-power applications. The reference current chosen was 150nA. All the blocks are using transistors operating in subthreshold or weak inversion region of operation, to work in low-voltage and low current supply. The DNL and INL plots are given in simulation results section. The area of the overall ADC was 0.046 mm2 only.

This thesis presents a delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-controlled delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-controlled delay line. By using multi-band technology the proposed DLL can provide wider range and lower jitter compared to those of other methods. Frequency can be ranged from 250MHz to 900MHz is using TSMC 0.18um process with 1.8V supply voltage. The other implement is using UMC 90nm 1P9M CMOS process with 1V supply voltage. The frequency can be ranged from 33MHz to 300MHz.

Energy consumption will reduce the battery life time and increase the weight and cost of mobile devices. Low-power design methods become an important issue of SOC. Until now, there is no commercial power estimates software in system-level. Users must add power estimation to SystemC simulation environment by themselves. In this paper, we proposed a system-level power estimation framework. Users can use their custom power model, and add power estimation automatically. The proposed framework separates the SystemC simulation environment and power estimation into two independent procedures. First, we generate a data collection SystemC module automatically based on the parameters set up by users. This data collection module will automatically collect the information of parameters from SystemC simulation environment, and send these information to power estimation program. Power estimation program will calculate power consumption according to these parameters and formulas set by user. Users can add power estimation to their SystemC simulation environment quickly and use our framework to analysis the power consumption of their SOC system to find improvement issues. Users can use of our framework to compare and analyze various low-power design methods. In this paper, we applied our framework to estimate the power consumption of a 3D graphics SOC to authenticate the functional and practical ability of our framework.

Floating-point multipliers are typically power hungry which is undesirable in many embedded applications. This paper proposes a variable-latency floating-point multiplier architecture, which is suitable for low-power, high-performance, and high-accuracy applications. The architecture splits the significand multiplier into upper and lower parts, and predicts the required significand product and sticky bit from upper part. In the case of correct prediction, the computation of lower part is disabled and the rounding operation is significantly simplified so that floating-point multiplication can be completed early. Finally, detailed design and simulation of the floating-point multiplier is presented, together with its evaluation by comparing power consumption with the fast and conventional floating-point multipliers. Experimental results demonstrate that the proposed double-precision multiplier consumes up to 26.41% and 24.97% less power and energy than the fast floating-point multiplier respectively at the expense of only small area and delay overhead. In addition, the results also show that the performance of proposed floating-point multiplier is very approximate to that of fast floating-point multipliers.