This thesis presents detail theoretical analysis of downconversion Gilbert cell mixer with the improvements on major performance parameters by utilizing different substrate biasing techniques. By modifying the threshold voltage of the switching core, the LO transistors perform more ideally as a perfect switch. It improves the active mixer performances in conversion gain, noise and linearity performances. The techniques are implemented on a 1.2 V low power CMOS downconversion mixer for performance comparisons between simulation and measurements result. They are realized in TSMC 0.18 um CMOS technology. It shows that body-biasing techniques help to increase the switching efficiency of the Gilbert mixer. And a mixer with a better switching provides better performance. With no additional power consumption, the no body effect technique in Design B has shown a 1.5 dB higher in conversion gain, 2 dBm higher in IIP3, and a 0.5 dB lower in NF performance. With the varying biasing technique implemented in Design C, it shows an improvement of 22 dB in conversion gain. Both Design B and C have less than 2 mW power consumption and are suitable for Bluetooth applications. This thesis introduces a stage-by-stage procedure for designing a Gilbert mixer; design tradeoffs at each stage are also discussed. / Thesis / Master of Applied Science (MASc)

Smart antenna technology is a promising means to overcome signal impairments in wireless personal communications. When spatial signal processing achieved through smart antennas is combined with temporal signal processing, the space-time processing can mitigate interference and multipath to yield higher network capacity, coverage, and quality. In this dissertation, we propose a dual smart antenna system incorporated into handsets for the third generation wireless personal communication systems in which the two antennas are separated by a quarter wavelength (3.5 cm). We examine the effectiveness of a dual smart antenna system with diversity and adaptive combining schemes and propose a new combining scheme called hybrid combining. The proposed hybrid combiner combines diversity combiner and adaptive combiner outputs using maximal ratio combining (MRC). Since these diversity combining and adaptive combining schemes exhibit somewhat opposite and complementary characteristics, the proposed hybrid combining scheme aims to exploit the advantages of the two schemes. To model dual antenna signals, we consider three channel models: loosely correlated fading channel model (LCFCM), spatially correlated fading channel model (SCFCM), and envelope correlated fading channel model (ECFCM). Each antenna signal is assumed to have independent Rayleigh fading in the LCFCM. In the SCFCM, each antenna signal is subject to the same Rayleigh fading, but is different in the phase due to a non-zero angle of arrival (AOA). The LCFCM and the SCFCM are useful to evaluate the upper and the lower bounds of the system performance. To model the actual channel of dual antenna signals lying in between these two channel models, the ECFCM is considered. In this model, two Rayleigh fading antenna signals for each multipath are assumed to have an envelope correlation and a phase difference due to a non-zero AOA. To obtain the channel profile, we adopted not only the geometrically based single bounce (GBSB) circular and elliptical models, but also the International Telecommunication Union (ITU) channel model. In this dissertation, we also propose a new generalized selection combining (GSC) method called minimum selection GSC (MS-GSC) and an adaptive rake combining scheme to reduce the power consumption of mobile rake receivers. The proposed MS-GSC selects a minimum number of branches as long as the combined SNR is maintained larger than a given threshold. The proposed adaptive rake combining scheme which dynamically determines the threshold values is applicable to the three GSC methods: the absolute threshold GSC, the normalized threshold GSC, and the proposed MS-GSC. Through simulation, we estimated the effectiveness of the proposed scheme for a mobile rake receiver for a wideband CDMA system. We also suggest a new power control strategy to maximize the benefit of the proposed adaptive scheme. / Ph. D.

Over the past couple decades, the capabilities of battery-powered electronics has expanded dramatically. What started out as large bulky 2-way radios, wristwatches, and simple pacemakers, has evolved into pocket sized smart-phones, digital cameras, person digital assistants, and implantable biomedical chips that can restore hearing and prevent heart attacks. With this increase in complexity comes an increase in the amount of processing, which runs on a limited energy source such as a battery or scavenged energy. It is therefore desirable to make the hardware as energy efficient as possible. Many battery-powered systems require digital signal processing, which often makes up a large portion of the total energy consumption. The digital signal processing of a battery-powered system is therefore a good target for power reduction techniques. One method of reducing the power consumption of digital signal processing is to operate the circuit in the subthreshold region, where the supply voltage is lower than the threshold voltage of the transistors. Subthreshold operation greatly reduces the power and energy consumption, but also decreases the maximum operating frequency. Many digital signal processing applications have real-time throughput requirements, so various architectural level techniques, such as pipelining and parallelism, must be used in order to achieve the required performance. This thesis investigates the use of parallelization and subthreshold operation to lower the power consumption of digital signal processing applications, while still meeting throughput requirements. Using an off the shelf fast fourier transform architecture, it will be shown that through parallelization and subthreshold operation, a 70% reduction in power consumption can be achieved, all while matching the performance of a nominal voltage single core architecture. Even better results can be obtained when an architecture is specifically designed for subthreshold operation. A novel Discrete Wavelet Transform architecture is presented that is designed to eliminate the need for memory banks, and a power reduction of 26x is achieved compared to a reference nominal voltage architecture that uses memory banks. Issues such as serial to parallel data distribution, dynamic throughput scaling, and memory usage are also explored in this thesis. Finally, voltage scaling greatly increases the design space, so power and timing analysis can be very slow due long SPICE simulation times. A simulation framework is presented that can characterize subthreshold circuits accurately using only fast gate level design automation tools. / Master of Science

Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external events. During this time, they are expending energy, using up battery life. Increasing power consumption is a rising concern to users and researchers alike. Power gating, turning off a blocks of hardware when idle, reduces static power consumption. The Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) currently employed in processors leak current. Even in power gated circuits, MOSFET power gating may only save between 60-80% of power. A different type of switch, a Nanoelectromechanical Systems (NEMS) switch, presents an air gap between the source and drain while in the off state, eliminating subthreshold leakage current. The NEMS switch is slower to operate and only has a finite number of switching before breaking. They should be switched with caution. Proposed in this thesis is a hybrid power gating model wherein a MOSFET is placed in series with a NEMS switch. Power gating the Floating Point Unit (FPU) of a processor is studied through the use of modern open source computer architecture simulators. Each switch type is used to model power gating to observe energy savings and performance costs. The hybrid power gating model is more flexible across a variety of applications. Energy savings are comparable to single NEMS switch power gating for applications with low FPU activity. Any performance loss remains low, matching that of MOSFETs. Processor electrical costs are heavily reduced while devices remain operating at a near-optimal speed. / Master of Science

According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This causes an exponential increase of the available area, and hence,the complexity of modern digital designs. This consistent enormous gross challenges different research areas in Electronic Design Automation (EDA). Thus, various EDA applications such as equivalence checking, model checking, Automatic Test Pattern Generation (ATPG), functional Bi-decomposition, and technology mapping need to keep pace with these challenges. In this thesis, we are concerned with improving the quality and performance of different EDA algorithms particularly in area of hardware verification and synthesis. First, we introduce algorithms to manipulate Reduced Ordered Binary Decision Diagrams (ROBDD) on multi-core machines. In order to perform multiple BDD operations concurrently, our algorithm uses a breadth-first search (BFS). As ROBDD algorithms are memory-intensive, maintaining locality of data is an important issue. Therefore, we propose the usage of Hopscotch hashing technique for both Unique Table and BFS Queues to improve the construction time of ROBDD on the parallel platform. Hopscotch hashing technique not only improves the locality of the manipulating data, but also provides a way to cache recently performed BDD operation. Consequently, The time and space usage can be traded off. Secondly, we used static implications to enhance the performance of SAT-based Bounded Model Checking (BMC) problem. we propose a parallel deduction engine to efficiently utilize low-cost off-shelf multi-core processors to compute the implications. With this engine, we can significantly reduce the computational processing time in analyzing the deduced implications. Secondly, we formulate the clause filter problem as an elegant set-covering problem. Thirdly, we propose a novel greedy algorithm based on the Johnson's algorithm to find the optimal set of clauses that would accelerate BMC solution. Thirdly, we proposed a novel synthesis paradigm to achieve timing-closure called Timing-Aware CUt Enumeration (TACUE). In TACUE, optimization is conducted through three aspects: First, we propose a new divide-and-conquer strategy that generates multiple sub-cuts on the critical parts of the circuit. Secondly, cut enumeration have been applied in two cutting strategies. In the topology-aware cutting strategy, we preserve the general topology of the circuit by applying TACUE in only self-contained cuts. Meanwhile, the topology-masking cutting strategy investigates circuit cuts beyond their current topology. Thirdly, we proposed an efficient parallel synthesis framework to reduce computation time for synthesizing TACUE sub-cuts. We conducted experiments on large and difficult industrial benchmarks. Finally, we proposed the first scalable SAT-based approaches for Observability Dont Care (ODC) clock gating. Moreover we intelligently choose those inductive invariants candidates such that their validation will benefit the purpose in clock-gating-based low-power design. / Ph. D.

Motion estimation and motion compensation comprise one of the most important compression methods for video communications. We propose a low-power design of a motion estimation block for a low bit-rate video codec standard H.263. Since the motion estimation is computationally intensive to result in large power consumption, a low-power design is essential for portable or mobile systems. Our block employs the Four-Step Search (4SS) method as its primary algorithm. The design and the algorithm have been optimized to provide adequate results for low-quality video at low-power consumption. The model is developed in VHDL and synthesized using a 0.35 um CMOS library. Power consumption of both gate-level circuits and memory-accesses have been considered. Gate-level simulation shows the proposed design offers a 38% power reduction over a "baseline" implementation of a 4SS model and a 60% power reduction over a baseline Three-Step Search (TSS) model. Power savings through reduction of memory access is 26% over the TSS model and 32% over the 4SS model. The total power consumption of the proposed motion estimation block ranges from 7 - 9 mW and is dependent on the type of video being motion estimated. / Master of Science

Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this thesis, we investigated an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Furthermore, the RSD cyclic algorithm is insensitive to offsets, allowing simple, low-power comparators. Our ADC is implemented in a 0.35 um CMOS technology with a single-ended 3.3 V power supply. Our ADC has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average of 10 percent less power when the resolution is decreased by two bits. Simulation results indicate our ADC achieves a bit rate of 1.7 MHz and has a SNR of 84 dB for the maximum input frequency of 8.3 kHz. / Master of Science

Considerable attention has been paid to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM. In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler generates an SRAM layout based on a given SRAM size, input by the user, with the option of choosing between fast vs. low-power SRAM. Array partitioning is used to partition the SRAM into blocks in order to reduce the total power consumption. Experimental results show that the low-power SRAM is capable of functioning at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20 MHz. In this report, we discuss the implementation of the SRAM compiler from the basic component to the top-level SKILL code functions, as well as simulation results and discussion. / Master of Science

In the last few years Wireless Sensor Networks (WSNs) have become an interesting field of research mainly due to the challenges and constraints of their design and the broad range of potential applications they can provide. One of the most important constraints is the limited energy resources of the sensor nodes that directly influences the design of the Medium Access Control (MAC) layer, as it is the responsible of controlling the transceiver that is the most consuming component of a sensor node. In this thesis the limitations of preamble sampling, one of the most well-known MAC protocols for WSNs, have been studied. Moreover, a new approach, called Low power listening with Wake up after Transmissions MAC (LWT-MAC), has been designed with the goal to overcome preamble sampling limitations while maintaining its reduced energy consumption and simplicity. The performance results obtained have shown that the LWT-MAC protocol is able to significantly improve the performance of WSNs. / Les xarxes de sensors sense fils han esdevingut una interessant àrea de recerca degut als reptes que presenta el seu disseny i a la gran quantitat d’aplicacions potencials que poden proporcionar. Un dels principals problemes d’aquestes xarxes és la limitació en els recursos energètics dels nodes sensors, cosa que afecta directament al disseny del nivell Medium Access Control (MAC), degut a què és el responsable de controlar la ràdio, el component de major consum energètic d’un node sensor. En aquesta tesi s’estudien les limitacions d'un dels protocols MAC per xarxes de sensors més conegut: preamble sampling. A més, s’ha dissenyat un nou protocol, anomenat Low power listening with Wake up after Transmissions MAC (LWT-MAC), amb l’objectiu de reduir les limitacions de preamble sampling però mantenint el seu baix consum energètic i la seva simplicitat. Els resultats obtinguts mostren que el protocol LWT-MAC és capaç de millorar de forma significativa el rendiment de la xarxa.

Bevielio jutiklių tinklo valdymo protokolas. Baigiamasis magistro darbas elektronikos inžinerijos laipsniui. Vilniaus Gedimino technikos universitetas. Vilnius, 2009, 63 p., 27 iliustr., 13 lent., 23 bibl., 3 priedų. Baigiamojo magistro darbo tikslas – sukurti ir ištirti energijos išteklius taupantį protokolą, skirtą jutiklių duomenims perduoti bevieliu būdu. Išanalizuoti skirtingų protokolo konfigūracijų ir funkcionalumo įtaką jutiklio veikimo laikui iš riboto energijos šaltinio. Protokolą sukurti pagal iš anksto užsibrėžtus kriterijus bendradarbiaujant su UAB „Teltonika“. Sukurtas bevielio jutiklių tinklo protokolas veikia IEEE 802.15.4 standarto pagrindu ir atitinka visas reikalaujamas specifikacijas. Jis pasižymi sparčiu naujų jutiklių tinkle tapatumo nustatymu, sumaniais energijos taupymo sprendimais, lanksčiu konfigūravimu, priklausomai nuo norimų charakteristikų ir funkcionalumo bei turi patogią programų sąsają. Dinaminis neveikos (angl. sleep) režimo laiko parinkimas leidžia jutikliams veikti iki 2 metų (esant tam tikromis sąlygomis ir ilgiau) iš ribotos energijos (1,5 Wh) maitinimo šaltinio. / Wireless sensors network protocol. Final Master Work of electronics engineering degree. Vilnius Gediminas Technical University. Vilnius, 2009, 63 p., 27 illustrations. 13 tables., 23 bibliographical sources, 3 appendixes. The main aim of this project is to create and explore low power, energy-efficient protocol for wireless sensors, to analyze the different protocol configurations and the impact on the sensor lifetime of different system functionality using limited energy power source. Protocol designed to meet specified technical criteria in cooperation with the "Teltonika" Inc. Wireless sensors network protocol is based on IEEE 802.15.4 standard and meets all required specifications. Main protocol advantages are: fast new sensor authentication, smart battery management solutions, flexible configuration, depending on the desired characteristics and functionality and a convenient software interface. Dynamic sleep mode time selection allows the sensors to operate for up to 2 years (and more, under certain conditions) from the limited energy (1.5 Wh) power source.