No description available.

The IoT sensing system plays an important role in the field of the smart city. IoT devices are generally constrained nodes due to their limited power and memory. How to save energy has been a challenge for the scalability of sensing networks. Previous studies introduce the dynamic sink and three dynamic sink deployment strategies. It has been proved by simulation experiments that the sensing network with dynamic sinks can reduce energy consumption. Further investigations on new dynamic sink deployment strategies are needed to explore the full potential of dynamic sinks. This work investigates three new deployment strategies, namely Determinisitic Strategy, Prediction Strategy, and Improved Prediction Strategy. We design experiments with different scenarios and evaluate the packet delivery ratio (PDR) and power consumption performances using emulated IoT devices on the Cooja simulator. The results show that the setups with these three new deployment strategies have good performance in terms of PDR and power consumption. Furthermore, we compare the performance difference between these three new strategies. The Improved Prediction Strategy has advantages over the other two strategies and has application prospects in reality. / IoT-baserade sensorsystem spelar en viktig roll för smarta städer. IoT-enheter är i allmänhet begränsade noder vad gäller till exempel kraftförsörjning och minnesutrymme. Hur man kan spara energi har varit en utmaning för skalbarheten hos sensornätverk. I tidigare studier introduceras dynamiska sänknoder och tre strategier för utplacering av sådana sänknoder. Det har visat sig genom simuleringsexperiment att ett nätverk med dynamiska sänknoder kan minska energiförbrukningen. Ytterligare undersökningar av nya strategier för utplacering av sänknoder behövs för att utforska den fulla potentialen hos dynamiska sänknoder. I det här arbetet undersöks tre nya strategier, nämligen Determinisitic Strategy, Prediction Strategy och Improved Prediction Strategy. Vi utformar experiment med olika scenarier och utvärderar andelen levererade paket (Packet Delivery Ration", PDR) och energiförbrukningen med hjälp av emulerade IoT-enheter i Cooja-simulatorn. Resultaten visar att uppställningarna med dessa tre nya strategier har bra prestanda när det gäller PDR och energiförbrukning. Dessutom jämför vi prestandaskillnaden mellan dessa tre nya strategier. Improved Prediction Strategy har fördelar jämfört med de andra två strategierna och bedöms ha goda tillämpningsmöjligheter i verkliga miljöer.

Master of Science / Department of Electrical and Computer Engineering / Don M. Gruenbacher / As semiconductor technologies advance, the smallest feature sizes that can be fabricated get smaller. This has led to the development of high density FPGAs capable of supporting high clock speeds, which allows for the implementation of larger more complex designs on a single chip. Over the past decade the technology market has shifted toward mobile devices with low power consumption at or near the top of design considerations. By reducing power consumption in FPGAs we can achieve greater reliability, lower cooling cost, simpler power supply and delivery, and longer battery life. In this thesis, FPGA technology is discussed for the design and commercial implementation of low power systems as compared to ASICs or microprocessors, and a few techniques are suggested for lowering power consumption in FPGA designs. The objective of this research is to implement some of these approaches and attempt to design a low power signal acquisition module. Designing for low power consumption without compromising performance requires a power-efficient FPGA architecture and good design practices to leverage the architectural features. With various power conservation techniques suggested for every stage of the FPGA design flow, the following approach was used in the design process implementation: the switching activity is addressed in the design entry, and synthesis level and software tools are utilized to get an initial estimate of and optimize the design’s power consumption. Finally, the device choice is made based on its features that will enhance the optimization achieved in the previous stages; it is configured and real time board level power measurements are made to verify the implementation’s efficacy

Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn and Balasubramaniam Natarajan / This thesis presents an energy harvesting wireless sensor network (EHWSN) architecture customized for use within a space suit. The contribution of this research spans both physical (PHY) layer energy harvesting transceiver design and appropriate medium access control (MAC) layer solutions. The EHWSN architecture consists of a star topology with two types of transceiver nodes: a powered Gateway Radio (GR) node and multiple energy harvesting (EH) Bio-Sensor Radio (BSR) nodes. A GR node works as a central controller to receive data from BSR nodes and manages the EHWSN via command packets; low power BSR nodes work to obtain biological signals, packetize the data and transmit it to the GR node. To demonstrate the feasibility of an EHWSN at the PHY layer, a representative BSR node is designed and implemented. The BSR node is powered by a thermal energy harvesting system (TEHS) which exploits the difference between the temperatures of a space suit's cooling garment and the astronaut's body. It is shown that through appropriate control of the duty-cycle in transmission and receiving modes, it is possible for the transceiver to operate with less than 1mW power generated by the TEHS. A super capacitor, energy storage of TEHS, acts as an energy buffer between TEHS and power consuming units (processing units and transceiver radio). The super capacitor charges when a BSR node is in sleep mode and discharges when the node is active. The node switches from sleep mode to active mode whenever the super capacitor is fully charged. A voltage level monitor detects the system's energy level by measuring voltage across the super capacitor. Since the power generated by the TEHS is extremely low(less than 1mW) and a BSR node consumes relatively high power (approximately 250mW) during active mode, a BSR node must work under an extremely low duty cycle (approximately 0.4%). This ultra-low duty cycle complicates MAC layer design because a BSR node must sleep for more than 99.6% of overall operation time. Another challenge for MAC layer design is the inability to predict when the BSR node awakens from sleep mode due to unpredictability of the harvested energy. Therefore, two feasible MAC layer designs, CSA (carrier sense ALOHA based)-MAC and GRI (gateway radio initialized)-MAC, are proposed in this thesis.

The prospect of replacing existing fixed networks with cheap, flexible and evenmobile low-power wireless network has been a strong research driver in recent years.However, many challenges still exist: reliability is hampered by unstable and burstycommunication links; the wireless medium is getting congested by an increasingnumber of wireless devices; and life-times are limited due to difficulties in developingefficient duty-cycling mechanisms. These challenges inhibit the industry to fullyembrace and exploit the capabilities and business opportunities that low-powerwireless devices offer. In this thesis, we propose, design, implement, and evaluateprotocols and systems to increase flexibility and improve efficiency of low-powerwireless communications. First, we present MobiSense, a system architecture for energy-efficient communicationsin micro-mobility sensing scenarios. MobiSense is a hybrid architecturecombining a fixed infrastructure network and mobile sensor nodes. Simulations andexperimental results show that the system provides high throughput and reliabilitywith low-latency handoffs. Secondly, we investigate if and how multi-channel communication can mitigate theimpact of link dynamics on low-power wireless protocols. Our study is motivated bya curiosity to reconcile two opposing views: that link dynamics is best compensatedby either (i) adaptive routing, or (ii) multi-channel communication. We perform acomprehensive measurement campaign and evaluate performance both in the singlelink and over a multi-hop network. We study packet reception ratios, maximumburst losses, temporal correlation of losses and loss correlations across channels.The evaluation shows that multi-channel communication significantly reduces linkburstiness and packet losses. In multi-hop networks, multi-channel communicationsand adaptive routing achieves similar end-to-end reliability in dense topologies,while multi-channel communication outperforms adaptive routing in sparse networkswhere re-routing options are limited. Third, we address the problem of distributed information exchange in proximitybasednetworks. First, we consider randomized information exchange and assess thepotential of multi-channel epidemic discovery. We propose an epidemic neightbordiscoverymechanism that reduces discovery times considerably compared to singlechannelprotocols in large and dense networks. Then, the idea is extended todeterministic information exchange. We propose, design and evaluate an epidemicinformation dissemination mechanism with strong performance both in theory andpractice. Finally, we apply some of the concepts from epidemic discovery to the designof an asynchronous, sender-initiated multi-channel medium access protocol. Theprotocol combines a novel mechanism for rapid schedule learning that avoids perpacketchannel negotiations with the use of burst data transfer to provide efficientsupport of ’multiple contending unicast and parallel data flows. / De senaste åren har forskning inom trådlös kommunikation drivits av önskemåletom att kunna ersätta nuvarande trådbundna kommunikationslänkar med trådlösa lågenergialternativ.Dock kvarstår många utmaningar, såsom instabila och sporadiskalänkar, överbelastning på grund av en ökning i antal trådlösa enheter, hur maneffektivt kan växla duty-cycling mekanismen för att förlänga nätverkens livstid,med flera. Dessa utmaningar begränsar industrin från att ta till sig och utnyttjade fördelar som trådlösa lågenergialternativ kan medföra. I den här avhandlingenföreslår, designar, implementerar och utvärderar vi protokoll och system som kanförbättra de nuvarande trådlösa lågenergialternativen. Först presenterar vi MobiSense, en systemarkitektur för energibesparande kommunikationi mikro-mobila sensorscenarier. MobiSense är en hybridarkitektur somkombinerar ett fast infrastrukturnätverk med rörliga sensornoder. Simulerings- ochexperimentella resultat visar att systemet uppnår en högre överföringskapacitet ochtillförlitlighet samtidigt som överlämnandet mellan basstationer har låg latens. I den andra delen behandlar vi hur effekterna från länkdynamiken hos protokollför lågenergikommunikation kan minskas, och försöker förena idéerna hos två motståendesynsätt: (i) flerkanalskommunikation och (ii) adaptiv routing. Vi analyserarenkanals- och flerkanalskommunikation över en-stegslänkar i termer av andelenmottagna paket kontra andelen förlorade, den maximala sporadiska förlusten avpaket, tidskorrelation för förluster och förlustkorrelation mellan olika kanaler. Resultatenindikerar att flerkanalskommunikation med kanalhoppning kraftigt minskardet sporadiska uppträdandet hos länkarna och korrelationen mellan paketförluster.För flerstegsnätverk uppvisar flerkanalskommunikation och adaptiv routingliknande tillförlitlighet i täta topologier, medan flerkanalskommunikation har bättreprestanda än adaptiv routing i glesa nätverk med sporadiska länkar. I den tredje delen studeras distribuerat informationsutbyte i närhetsbaseradenätverk. Först betraktas det slumpmässiga fallet och vi fastställer potentialen hosflerkanalig indirekt utforskning av nätverket. Vi analyserar ett trestegs protokoll,som möjliggör en snabbare utforskning av nätverket. Sedan föreslår vi en ny algoritmför att upptäcka grannarna i ett flerkanalsnätverk, som kraftigt minskarutforskningstiden i jämförelse med ett enkanalsprotokoll. Vi utökar även problemettill det deterministiska fallet och föreslår en mekanism för informationsspridningsom påskyndar utforskningstiderna för deterministiska protokoll. Utvidgningen hartvå huvudförbättringar som leder till kraftigt ökad prestanda samtidigt som degaranterar att utforskningsprocessen är deterministisk. Till sist applicerar vi koncepten rörande indirekt utforskning för att designa,implementera och evaluera ett asynkront sändare-initierat flerkanals MAC protokollför trådlös lågenergikommunikation. Protokollet kombinerar en ny mekanism försnabbt lärande av tidsschemat, vilket undviker kanalförhandling för varje paket,med sporadisk dataöverföring. Detta möjliggör ett effektivt tillhandahållande avflera konkurrerande och parallella dataflöden. / <p>QC 20151204</p>

Power consumption is a critical issue for portable devices. The ever-increasing demand for multimode wireless applications and the growing concerns towards power-aware green technology make dynamically reconfigurable hardware an attractive solution for overcoming the power issue. This is due to its advantages of flexibility, reusability, and adaptability. During the last decade, reconfigurable analog-to-digital converters (ReADCs) have been used to support multimode wireless applications. With the ability to adaptively scale the power consumption according to different operation modes, reconfigurable devices utilise the power supply efficiently. This can prolong battery life and reduce unnecessary heat emission to the environment. However, current adaptive mechanisms for ReADCs rely upon external control signals generated using digital signal processors (DSPs) in the baseband. This thesis aims to provide a single-chip solution for real-time and low-power ReADC implementations that can adaptively change the converter resolution according to signal variations without the need of the baseband processing. Specifically, the thesis focuses on the analysis, design and implementation of a low-power digital controller unit for ReADCs. In this study, the following two important reconfigurability issues are investigated: i) the detection mechanism for an adaptive implementation, and ii) the measure of power and area overheads that are introduced by the adaptive control modules. This thesis outlines four main achievements to address these issues. The first achievement is the development of the switching activity measurement (SWAM) method to detect different signal components based upon the observation of the output of an ADC. The second achievement is a proposed adaptive algorithm for ReADCs to dynamically adjust the resolution depending upon the variations in the input signal. The third achievement is an ASIC implementation of the adaptive control module for ReADCs. The module achieves low reconfiguration overheads in terms of area and power compared with the main analog part of a ReADC. The fourth achievement is the development of a low-power noise detection module using a conventional ADC for signal improvement. Taken together, the findings from this study demonstrate the potential use of switching activity information of an ADC to adaptively control the circuits, and simultaneously expanding the functionality of the ADC in electronic systems.

I propose compact models of single-gate (SG) and double-gate (DG) JFETs predicting the current-voltage characteristics for both long and short channel devices. In order to make the current equation continuous through all operating conditions from subthreshold to well-above threshold, without non-physical fitting parameters, mobile carriers in depletion region are considered. For describing the short channel behavior, relevant parameters extracted from the two-dimensional analytical solution of Poisson's equation are used for modifying long channel equations. Comparisons of models with the numerical simulation showing close agreement are presented. Based on models, merits of DG JFET over SG JFET and SG MOSFET are discussed by examining the schematic circuit diagram describing the relation between gate and channel potentials for each device. / text

In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variation. A strategy to derive the optimal buffer size and the optimal tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variations. Using HSPICE simulations based on the high performance 32nm ASU Predictive Model, we show that up to 30% average power reduction can be achieved for a SRAM word-line decoder while maintaining the same timing yield. / text

Low power and Lossy Networks (LLNs) such as wireless sensor networks are currently used in many important applications fields such as remote environment monitoring and target tracking. This deployment has been enabled by the availability, especially in recent years, of embedded micro-controller devices that are smaller and cheaper. These devices are equipped with wireless interfaces, with which they can communicate with each other to form a network. In this thesis we focus on studying the energy consumption of reliable transport protocols over LLNs. Recently, much research has been carried out to improve the reliability and the congestion control on low power networks. Some of these works have considered TCP inappropriate for this kind of networks. Indeed, the idea of deploying TCP was rejected due to its header overhead, its end-to-end retransmission mechanism, its large rate of acknowledgment, and the impact of the lower layers fragmentation on the energy consumption. Nonetheless, the use of standard TCP/IP protocols offers the advantage of a seamless connectivity between the wireless network and the Internet. TCP allows easily the use of standard applications (HTTP, SSH) for some tasks like reprogramming of nodes or firmware updates, without the need of deploying complex proxies in border routers. In the first part of this work, we study the energy consumption of TCP and the ways that reduce its energy consumption. We study one of the proposed TCP algorithms to reduce the end-to-end retransmissions cost and we propose some improvements that allow it to reduce the energy consumption. Then, we study the compression of the TCP header over low-power and lossy networks and we consider IPv6 over Low power Wireless Personnel Area Networks (6LoWPAN) as an example. We propose a new TCP header compression algorithm that reduces the TCP header size to about six bytes. In the second part, we propose a mathematical model that allows to estimate the energy consumption of wireless nodes. Using the model, we study the tradeoff between sending long and short TCP segments and their impact on the energy consumption. Finally, we study the impact of a new fragment recovery mechanism on the energy performance of TCP.

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel. / Graduation date: 2012