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41	Simulator for optimizing performance and power of embedded multicore processors Goska, Benjamin J. 26 April 2012 (has links) This work presents improvements to a multi-core performance/power simulator. The improvements which include updated power models, voltage scaling aware models, and an application specific benchmark, are done to increase the accuracy of power models under voltage and frequency scaling. Improvements to the simulator enable more accurate design space exploration for a biomedical application. The work flow used to modify the simulator is also presented so similar modifications could be used on future simulators. / Graduation date: 2012 Low power digital SIMD Multicore Digital simulation Power modeling
42	Performance enhancement techniques for low power digital phase locked loops Elshazly, Amr 16 July 2014 (has links) Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014 Phase locked loops Delay locked loops Supply noise mitigation background calibration Digital PLL Supply noise Time to digital converter TDC Switched ring oscillator SRO-TDC Digital circuits Low power Area efficient Digitally controlled oscillator Performance enhancement techniques Integrated circuits Frequency synthesizers Clock multipliers Integrated circuits Microelectronics Analog and mixed Circuits and systems Analog Digital Solid state circuit Phase-locked loops Electronic noise -- Prevention Low voltage systems Frequency synthesizers

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Simulator for optimizing performance and power of embedded multicore processors

Performance enhancement techniques for low power digital phase locked loops