In this work, a highly linear broadband Low Noise Amplifier (LNA) is presented. The linearity issue in broadband Radio Frequency (RF) front-end is introduced, followed by an analysis of the specifications and requirements of a broadband LNA through consideration of broadband, multi-standard front-end design. Metal-Oxide- Semiconductor Field-Effect Transistor (MOSFET) non-linearity characteristics cause linearity problems in the RF front-end system. To solve this problem, feedback and the Derivative Superposition Method linearized MOSFET. In this work, novel linearization approaches such as the constant current biasing and the Derivative Superposition Method using a triode region transistor improve linearization stability against Process, Supply Voltage, and Temperature (PVT) variations and increase high power input capability. After analyzing and designing a resistive feedback LNA, novel linearization methods were applied. A highly linear broadband LNA is designed and simulated in 65nm CMOS technology. Simulation results including PVT variation and the Monte Carlo simulation are presented. We obtained -10dB S11, 9.77dB S21, and 4.63dB Noise Figure with IIP3 of 19.18dBm for the designed LNA.

This thesis consists of two parts. Part one includes the design procedure and implementation of the building blocks for an RF tuner module used in the Digital Video Broadcasting ¡V Terrestrial ¡]DVB-T¡^system. It contains the comparison of several RF tuner architectures, frequency planning, and link-budget analysis. Measurement results for the designed tuner operating in the frequency range from 50 to 860 MHz show that the maximum power gain ranges from 49 to 57.6 dB. The entire range for gain control is over 60 dB. In the maximum gain state, the noise figure ranges form 6.8 to 11.5 dB, the output third-order interception point¡]OIP3¡^ranges from 11.7 to 13.8 dBm, and the image rejection is over 50 dB. By applying the simplified single-carrier modulation signals, the tuner can pass the DVB-T system specifications with respect to the adjacent-channel and overlapping-channel protection ratios. In part two, an RFIC design for low-noise variable-gain amplifier that can be used in the RF front end of DVB-T system is presented. It operates from 100 to 900 MHz and dissipates 59.4 mW under a 3.3-V power supply. In the maximum gain state, measurement results for this RFIC show that the noise figure is less than 4 dB, the maximum gain is more than 14 dB, and the OIP3 is about 6.8dBm. The entire gain control range is over 40 dB.

This thesis proposes a modified inductively degenerated common-emitter low-noise amplifier. To add a series-shunt feedback capacitance in series to the base of the cascode transistor for increasing the load impedance of the common-emitter transistor and enhancing the Miller effect, it is applied to improve the circuit¡¦s performance. By thoroughly studying the Miller effect for the input matching, noise, and linearity analysis and derivation of the modified structure, the theoretical analysis and experiments demonstrate the improved linearity and well noise performance. In addition, the proposed method is presented with the good figure of merit. The proposed method is presented in a hybrid circuit with the NEC 2S5010 NPN transistor for 900 MHz applications. It demonstrates that this method improves the linearity and the figure of merit has been increased by 50 to 70 percent. Moreover, the novel low noise amplifier is designed with a 0.35£gm SiGe BiCMOS process supported by the TSMC for 5.7 GHz WLAN band applications. It is found that the circuit has the characteristic of IM3 nonlinearity cancellation because the cascode transistor eliminates the third-order intermodulation genaerated by the common-emitter transistor. This thesis establishes a realizable method for high-linearity low-noise amplifier.

The objective of this thesis is aimed at the design of low noise amplifier (LNA) for an ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. A two amplified stage topology is proposed in the low noise amplifier. The first stage introduces inductively source degeneration and resistive-feedback, it can achieve wideband input impedance matching. The second stage introduces traditional CS configuration, it can improve the forward gain (S21). The second stage also used L-C section for output match. In order to improve the gain at high frequency, we introduces the series peaking between the first stage and second stage. The total power dissipation of the low noise amplifier is about 24.3mW at power supply 1.5 volt and the chip size is 1.283*1.008mm2. The simulated result shows that S11 is under -8dB, S22 is under -10dB, the forward gain S21 is 12.6dB~15.3dB at 3.1-10.6GHz, the reverse isolation S12 is under -30dB, and the noise figure is 3.24dB~4.84dB.

<p>In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components.</p><p>Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach.</p><p>The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.</p>

<p>In this thesis, three different types of low-noise amplifiers (LNA’s) have been designed using a 0.25 mm SiGe BiCMOS process. Firstly, a single-stage amplifier has been designed with 11 dB gain and 3.7 dB noise figure at 8 GHz. Secondly, a cascode two-stage LNA with 16 dB gain and 3.8 dB noise figure at 8 GHz is also described. Finally, a cascade two-stage LNA with a wide-band RF performance (a gain larger than unity between 2-17 GHz and a noise figure below 5 dB between 1.7 GHz and 12 GHz) is presented. </p><p>These SiGe BiCMOS LNA’s could for example be used in the microwave receivers modules of advanced phased array antennas, potentially making those more cost- effective and also more compact in size in the future. </p><p>All LNA designs presented in this report have been implemented with circuit layouts and validated through simulations using Cadence RF Spectre.</p>

Στη διπλωματική αυτή εργασία περιγράφεται η σχεδίαση και η υλοποίηση σε πλακέτα (PCB) ενός Ultra Wideband Low Noise Amplifier (UW-LNA) με περιοχή λειτουργίας 3.1- 10.6 GHz. Ο ενισχυτής αυτός αποτελεί το σημαντικότερο κομμάτι ενός δέκτη σε ό,τι α- φορά τη θορυβική συμπεριφορά του τελευταίου. / In this diploma thesis we designed an Ultra Wideband Low Noise Amplifier (UW-LNA), operating in the band of frequencies between 3.1-10.6 GHz. The LNA has also been implemented on a PCB. The LNA is the most important component of a receiver as far as the noise behavior is concerned.

Αντικείμενο αυτής της διπλωματικής εργασίας είναι ο σχεδιασμός ενός αναλογικού ενισχυτικού κυκλώματος χαμηλού θορύβου το οποίο θα λειτουργεί σε υψηλές συχνότητες. Ο ενισχυτής αυτός προορίζεται για χρήση στο analog front end κυκλωμάτων τα οποία θα υποστηρίζουν πρωτόκολλα μεταφοράς πληροφορίας σε δίκτυα ισχύος (Power Line Communication, Internet of Things). Για τον σχεδιασμό γίνεται η χρήση της κλασικής θεωρίας μικροηλεκτρονικών κυκλωμάτων αλλά και της μικροκυματικής θεωρίας. Παρουσιάζονται οι διάφορες τοπολογίες των τρανζίστορ BJT, γίνεται μία παρουσίαση των βασικότερων πηγών θορύβου και αναφέρονται βασικές αρχές των S παραμέτρων και της προσαρμογής εμπέδησης. Ο ενισχυτής κοινού εκπομπού απορρίφθηκε καθώς αποδείχθηκε αμφίπλευρος οπότε καταλήξαμε στην επιλογή της cascode τοπολογίας η οποία προσδίδει ευστάθεια, απομόνωση και καλή γραμμικότητα. Η απόλυτη προδιαγραφή που τέθηκε για το θόρυβο δεν επιτεύχθηκε και οπότε αναφέραμε τους λόγους που οδήγησαν σε αυτό και προτείναμε πιθανές λύσεις μέσω άλλων υλοποιήσεων. / The subject of this diploma thesis is the design of a low noise high-frequency analogue amplifier. The amplifier is designed to be used in the analog front end of circuits designed to support protocols that control the transmission of information over power lines (internet of things). To achieve this goal we make use of classic microelectronics theory but also microwave theory. The topologies of the BJT transistors are presented, we also go through the basic noise production reasons and we also make a short reference on the s-parameters and on the basic principles of impedance matching. The common emitter amplifier proved to be bilateral, so the cascode amplifier, which provides stability, isolation and linearity, was preferred. The noise specification was not achieved so we present the basic reasons of this, as well as we propose possible solutions.

The goal of this work is to extend the state-of-the-art in digital medical X-ray imaging as it pertains to real-time, low-noise imaging and multi-mode imager functionality. One focus of this research in digital flat-panel imagers is to increase the detective quantum efficiency, particularly at low X-ray exposures, in order to enable low-noise imaging applications such as fluoroscopy or tomographic mammography. Another focus of this research is in the creation of a multi-mode imager, such as a combined radiographic and fluoroscopic (R&F) imager, which will reduce hospital costs, both in terms of equipment acquisition and storage space. To that end, we propose a novel three-transistor multi-mode digital flat-panel imager with a dynamic range capable for use in R&F applications, with a particular focus on noise optimization for low-noise real-time digital flat-panel X-ray fluoroscopy. This work involves the derivation and optimization of the total input referred noise of an active pixel sensor (APS) in terms of the on-pixel thin-film transistor device dimensions. It is determined that in order to minimize noise, all non-transistor capacitances at the pixel sense node needed to be minimized. This leads to a design where the on-pixel storage capacitance is eliminated; and instead the gate capacitance of the sense-node transistor is used to store the incoming X-ray converted charge. This work allows researchers to gain insight into the fundamental noise operation of active pixels used in medical imaging, and to appropriately choose device dimensions. Due to the inherent large feature sizes of thin-film transistors, active pixel flat-panel X-ray medical imagers offer lower resolution than their film-screen counterparts. By demonstrating the desirability of smaller device dimensions for reduced noise and the elimination of a storage capacitor, this research frees some of the area constraints that exist in active pixel flat-panel imagers, allowing for smaller pixels, and thus higher resolution medical imagers. The noise analysis and optimization as a function of pixel TFT device dimensions in this work is applicable to any amorphous silicon (a-Si) based charge-sensitive pixel, and is easily extended to other device technologies such as polysilicon (poly-Si). iv In addition, experimental results of a 64x64 pixel four-transistor APS imaging array fabricated in a-Si technology and mated with an a-Se photoconductor for use in medical X-ray imaging is presented. MTF results and transient response in the presence of X-rays (image lag) for the APS array are poor, which is ascribed to high charge trapping at the silicon nitride/a-Se interface. Improvements to the silicon nitride passivation layer and pixel layout are suggested to reduce this charge trapping. The prototype imager is compared directly with a state-of-the-art a-Si PPS imaging array and demonstrates good SNR performance for X-ray exposures down to 1.5μR. Pixel design and fabrication process improvements are suggested for low-exposure APS testing and improved low-noise performance.

In this thesis, three low-noise active mixing circuits are presented in CMOS technology. Mixers can be found at the front-end of almost every communication systems. However, despite many advantages the active mixers have, one drawback is their poor noise performance. One mixer that has been widely used in integrated circuit is the Gilbert cell. This thesis demonstrated that by merging the low-noise amplifier (LNA) with the Gilbert cell, a low-noise active mixer can be realized. This kind of mixer relaxes the front-end design, allows higher circuit integration, and reduces power consumption. The first circuit is a narrowband low-noise mixer that operates at 5.4 GHz in 0.18 um CMOS. An inductive degenerated LNA is used as the transconductor. Together with a current bleeding circuit, a gain of 13.1 dB and a low 7.8 dB single-sideband noise figure are achieved. The circuit was fabricated and measured. Simulation and measurement results are compared and discussed. The second circuit is a broadband low-noise mixer that operates between 1 and 5.5 GHz in 0.13 um CMOS. The noise-cancelling technique is used to design the transconductors. This technique does not require the use of inductors while able to achieve a sub 3 dB noise figure and input matching over a large bandwidth. To further extend the mixer bandwidth, the series inductive peaking was used. Measured and simulated results showed great agreement. It has a high gain of 17.5 dB, a bandwidth of 4.5 GHz, and a low average double-sideband noise figure of 3.9 dB. This mixer has the best broadband noise performance ever reported in CMOS. Finally, a double-balanced low-noise self-oscillating mixer (SOM) in 0.13 um CMOS is presented. This is a current-reuse, highly integrated circuit that combines an LNA, mixer, and oscillator seamlessly into a single component. The oscillator generates the required LO while serving as the mixer load simultaneously. Measured and simulated results showed excellent agreement. A low double-sideband noise figure of 4.4 dB and a gain of 11.6 dB were measured. This type of SOM and loading structure are the first ever reported. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2009-08-23 12:41:20.445