A redução das dimensões dos dispositivos semicondutores para escalas submicrométricas impõe diversos desafios no projeto de circuitos integrados. O impacto das variações intrínsecas afetando parâmetros elétricos cresce em importância à medida que a área dos dispositivos adentra a faixa nanométrica. Dentre essas variações estão flutuações nas tensões e correntes de terminal causadas pelas diferentes formas de ruído intrínseco dos dispositivos MOS. Este trabalho apresenta um estudo sobre o impacto do ruído elétrico no desempenho de circuitos MOS. Um novo modelo para simulação do Random Telegraph Signal (RTS) no domínio do tempo é utilizado. Uma metodologia de simulação para contabilizar o ruído térmico em simulações transientes também é proposta. A partir desses modelos de simulação de dispositivos, o trabalho de pesquisa analisa o impacto da variabilidade de parâmetros elétricos em nível de circuito. As simulações focam na caracterização da pureza espectral em osciladores em anel de sinal diferencial. Diversas topologias são apresentadas e posteriormente comparadas em termos do jitter no período de oscilação. / The shrinking of semiconductors devices dimensions to submicron scales introduces many challenges in integrated circuit design. The impact of intrinsic variability affecting electrical parameters increases in importance as transistors enter the nanometric range. Among these variations are fluctuations in terminal voltages and currents caused by different forms of intrinsic noise of MOS devices A new model for Random Telegraph Signal (RTS) simulation in time-domain is utilized. A simulation methodology to account for thermal noise effects in transient simulations is also proposed. Using these simulation models, this research work analyses the impact of electrical noise at circuit level. The simulations focus on the characterization of spectral purity in differential ring oscillators. Different topologies are presented and compared in terms of jitter in the period of oscillation.

Les transistors organiques attirent actuellement beaucoup d'attention en raison des avantages uniques par rapport à leur homologue inorganique. En revanche, la compréhension physique du fonctionnement et du transport des porteurs de charge est très limitée. L'objectif de cette thèse est de contribuer à apporter une meilleure compréhension des transistors organiques. Le Chapitre 1 présente les semi-conducteurs organiques : le mécanisme de conduction, les paramètres essentiels, les matériaux typiques etc. Le Chapitre 2 discute des transistors organi-ques en termes de structures, de mécanismes de fonctionnement, de paramètres principaux et des procédés de fabrication. Le Chapitre 3 étudie la caractérisation statique. Après les méthodes classiques, la méthode de la fonc-tion Y est introduite. Subséquemment, des techniques pour extraire les paramètres principaux sont présentées sé-parément. Enfin, les résultats expérimentaux sur nos échantillons sont exposés. Sur la base des données mesurées, les travaux de modélisation sont présentés dans le chapitre 4. Premièrement, une solution de l'équation Poisson est introduite qui donne la distribution de potentiel et donc la distribution de porteurs dans le film organique. Avec la prise en compte des pièges, les résultats obtenus par simulation sont en bon accord avec les données expérimen-tales. A partir de mesures des caractéristiques de courant –tension effectuées à basse température, on propose une procédure d'analyse de la mobilité en utilisant l'intégrale de Kubo-Greenwood. Ensuite, prenant en compte la dis-tribution de porteurs dans le film organique, une solution de l'équation de Poisson est donnée et la mobilité effec-tive est calculée en fonction de la tension de grille et de la température. Le Chapitre 5 est consacré à l'analyse du bruit à basse fréquence. On étudie d'abord le bruit du canal où une domination du bruit provenant des contacts est observée. En conséquence, une méthode TLM pour l'extraction du bruit des contacts est présentée. Ensuite, un procédure d'analyse des sources de bruit dû au contact est aussi proposée. Les résultats de bruit obtenus sur des transistors organiques de différentes origines sont également discutés à la fin. / Organic transistors recently attract much attention because of their unique advantages over the conventional inorganic counterparts. However, the understanding of their operating mechanism and the carrier transport process are still very limited, this thesis is devoted to such a subject. Chapter 1 presents the organic semiconductors regarding carrier transport, parameters, typically applied materials. Chapter 2 describes the issues related to organic transistors: structure, operating mechanism, principal parameters and fabrication technologies. Chapter 3 deals with the static properties characterization. The commonly used methods are firstly presented and then the Y function method is introduced. Afterwards, the characterization methods for principles parameters are separately discussed. The experimental results on our organic transistors are finally described. Chapter 4 focuses on the mod-eling on the basis of the experimental data, regarding DC characteristics modeling with a solution for Poisson's equation, carrier mobility modeling with using Kubo-Greenwood integral as well as a theoretical analysis of OFETs' carrier mobility involving a solution of Poisson's equation. Chapter 5 analyzes the low-frequency noise in organic transistors. One firstly addresses the channel noise sources and then concentrates on the contact noise extraction and contact noise sources diagnosis. The noise measurements on other samples are also presented.

A redução das dimensões dos dispositivos semicondutores para escalas submicrométricas impõe diversos desafios no projeto de circuitos integrados. O impacto das variações intrínsecas afetando parâmetros elétricos cresce em importância à medida que a área dos dispositivos adentra a faixa nanométrica. Dentre essas variações estão flutuações nas tensões e correntes de terminal causadas pelas diferentes formas de ruído intrínseco dos dispositivos MOS. Este trabalho apresenta um estudo sobre o impacto do ruído elétrico no desempenho de circuitos MOS. Um novo modelo para simulação do Random Telegraph Signal (RTS) no domínio do tempo é utilizado. Uma metodologia de simulação para contabilizar o ruído térmico em simulações transientes também é proposta. A partir desses modelos de simulação de dispositivos, o trabalho de pesquisa analisa o impacto da variabilidade de parâmetros elétricos em nível de circuito. As simulações focam na caracterização da pureza espectral em osciladores em anel de sinal diferencial. Diversas topologias são apresentadas e posteriormente comparadas em termos do jitter no período de oscilação. / The shrinking of semiconductors devices dimensions to submicron scales introduces many challenges in integrated circuit design. The impact of intrinsic variability affecting electrical parameters increases in importance as transistors enter the nanometric range. Among these variations are fluctuations in terminal voltages and currents caused by different forms of intrinsic noise of MOS devices A new model for Random Telegraph Signal (RTS) simulation in time-domain is utilized. A simulation methodology to account for thermal noise effects in transient simulations is also proposed. Using these simulation models, this research work analyses the impact of electrical noise at circuit level. The simulations focus on the characterization of spectral purity in differential ring oscillators. Different topologies are presented and compared in terms of jitter in the period of oscillation.

A redução das dimensões dos dispositivos semicondutores para escalas submicrométricas impõe diversos desafios no projeto de circuitos integrados. O impacto das variações intrínsecas afetando parâmetros elétricos cresce em importância à medida que a área dos dispositivos adentra a faixa nanométrica. Dentre essas variações estão flutuações nas tensões e correntes de terminal causadas pelas diferentes formas de ruído intrínseco dos dispositivos MOS. Este trabalho apresenta um estudo sobre o impacto do ruído elétrico no desempenho de circuitos MOS. Um novo modelo para simulação do Random Telegraph Signal (RTS) no domínio do tempo é utilizado. Uma metodologia de simulação para contabilizar o ruído térmico em simulações transientes também é proposta. A partir desses modelos de simulação de dispositivos, o trabalho de pesquisa analisa o impacto da variabilidade de parâmetros elétricos em nível de circuito. As simulações focam na caracterização da pureza espectral em osciladores em anel de sinal diferencial. Diversas topologias são apresentadas e posteriormente comparadas em termos do jitter no período de oscilação. / The shrinking of semiconductors devices dimensions to submicron scales introduces many challenges in integrated circuit design. The impact of intrinsic variability affecting electrical parameters increases in importance as transistors enter the nanometric range. Among these variations are fluctuations in terminal voltages and currents caused by different forms of intrinsic noise of MOS devices A new model for Random Telegraph Signal (RTS) simulation in time-domain is utilized. A simulation methodology to account for thermal noise effects in transient simulations is also proposed. Using these simulation models, this research work analyses the impact of electrical noise at circuit level. The simulations focus on the characterization of spectral purity in differential ring oscillators. Different topologies are presented and compared in terms of jitter in the period of oscillation.

Avec la diminution constante des dimensions des dispositifs électroniques, les structures MOS font face à de nombreux effets physiques liés à la miniaturisation. Dans le but de maintenir le rythme d'intégration indiqué par la loi de Moore, des nouvelles technologies, dont la structure résiste plus à ces effets physiques, remplacerons le transistor MOSFET bulk. Les modèles physiques permettant de prédire le comportement des transistors MOS atteignent rapidement leurs limites quand ils sont appliqués à ces structures émergentes. Ce travail de thèse est consacré au développement des modèles numériques et analytiques dédiés à la caractérisation des nouvelles architectures SOI et à substrat massif. Nous nous focalisons sur la modélisation du courant de drain basée sur le potentiel de surface, ainsi qu'à la modélisation du comportement en bruit basse fréquence de ces nouveaux dispositifs. Nous proposons un modèle explicite décrivant les potentiels de surface avant et arrière d'une structure SOI. Nous développons ensuite un modèle de bruit numérique et analytique permettant de caractériser les différents oxydes d'une structure FD SOI. La dernière partie de ce mémoire est consacrée à l'étude d'une nouvelle architecture du transistor MOS sur substrat massif. Une caractérisation de la conduction électrique de ce dispositif et de son comportement en bruit basse fréquence sont présentés / With the continuous reduction of the size of MOS devices, various associated short channel effects become significant and limit this scaling. To restrain this limit, multi-gate MOSFET devices seem to be more interesting, thanks to their better control of the gate on the channel. These new devices seem to be good candidates to replace the classical MOS architecture. The existing physical models used to predict the behaviour of MOSFET bulk devices are limited when they are applied to these emerging structures. This thesis is devoted to the development of numerical and analytical models dedicated to the characterization of new SOI architectures and bulk devices. We focus on the modeling of the drain current based on the surface potential as well was the modeling of the low frequency noise behaviour of these devices. We propose an explicit model describing the front and back surface potential of a FD SOI structure. We then develop numerical and analytical low frequency noise models allowing the characterization of the different oxides of a FD SOI structure. The last part of this thesis is devoted to the study of a new architecture of bulk MOS transistors. A characterization of the electrical conduction of this device and its low frequency noise behavior are presented

Gallium Nitride (GaN) high electron mobility transistors (HEMT) have superior performance characteristics compared to Silicon (Si) and Gallium Arsenide (GaAs) based transistors. GaN is a wide bandgap semiconductor which allows it to operate at higher breakdown voltages and power. Unlike traditional semiconductor devices, the GaN HEMT channel region is undoped and relies on the piezoelectric effect created at the GaN and Aluminum Gallium Nitride (AlGaN) heterojunction to create a conduction channel in the form of a quantum well known as the two dimensional electron gas (2DEG). Because the GaN HEMTs are undoped, these devices have higher electron mobility crucial for high frequency operation. However, over time and use these devices degrade in a manner that is not well understood. This research utilizes low frequency noise (LFN) as a method for analyzing changes and degradation mechanisms in GaN-on-Si devices due to gate stress. LFN is a useful tool for probing different regions of the device that cannot be measured through direct means. LFN generation in GaN HEMTs is based on the carrier fluctuation theory of 1/f noise generation which states fluctuations in the number of charge carriers results in conductance fluctuations that produce a Lorentzian noise spectrum. The summing Lorentzian noise spectra from multiple traps leads to 1/f and random telegraph signal (RTS) noise. The primary cause of carrier fluctuations are electron traps near the 2DEG and in the AlGaN bulk. These traps occur naturally due to dislocations and impurities in the manufacturing process, but new traps can be generated by the inverse-piezoelectric effect during gate stress. This thesis introduces noise and presents a circuit to bias the devices and measure gate and drain LFN simultaneously. Three measurements are performed before and after gate DC stress at three different temperatures: DC characterization, capacitance-voltage (C-V) measurements, and LFN measurements. The DC characteristics show an increase in gate leakage after stress caused by an increase in traps after degradation consistent with trap assisted tunneling. However, the leakage current on the drain and source side differ before and after stress leading to the conclusion that the source side of the gate is more sensitive to gate stress. Gate leakage current on the drain side is also sensitive to temperature due to thermionic trap assisted tunneling. Hooge parameter calculations agree with previous research. The LFN results show an increase in gate and drain noise power, SIg(f) and SId(f), in accordance with increased gate leakage current under cutoff bias. RTS noise is also observed to increase in frequency with increased temperature. Activation energies for RTS noise are extracted and qualitatively linked to trap depth based on the McWhorter trap model.

No description available.

The objective of this doctoral thesis is to study three different innovative noise control techniques in ducts namely: acoustic metamaterials, porous absorbers and microperforates. There has been a lot of research done on all these three topics in the context of duct acoustics. This research will assess the potential of the acoustic metamaterial technique and compare to the use of conventional methods using microperforated plates and/or porous materials.  The objective of the metamaterials part is to develop a physical approach to model and synthesize bulk moduli and densities to feasibly control the wave propagation pattern, creating quiet zones in the targeted fluid domain. This is achieved using an array of locally resonant metallic patches. In addition to this, a novel thin slow sound material is also proposed in the acoustic metamaterial part of this thesis. This slow sound material is a quasi-labyrinthine structure flush mounted to a duct, comprising of coplanar quarter wavelength resonators that aims to slow the speed of sound at selective resonance frequencies. A good agreement between theoretical analysis and experimental measurements is demonstrated. The second technique is based on acoustic porous foam and it is about modeling and characterization of a novel porous metallic foam absorber inside ducts. This material proved to be a similar or better sound absorber compared to the conventional porous absorbers, but with robust and less degradable properties. Material characterization of this porous absorber from a simple transfer matrix measurement is proposed.The last part of this research is focused on impedance of perforates with grazing flow on both sides. Modeling of the double sided grazing flow impedance is done using a modified version of an inverse semi-analytical technique. A minimization scheme is used to find the liner impedance value in the complex plane to match the calculated sound field to the measured one at the microphone positions. / <p>QC 20160923</p>

O Ruído de Baixa Frequência (LFN), tais como o ruído flicker e o Random Telegraph Noise (RTN), são limitadores de performance em muitos circuitos analógicos e digitais. Para transistores diminutos, a densidade espectral de potência do ruído pode variar muitas ordens de grandeza, impondo uma séria limitação na performance do circuito e também em sua confiabilidade. Nesta tese, nós propomos um novo modelo de RTN estatístico para descrever o ruído de baixa frequência em MOSFETs. Utilizando o modelo proposto, pode-se explicar e calcular o valor esperado e a variabilidade do ruído em função das polarizações, geometrias e dos parâmetros físicos do transistor. O modelo é validado através de inúmeros resultados experimentais para dispositivos com canais tipo n e p, e para diferentes tecnologias CMOS. É demonstrado que a estatística do ruído LFN dos dispositivos de canal tipo n e p podem ser descritos através do mesmo mecanismo. Através dos nossos resultados e do nosso modelo, nós mostramos que a densidade de armadilhas dos transistores de canal tipo p é fortemente dependente do nível de Fermi, enquanto para o transistor de tipo n a densidade de armadilhas pode ser considerada constante na energia. Também é mostrado e explicado, através do nosso modelo, o impacto do implante de halo nas estatísticas do ruído. Utilizando o modelo demonstra-se porque a variabilidade, denotado por σ[log(SId)], do RTN/LFN não segue uma dependência 1/√área; e fica demonstrado que o ruído, e sua variabilidade, encontrado em nossas medidas pode ser modelado utilizando parâmetros físicos. Além disso, o modelo proposto pode ser utilizado para calcular o percentil do ruído, o qual pode ser utilizado para prever ou alcançar certo rendimento do circuito. / Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices, the noise power spectral density can easily vary by many orders of magnitude, imposing serious threat on circuit performance and possibly reliability. In this thesis, we propose a new RTN model to describe the statistics of the low frequency noise in MOSFETs. Using the proposed model, we can explain and calculate the Expected value and Variability of the noise as function of devices’ biases, geometry and physical parameters. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS technology nodes. We show that the LFN statistics of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results and model, we show that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We also show and explain, using the proposed model, the impact of the halo-implanted regions on the statistics of the noise. Using this model, we clarify why the variability, denoted by σ[log(SId)], of RTN/LFN doesn't follow a 1/√area dependence; and we demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities. Moreover, the proposed model can be used to calculate the percentile quantity of the noise, which can be used to predict or to achieve certain circuit yield.

No description available.