Earlier designs were driven by the goal of achieving higher performance, but lately, energy efficiency has emerged as an even more important design principle. Strong demand from the consumer electronics drives research in the low power and energy-efficient methodologies. Moreover, with exponential increase in the number of transistors on a chip and with further technology scaling, variability in the design is now of greater concern. Variations can make the design unreliable or the design may suffer from sub-optimal performance. Through the work in this thesis, we present a multi-dimensional investigation into the design of variation aware energy-efficient systems. Our overarching methodology is to use system-level decisions to mitigate undesired effects originating from device-level and circuit-level issues. We first look into the impact of process variation (PV) on energy efficient, scalable throughput many-core DSP systems. In our proposed methodology, we leverage the benefits of aggressive voltage scaling (VS) for obtaining energy efficiency while compensating for the loss in performance by exploiting parallelism present in various DSP designs. We demonstrate this proposed methodology consumes 8% - 77% less power as compared to simple dynamic VS over different workload environments. Later, we show judicious system-level decisions, namely, number of cores, and their operating voltage can greatly mitigate the effects of PV and consequently, improve the energy efficiency of the design. We also present our analysis discussing the impact of aging on the proposed methodology. To validate our proposed system-level approach, design details of a prototype chip fabricated in the 90nm technology node and its findings are also presented. The chip consists of 8 homogeneous FIR cores, which are capable of running from near-threshold to nominal voltages. In the 20-chip population, we observe 7% variation in the speed at nominal voltage (0.9V) and 26% at near threshold voltage (0.55V) among all the cores. We also observe 54% variation in power consumption characteristics of the cores. The chip measurement results show that our proposed methodology of judiciously selecting the cores and their operating voltage can result in 6.27% - 28.15% more energy savings for various workload environments, as compared to globally voltage scaled systems. Furthermore, we present the impact of temperature variations on the energy-efficiency of the above systems. We also study the problem of voltage variations in the integrated circuits. We first present the characteristics of a dynamic voltage noise as measured on a 28nm FPGA. We propose a fully digital on-chip sensor that can detect the fast voltage transients and alert the system of voltage emergency. A traditional approach to mitigate this problem is to use safety guardbands. We demonstrate that our proposed sensor system will be 6% - 27.5% more power efficient than the traditional approach. / Ph. D.

Structural Health Monitoring (SHM) is the technology of monitoring and assessing the condition of aerospace, civil, and mechanical infrastructures using a sensing system integrated into the structure. Among variety of SHM approaches, impedance-based method is efficient for local damage detection. This thesis focuses on system level concerns for impedance-based SHM. Two essential requirements are reached in the thesis: reduction of power consumption of wireless SHM sensor, and compensation of temperature dependency on impedance. The proposed design minimizes power by employing on-board signal processing, and by eliminating power hungry components such as ADC and DAC. The prototype implemented with MSP430 micro controller is verified to be able to handle SHM operation and wireless communication with extremely low-power: 0.15 mW during the inactive mode and 18 mW during the active mode. Each SHM operation takes about 13 seconds to consume 236 mJ. When our ASN-2 operates once in every four hours, it can run for about 2.5 years with two AAA-size batteries. To compensate for temperature change, we proposed an algorithm to select a small subset of baseline profiles for some critical temperatures and to estimate the baseline profile for a given ambient temperature through interpolation. Experimental results show that our method reduces the number of baseline profiles to be stored by 45%, and estimates the baseline profile of a given temperature accurately. / Master of Science

Physical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to create but impossible to duplicate. They offer solutions to many of the FPGA (Field Programmable Gate Array) issues like intellectual property, chip authentication, cryptographic key generation and trusted computing. Moreover, FPGA evolving as an important platform for flexible logic circuit, present an attractive medium for PUF implementation to ensure its security. In this thesis, we explore the behavior of RO-PUF (Ring Oscillator Physical Unclonable Functions) on FPGA when subjected to low voltages. We investigate its stability by applying environmental variations, such as temperature changes to characterize its effectiveness. It is shown with the help of experiment results that the spread of frequencies of ROs widens with lowering of voltage and stability is expected. However, due to inherent circuit challenges of FPGA at low voltage, RO-PUF fails to generate a stable response. It is observed that more number of RO frequency crossover and counter value fluctuation at low voltage, lead to instability in PUF. We also explore different architectural components of FPGA to explain the unstable nature of RO-PUF. It is reasoned out that FPGA does not sustain data at low voltage giving out unreliable data. Thus a low voltage FPGA is required to verify the stability of RO-PUF. To emphasize our case, we look into the low power applications research being done on FPGA. We conclude that FPGA, though flexible, being power inefficient, requires optimization on architectural and circuit level to generate stable responses at low voltages. / Master of Science

The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency, was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software applications to test the architecture performance. The application framework is integrated with the prior automation framework bringing software applications at the right level of abstraction. The processor architecture design is made flexible and scalable, making it suitable for a wide range of applications. Additionally, an embedded flash memory based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory. / Master of Science

Une solution de gestion de puissance d’un système sur puce peut être définie par une architecture de faible puissance composée de multiples domaines d'alimentation et de leur stratégie de gestion. Si ces deux éléments sont économes en énergie, une solution efficace en énergie peut être obtenue. Cette approche nécessite l’ajout d’éléments structurels de puissance et de leurs comportements. Une stratégie de gestion doit respecter les dépendances structurelles et fonctionnelles dues au placement physique des domaines d'alimentation. Cette relation forte entre l'architecture et sa stratégie de gestion doit être analysée tôt dans le flot de conception pour trouver la solution de gestion de puissance la plus efficace. De récentes normes de conception basse consommation définissent des sémantiques pour la spécification, simulation et vérification d’architecture de faible puissance au niveau transfert de registres (RTL). Mais elles manquent une sémantique d’interface de gestion des domaines d'alimentation réutilisable ce qui alourdit l’exploration. Leurs sémantiques RTL ne sont pas aussi utilisables au niveau transactionnel pour une exploration plus rapide et facile. Pour combler ces lacunes, cette thèse étend ces normes et fournit une étude complète des possibilités d'optimisation de puissance basées sur la composition et la gestion des domaines d'alimentation pour des modèles fonctionnels transactionnels utilisant un environnement commun USLPAF. USLPAF comprend une méthodologie alliant conception et vérification des modèles transactionnels de faible consommation, ainsi qu’une bibliothèque de techniques de modélisation et fonctions prédéfinies pour appliquer cette méthodologie. / A SoC power management solution can be defined by a low-power architecture composed of multiple power domains and a power management strategy for power domains states control. If these two elements are energy-efficient, an energy-efficient solution can be obtained. This approach requires inferring power structural elements and their related behavior in the chip internal logic. A strategy adjusting the power domains states must respect structural and functional dependencies due to the physical power domains composition. This strong relationship between power architecture and its management strategy must be explored at early design stages to find the most energy-efficient solution. Low-power design standards have recently enabled low-power architecture exploration starting from the Register Transfer Level (RTL) by defining semantics to specify power architecture, simulate and check its behavior along with the initial functional one. But, these standards miss semantics for reusable power domain control interface making power management strategies exploration tedious. The RTL-based semantics defined by these standards constrain also their use at Transaction-Level of Modeling (TLM) for fast and easy exploration. This dissertation proposes extensions to low-power standards to fill these gaps. It provides a complete study of power optimization opportunities based on composition and management of power domains in Transaction-Level (TL) functional models within a common USLPAF framework. USLPAF includes a methodology that combines design and verification of TL low-power models. To apply this methodology, USLPAF incorporates a library of modeling techniques and built-in features.

A Large instruction window is a key requirement to exploit greater Instruction Level Parallelism in out-of-order superscalar processors. Along with the instruction window size, the size of various other structures including the issue queue, store queue and register file need to increase as well. However, the cycle time and energy consumption of conventional large monolithic Content Addressable Memories (CAMs), the underlying structure of most conventional issue queue and store queue designs, worsen rapidly with an increase in size. This results in a three way trade-off involving ILP, clock frequency and energy consumption. In this thesis, we propose efficient designs for the issue queue and the store queue that improve the circuit latency and energy consumption while minimizing the loss in IPC. We propose the Scalable Low power Issue Queue (SLIQ) design which segments the issue queue structure to reduce the latency. This is complemented with a fast Wakeup index to a consumer in the issue queue for every instruction. As this consumer instruction can be woken up directly, without any delay, this mitigates the IPC loss faced by the pipelined issue queue. Also, as the scheme incorporates a pipelined broadcast, the indices are not required for correctness and can simply be gang invalidated on branch mispredictions. The IPC loss of an 8 segment SLIQ is Within 2.3% for the entire SPEC CPU2000 benchmark suite while achieving a 39.3% reduction in issue latency. Further, in the SLIQ design unnecessary broadcasts to the higher segments are avoided most of the time as in a large majority of the cases, an instruction has a single consumer. This consumer is woken up either by direct indexing or by broadcast in the first segment of the SLIQ. This enables the 8 segment SLIQ to significantly reduce the energy consumption and the energy-delay product by 48.3% and 67.4% respectively on an average. SLIQ also allows the architects to segment the issue queue carefully so that the latency of the issue logic is just within the per pipeline stage latency goals of the design. We also propose the Scalable Low power Store Queue (SLSQ) to address similar problems associated with the store queue data forwarding logic. We extend the state- of-the-art Store Vector based Disambiguator to also predict the index of the store that will forward to a given load. SLSQ marginally adds to the hardware budget, but predicts the store queue index of the store which will forward with an accuracy of 99.5% on an average. SLSQ, thus, eliminates unnecessary address broadcasts and Compares and reduces energy consumption of the store-to-load forwarding logic by 78.4% and 91.6% for the SPEC Int and FP suites respectively. Another variant of SLSQ, eliminates the need for a CAM in the forwarding logic and achieves a 49.9% reduction in store to load data forwarding latency while incurring a minimal IPC loss less than 0.1% on average for the entire SPEC CPU2000 benchmark suite.

Les systèmes intégrés sont aujourd’hui de plus en plus fréquemment confrontés à des contraintes de faible consommation ou d’efficacité énergétique. Ces problématiques se doivent d’être intégrées le plus en amont possible dans le flot de conception afin de réduire les temps de design et d’éviter de nombreuses itérations dans le flot. Dans ce contexte, le projet collaboratif HiCool, partenariat entre les laboratoires LIRMM et TIMA, les sociétés Defacto, Docea et ST Microelectronics, a mis en place une stratégie et un flot de conception pour concevoir des systèmes intégrés faible consommation tout en facilitant la réutilisation de blocks matériels (IPs) existants. L’approche proposée dans cette thèse s’intègre dans cette stratégie en apportant une petite dose d’asynchronisme dans des systèmes complètement synchrones. En effet, la réduction de la consommation est basée sur le constat que l’activation permanente de la totalité du circuit est inutile dans bien des cas. Néanmoins, contrôler l’activité avec des techniques de « clock gating » ou de « power gating » nécessitent usuellement d’effectuer un re-design du système et d’ajouter un organe de commande pour contrôler l’activation des zones effectuant un traitement. Le travail présenté dans ce manuscrit définit une stratégie basée sur des contrôleurs d’horloge et de domaine d’alimentation, asynchrones, distribués et facilement insérables dans un circuit avec un coût de re-design des plus réduit. / Today integrated systems are increasingly faced with the constraints of low consumption or energy efficiency. These issues need to be integrated as far upstream as possible in the design flow to reduce design time and avoid much iteration in the flow. In this context, the collaborative project HiCool, between LIRMM and TIMA laboratories, Defacto, Docea and ST Microelectronics companies, has set up a strategy and design flow to design integrated low power systems while facilitating the reuse of existing hardware blocks (IPs). The approach proposed in this thesis fits into this strategy by bringing a small dose of asynchrony in completely synchronous systems. Indeed, the reduction in consumption is based on the observation that permanent activation of the entire circuit is unnecessary in many cases. However, controlling the activity with techniques of "clock gating" or "power gating" usually need to perform a re-design of the system and to add a control device for controlling activation of areas effecting treatment. The work presented in this manuscript provides a strategy based clock controllers and power domain, asynchronous, distributed and easily insertable into a circuit with a low cost design.

Sensor nodes in a sensor network is power constrained. Transceiver electronics of a node in sensor network consume a good share of total power consumed in the node. The thesis proposes receiver architecture and algorithms which reduces power consumption of the receiver. The work in the thesis ranges from designing low power architecture of the receiver to experimentally verifying the functioning of the receiver. Concepts proposed in the thesis are: Low power adaptive architecture :-A baseband digital receiver design is proposed which changes its sampling frequency and bit-width based on interference detection and SNR estimation. The approach is based on Look-up-table (LUT) in the digital section of the receiver. Interference detector and SNR estimator has been proposed which suits this approach. Settings of different sections of digital receiver changes as sampling frequency and bit-width varies. But, this change in settings ensures that the desired BER is achieved. Overall, the receiver reduces amount of processing when conditions are benign and does more processing when conditions are not favorable. It is shown that the power consumption by the digital baseband can be reduced by 85% (7 times) when there is no interference and SNR is high. Thus the proposed design meets our requirement of low power hardware. The design is coded in Verilog HDL and power and area estimation is done using Synopsys tools. Faster Simulation Methodologies :-Usually physical layer simulations are done on baseband equivalent model of the signal in the receiver chain. Simulating Physical layer algorithms on bandpass signals for BER evaluation is very time consuming. We need to do the bandpass simulations to capture the effect of quantization on bandpass signal in the receiver. We have developed a variance measuring simulation methodology for faster simulation which reduces simulation time by a factor of 10. Low power, Low area, Non-coherent, Non-data-aided joint tracking and acquisition algorithm :-Correlation is a very popular function used particularly in synchronization algorithms in the receivers. But correlation requires usage of multipliers. Multipliers are area and power consuming blocks. A very low power and low area joint tracking and acquisition algorithm is developed. The algorithm does not use any multiplier to synchronize. Even it avoids squaring and adding the signals to achieve non-coherency. Beside the algorithm is non-data-aided as well and does not require ROM to store the sequence. The Algorithm saves area/power of existing similar algorithms by 90%. Experimental setup for performance evaluation of the receiver :-The developed baseband architecture and algorithms are experimentally verified on a wireless test setup. Wireless test setup consists of FPGA board, VSGs, Oscilloscopes, Spectrum analyzer and a discrete component RF board. Packet error and packet loss measurement is done by varying channel conditions. Many practical and interesting issues dealing with wireless test setup infrastructure were encountered and resolved.

The size of the IoT network is expanding due to advancements in the IoT field, leading to increased interest in the multi-sink mechanism. The IPv6 Routing Protocol for Low-Power and Lossy Networks (RPL) is a representative IoT protocol that focuses on the Low-Power and Lossy Networks. However, research on comparing multi-sink strategies within the RPL network is limited. Therefore, this project aims to compare three common strategies: multiple-DODAG in one instance, virtual root, and multiple-instance. Using these strategies, we design and implement RPL networks and conduct simulations in various scenarios. Five different topologies are utilized in the experiments, considering different packet loss rates. Performance evaluation of each strategy is conducted using the Cooja simulator and Contiki-NG system, with a focus on the number of RPL control packets, Packet Delivery Ratio (PDR), and energy consumption. The results indicate that both the virtual root and multiple-DODAG strategies perform well with low packet loss, while the virtual root strategy outperforms the multiple-DODAG strategy with high packet loss. Additionally, the virtual root strategy incurs slightly higher energy costs than the multiple-DODAG strategy. Furthermore, the multiple-instance strategy demonstrates poor performance in most scenarios, except for the packet delivery ratio under high packet loss conditions. Besides the analysis, potential areas for future research on the RPL’s multi-sink mechanism are finally identified. / Storleken på IoT-nätverket expanderar på grund av framsteg inom IoT-området, vilket leder till ökat intresse för multi-sink-mekanismen. IPv6 Routing Protocol for Low-Power and Lossy Networks (RPL) är ett representativt IoT-protokoll som fokuserar på Nät med låg effekt och förluster. Forskningen om jämförelse av multi-sink-strategier inom RPL-nätverket är dock begränsad. Därför syftar detta projekt till att jämföra tre vanliga strategier: multiple - DODAG i en instans, virtuell rot och multi-instans. Med hjälp av dessa strategier designar och implementerar vi RPL-nätverk och genomför simuleringar i olika scenarier. Fem olika topologier används i experimenten, med olika packet loss rate. Prestationsutvärdering av varje strategi utförs med hjälp av Cooja-simulatorn och Contiki-NG-systemet, med fokus på antalet RPL control packets, Packet Delivery Ratio (PDR) och energiförbrukning. Resultaten indikerar att både virtuell rot och multiple-DODAG strategier fungerar bra vid låg datapaketförlust, medan den virtuella rotstrategin överträffar multiple-DODAG strategin vid hög datapaketförlust. Dessutom medför den virtuella rotstrategin något högre energikostnader än flera DODAG-strategin. Dessutom visar multi-instans-strategin dålig prestanda i de flesta scenarier, förutom när det gäller datapaketleveransförhållandet under höga datapaketförlustförhållanden. Utöver analysen identifieras slutligen potentiella områden för framtida forskning om RPL-protokollets multi-sink-mekanism.

Reliability is one of the important issues of recent microprocessor design. Processors must provide correct behavior as users expect, and must not fail at any time. However, unreliable operation can be caused by excessive supply voltage fluctuations due to an inductive part in a microprocessor power distribution network. This voltage fluctuation issue is referred to as inductive or di/dt noise, and requires thorough analysis and sophisticated design solutions. This dissertation proposes an automated stressmark generation framework to characterize di/dt noise effect, and suggests a practical solution for management of di/dt effects while achieving performance and energy goals. First, the di/dt noise issue is analyzed from theory to a practical view. Inductance is a parasitic part in power distribution network for microprocessor, and its characteristics such as resonant frequencies are reviewed. Then, it is shown that supply voltage fluctuation from resonant behavior is much harmful than single event voltage fluctuations. Voltage fluctuations caused by standard benchmarks such as SPEC CPU2006, PARSEC, Linpack, etc. are studied. Next, an AUtomated DI/dT stressmark generation framework, referred to as AUDIT, is proposed to identify maximum voltage droop in a microprocessor power distribution network. The di/dt stressmark generated from AUDIT framework is an instruction sequence, which draws periodic high and low current pulses that maximize voltage fluctuations including voltage droops. AUDIT uses a Genetic Algorithm in scheduling and optimizing candidate instruction sequences to create a maximum voltage droop. In addition, AUDIT provides with both simulation and hardware measurement methods for finding maximum voltage droops in different design and verification stages of a processor. Failure points in hardware due to voltage droops are analyzed. Finally, a hardware technique, floating-point (FP) issue throttling, is examined, which provides a reduction in worst case voltage droop. This dissertation shows the impact of floating point throttling on voltage droop, and translates this reduction in voltage droop to an increase in operating frequency because additional guardband is no longer required to guard against droops resulting from heavy floating point usage. This dissertation presents two techniques to dynamically determine when to tradeoff FP throughput for reduced voltage margin and increased frequency. These techniques can work in software level without any modification of existing hardware. / text