<p>This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.</p><p>The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).</p><p>The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.</p><p>A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.</p><p>When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.</p><p>The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.</p>

This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm. The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF). The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project. A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa. When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s. The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.

Backscatter communication enables wireless communication at a power consumption orders of magnitude lower than conventional wireless communication. Instead of generating new RF-signals backscatter communication leverages ambient signals, such as WiFi-, Bluetooth- or TV-signals, and reflects them by changing the impedance of the antenna. Backscatter communication is known as a short-range communication technique achieving ranges in the order of meters. To improve the communication range, we explore the use of a tunnel diode as an amplifier of the backscattered RF-signal. We developed the amplifier on a PCB-board together with a matching network tuned to give maximum gain at 868 MHz. Our work demonstrates that the 1N3712 tunnel diode can achieve gains up to 35 dB compared to a tag without amplification while having a peak power consumption of 48 μW. With this amplifier the communication distance can be increased by up to two orders of magnitude.

Submitted by Lúcia Brandão (lucia.elaine@live.com) on 2015-12-11T18:22:47Z No. of bitstreams: 1 Dissertação - Rawlinson da Silva Gonçalves.pdf: 25918994 bytes, checksum: 31dbbcde9e265b8281faa9ef25a9b346 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-01-20T15:20:18Z (GMT) No. of bitstreams: 1 Dissertação - Rawlinson da Silva Gonçalves.pdf: 25918994 bytes, checksum: 31dbbcde9e265b8281faa9ef25a9b346 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-01-20T15:23:25Z (GMT) No. of bitstreams: 1 Dissertação - Rawlinson da Silva Gonçalves.pdf: 25918994 bytes, checksum: 31dbbcde9e265b8281faa9ef25a9b346 (MD5) / Made available in DSpace on 2016-01-20T15:23:25Z (GMT). No. of bitstreams: 1 Dissertação - Rawlinson da Silva Gonçalves.pdf: 25918994 bytes, checksum: 31dbbcde9e265b8281faa9ef25a9b346 (MD5) Previous issue date: 2015-07-10 / FAPEAM - Fundação de Amparo à Pesquisa do Estado do Amazonas / Embedded systems have evolved significantly in recent years,mainlyduetoadvances in technology, cost reduction of electronic equipment, and mainly the popularization of mobile devices. Many of these systems require energy resources from battery to maintain the operation of their various components. However, for these devices to have a good autonomy, several techniques and methodologies have been implemented to better manage energy consumption of the system as a whole. This need has contributed to the rise of various lines of research, mainly in the area of real-time systems, where the complicating factor is not only reducing energy consumptionbutalsorespectthetime constraints of all tasks running on the system. Thus, this work aims to maximize energy gains from the use of intra-task dynamic voltage and frequency scaling technique, also known as intra-task DVFS. The proposed online methodology aims to achieve better management of exchanging voltages and frequency of the processor, through a collaborative approach between real-time applications and the operating system. Therefore, both can work together, within the kernel of the system, to reduce the response times of the processor context switches, mainly after preemptions. The experimental results, using the C-Benchmarck, showed that it is possible to decrease about 6% processor power consumption even performing all tasks in the worst case. / Os sistemas embarcados têm evoluído significativamente nos últimos anos, principalmente devido aos avanços da tecnologia, a redução dos custos dos equipamentos eletrônicos e a popularização dos dispositivos móveis. Muitos desses sistemas dependem da energia provenientes de baterias para manter o funcionamento dos seus diversos componentes. No entanto, para que esses dispositivos tenham uma boa autonomia, várias técnicas e metodologias têm sido propostas para melhor gerenciar o consumo de energia do sistema como um todo. Essa necessidade tem contribuído para o surgimento de diversas linhas de pesquisa, principalmente na área de sistemas de tempo real, onde o fator complicante não está somente em reduzir o consumo de energia, mas também em respeitar as restrições temporais de todas as tarefas em execução no sistema. Sendo assim, este trabalho tem como objetivo diminuir o consumo de energia do processador utilizando a técnica de escalonamento dinâmicodetensõesefrequênciasdo processador intra-tarefa, também conhecido como DVFS intra-tarefa (em inglês, Dynamic Voltage and Frequency Scaling). A metodologia online proposta visa realizar ogerenciamentodastrocasdetensõesefrequênciasdoprocessador, através de uma abordagem colaborativa entre as aplicações de tempo real e o sistema operacional. Dessa forma, ambos podem trabalhar em conjunto, dentro do núcleo do sistema, para diminuir os tempos de resposta dos chaveamentos de tensões e frequências do processador, principalmente diante de sucessivas preempções entre as aplicações de tempo real em execução no sistema. Os resultados experimentais dessa metodologia, utilizando o C-Benchmarck, mostraram que é possível diminuircercade6%oconsumo de energia do processador, mesmo executando todas as tarefasnopiorcaso.

Grâce au confort d’utilisation qu’elles procurent, les technologies sans fil se retrouvent aujourd’hui dans un vaste panel d’applications. Ainsi le nombre d’éléments de transmission/réception radio se multiplie. Aujourd’hui pour réduire les consommations des éléments radio, il faut les rendre davantage efficaces notamment pour la partie réception. En effet, pour les communications asynchrones, les récepteurs consomment inutilement de l’énergie à attendre qu’une transmission soit faite. Dans l’objectif de réduire ce gaspillage d’énergie, des nouveaux standards ont vu le jour tel que le Zigbee et le Bluetooth Low Energy. Les performances en consommation procurées par ces deux standards résident sur leur fonction périodique à très faible rapport cyclique. Une nouvelle solution émergente pour réduire drastiquement la consommation des récepteurs en les rendant plus efficaces est l’utilisation de récepteur d’activation. Les récepteurs d’activation ou récepteur de réveil sont des récepteurs simples ce qui leur permet d’atteindre une ultra basse consommation uniquement en charge de guetter l’arrivée d’une trame et de réveiller le récepteur principal, placé en veille au préalable, pour traitement de cette dernière. Le récepteur d’activation proposé ici a été réalisé dans la technologie CMOS 160 nm de NXP. Il offre une sensibilité de -54 dBm, pour une consommation moyenne de 35 μA, prodiguant une portée de 70m à 433,92 MHz pour une puissance de 10 dBm émis. Ce récepteur ASK se distingue des autres récepteurs d’activation par le système de calibration breveté avec ajustement automatique la tension de référence requise pour la démodulation. Ce système rend le circuit robuste au problème d’offset DC et ne consomme aucun courant lorsque le circuit est en écoute. Le récepteur d’activation reconnaît un code de Manchester de 24 bits à 25 kbps, programmable grâce à une interface SPI. / Wireless technologies are now widespread due to the easiness of use they provide. Consequently, the number of radio devices increases. Despite of the efforts to reduce radio circuits power consumption as they are more and more numerous, now they must achieve ultra-low power consumption. Today, radio devices are made more efficient to reduce their power consumption especially for the receiving part. Indeed, for asynchronous communication, a lot of energy is wasted by the receiver waiting for a transmission. In order to avoid this waste, new standards have been created such as Zigbee and Bluetooth Low Energy. Due to periodic operation with ultra-low duty cycle, they provide ultra-low power consumption. Another solution to drastically reduce the power consumption has emerged, wake-up receiver. Wake-up receivers are based in simple architecture to provide ultra-low power consumption, they are only in charge to wait for a frame and when it occurs, wake-up the main receiver put in standby mode before that. The proposed wake-up receiver has been designed in NXP CMOS technology 160 μm. It provides a-54 dBm sensitivity, consuming 35 μA which allows a 70m range considering a 10 dBm emitter at 433,92 MHz. This wake-up receiver operates with ASK modulation, compared to others it provides a smart patented calibration system to get the necessary reference voltage for demodulation. This mechanism provide DC offset robustness and does not drain any current while the wake-up receiver is operating. To wake up the main receiver a 24 bits programmable Manchester code is required. This code at 25 kbps is programmable by the use of an SPI interface.

The work deals with the design and optimization of amplifiers in CMOS technology with low supply voltage and low power consumption. The main aim is to design an amplifier to amplify the biological signal. The first part is a brief introduction to the theory of biological signals. The work also contains a brief description of the biological signal processing methods and their properties. The important part is the description of the methods to reduce the supply voltage of the amplifier. The practical part of this thesis focuses on the design amplifiers with low supply voltage and low power consumption. All active elements and application examples have been verified by PSpice simulator using the 0.18 µm TSMC CMOS parameters. Simulated plots are included in this thesis to illustrate behavior of structures.

OMA’s Lightweight Machine to Machine (LwM2M) is an application protocol for device management in the Internet of Things (IoT) that has been recently published and widely adopted in a lot of projects. The protocol is designed to operate in sensor networks and machine-to-machine environments, where one of the main constraints is the energy consumption since the nodes are usually battery powered. Different strategies to achieve high energy efficiency in IoT networks have been developed, but there is no deep knowledge about the performance of LwM2M operating with them. Moreover, the specification of this protocol includes one strategy, called the Queue Mode, which could be more efficient than the usual ones because it has been specified for this particular protocol. This project aims to implement this Queue Mode at both sides of the communication, and then evaluate its performance by comparing it with TSCH, which is the standard MAC protocol used in IEEE 802.15.4 that defines a way of radio duty cycling. It has been proven to achieve a high energy efficiency, and that is the main reason why it is selected. The comparison is performed according to several metrics to have a comprehensive evaluation, and in different kind of scenarios, with different numbers of IoT devices and different parameters in the communication. The implementation was done inside the Contiki-NG OS for the client side, which is an operating systems designed for constrained devices. For the server side it has been carried out inside the Eclipse Leshan code, which is a LwM2M implementation in Java made by the Eclipse Foundation. As a result of the evaluation, it shown that both implementations operate correctly. This thesis contributes as a guideline for making decisions about which low power strategy is better to use depending on the IoT scenario and the type of application. It shows that for many use cases Queue Mode is a better option than TSCH because it achieves a higher energy efficiency and the rest of the metrics used in the evaluation have also improved values. TSCH has a better performance only in demanding scenarios or in cases where the communication is not produced at fixed time instants. The thesis was developed in cooperation with RISE SICS AB, Networked Embedded Systems Group. / OMA:s Lightweight Machine to Machine (LwM2M) är ett applikationsprotokoll för enhetshantering i Sakernas Internet (IoT) som nyligen har publicerats och börjat användas i många projekt. Protokollet är utformat för att fungera i sensornätverk och maskin-till-maskin miljöer, där en av de viktigaste begränsningarna är energiförbrukningen eftersom noderna vanligtvis är batteridrivna. Olika strategier för att uppnå hög energieffektivitet i sensornätverk har utvecklats, men det finns ingen djup kunskap om hur LwM2M fungerar med dem. Dessutom innehåller specifikationen av LwM2M en strategi kallad Queue Mode (köläge) som kan vara effektivare än de vanliga strategierna eftersom den har utvecklats direkt för det här protokollet.Detta examensarbete syftar till att implementera detta köläge på båda sidor av kommunikationen och sedan utvärdera prestandan genom att jämföra det med TSCH, vilket är ett MAC-protokoll specificerat i IEEE 802.15.4-standarden. Tidigare arbeten har visat att TSCH kan uppnå en låg energiförbrukning, vilket är den främsta anledningen till att detta protokoll väljs ut för att jämföra mot LwM2M:s köläge. Jämförelsen inkluderar flera olika typer av mätvärden och scenarier för att få en omfattande utvärdering, samt med flera olika antal sensor noder och parametrar.Implementationen gjordes för Contiki-NG OS på klientsidan, vilket är ett operativsystem för resursbegränsade IoT-enheter. På serversidan har implementationen gjorts för Eclipse Leshan, vilken är en LwM2M-implementation skriven i Java och publicerad av Eclipse Foundation. Som en följd av utvärderingen har det visat sig att båda implementationerna fungerar korrekt.Detta examensarbete bidrar med riktlinjer för att fatta beslut om vilken energibesparingsstrategi som är bättre att använda beroende på IoT-scenariot och typen av applikation. Utvärderingen visar hur Queue Mode i många användningsfall är ett bättre alternativ än TSCH eftersom det uppnår en högre energieffektivitet utan att de andra typerna av mätvärden påverkas av det. I vissa fall uppnås dessutom förbättrade resultat även i de andra typerna av mätvärden. TSCH har endast bättre prestanda i krävande scenarier eller i fall där kommunikationen inte genereras vid bestämda tillfällen.Examensarbetet har genomförts hos Networked Embedded Systems-gruppen på RISE SICS AB.

L'impédance d'entrée d'une antenne miniature est fortement affectée par des facteurs environnementaux à l'origine de pertes de puissance réduisant l'efficacité énergétique des têtes radiofréquences dans les applications RF, en particulier dans la télémétrie des implants cardiaques. Le but de mes études est de développer une unité de calibration d'impédance d'antenne très faible consommation capable d'adapter toute variation de l'impédance d'entrée de l'antenne à l'impédance de la source radiofréquence. La première partie de mon étude est axée sur la conception au niveau système d'une approche nouvelle de calibration automatique du système. Un réseau d'adaptation automatique d'impédance sans coupleur et fonctionnant de façon directe est étudié et permet d'optimiser la taille du dispositif, la vitesse de l'adaptation, la consommation d'énergie et les performances globales. Deuxièmement, une nouvelle méthode de synthèse du réseau d'adaptation variable est proposée pour réduire fortement la complexité globale de l'algorithme d'adaptation. La troisième partie de mon étude est axée sur la fabrication d'un démonstrateur hybride fonctionnant dans la bande médicale MICS afin de valider le concept auto adaptatif d'impédance. Un banc expérimental qui comprend une antenne immergée dans son milieu connectée au démonstrateur piloté par un microcontrôleur a été mis en place et a permis d'atteindre un coefficient de réflexion jusqu'à -30dB avec un temps de calibration inférieur à 1ms. La dernière partie de mon travail consiste à concevoir le circuit d'adaptation automatique d'impédance d'antenne très faible consommation fonctionnant dans la bande ISM 2.4GHz en utilisant la technologie CMOS 0.13um. Antenna input impedance is highly affected by environmental factors increasing the losses or reducing the power efficiency of the radiofrequency transceiver in many RF applications such as in implantable pacemaker device telemetry. The purpose of my study is to develop a low power fully integrated antenna-impedance tuning unit to match any variation of the antenna impedance to the source. The first part of my study is focused on the system-level design of a new approach to automatically match the system. A couplerless single step automatic matching network is investigated to optimize the die size, the speed, the power consumption and the overall performance. Second, a new method for synthesizing an automatic matching network is developed reducing strongly the overall complexity of the matching algorithm. The third part of my study is focused on the fabrication of a hybrid demonstrator operating at the Medical Implantable Communication Service (MICS) frequency band to validate the concept. An experimental set-up including the antenna tuning unit, a microcontroller and a pacemaker antenna connected to the demonstrator was done achieving a reflection coefficient up to -30dB, an overall tuning time less than 1ms. The last part of my work is to design the entire automatic matching network circuit in 0.13um CMOS technology including a front-end transceiver designed under ultra low power constraints and operating at 2.4GHz ISM frequency band. The additional items overall power consumption is less than 1.5mW under 1.2V supply voltage.

L'impédance d'entrée d'une antenne miniature est fortement affectée par des facteurs environnementaux à l'origine de pertes de puissance réduisant l'efficacité énergétique des têtes radiofréquences dans les applications RF, en particulier dans la télémétrie des implants cardiaques. Le but de mes études est de développer une unité de calibration d'impédance d'antenne très faible consommation capable d'adapter toute variation de l'impédance d'entrée de l'antenne à l'impédance de la source radiofréquence. La première partie de mon étude est axée sur la conception au niveau système d'une approche nouvelle de calibration automatique du système. Un réseau d'adaptation automatique d'impédance sans coupleur et fonctionnant de façon directe est étudié et permet d'optimiser la taille du dispositif, la vitesse de l'adaptation, la consommation d'énergie et les performances globales. Deuxièmement, une nouvelle méthode de synthèse du réseau d'adaptation variable est proposée pour réduire fortement la complexité globale de l'algorithme d'adaptation. La troisième partie de mon étude est axée sur la fabrication d'un démonstrateur hybride fonctionnant dans la bande médicale MICS afin de valider le concept auto adaptatif d'impédance. Un banc expérimental qui comprend une antenne immergée dans son milieu connectée au démonstrateur piloté par un microcontrôleur a été mis en place et a permis d'atteindre un coefficient de réflexion jusqu'à -30dB avec un temps de calibration inférieur à 1ms. La dernière partie de mon travail consiste à concevoir le circuit d'adaptation automatique d'impédance d'antenne très faible consommation fonctionnant dans la bande ISM 2.4GHz en utilisant la technologie CMOS 0.13um. / Antenna input impedance is highly affected by environmental factors increasing the losses or reducing the power efficiency of the radiofrequency transceiver in many RF applications such as in implantable pacemaker device telemetry. The purpose of my study is to develop a low power fully integrated antenna-impedance tuning unit to match any variation of the antenna impedance to the source. The first part of my study is focused on the system-level design of a new approach to automatically match the system. A couplerless single step automatic matching network is investigated to optimize the die size, the speed, the power consumption and the overall performance. Second, a new method for synthesizing an automatic matching network is developed reducing strongly the overall complexity of the matching algorithm. The third part of my study is focused on the fabrication of a hybrid demonstrator operating at the Medical Implantable Communication Service (MICS) frequency band to validate the concept. An experimental set-up including the antenna tuning unit, a microcontroller and a pacemaker antenna connected to the demonstrator was done achieving a reflection coefficient up to -30dB, an overall tuning time less than 1ms. The last part of my work is to design the entire automatic matching network circuit in 0.13um CMOS technology including a front-end transceiver designed under ultra low power constraints and operating at 2.4GHz ISM frequency band. The additional items overall power consumption is less than 1.5mW under 1.2V supply voltage.

La thèse présente le développement de capteurs CMOS pour un futur dosimètre électronique neutrons. A côté des systèmes passifs largement répandus, les dosimètres actifs existants ne donnent pas satisfaction, alors qu’ils sont fermement recommandés par une directive européenne (IEC 1323). Le groupe RaMsEs de l’IPHC développe un nouveau concept de dosimètre électronique personnel neutrons à base de capteurs CMOS. Au cours de cette thèse, le circuit intégré AlphaRad2, à très bas bruit et très faible consommation électrique, a été implémenté dans une technologie commerciale. Il intègre un réseau de micro-diodes sur une surface sensible de 6.55 cm2 avec sa chaîne de traitement sur le même substrat de silicium. Des simulations physiques ont permis d’étudier le processus de collection de charge et d’optimiser l'efficacité de collection. La géométrie du capteur est un compromis entre la collection des électrons secondaires et de la capacité totale du détecteur. Le circuit de lecture comprend un amplificateur de charge (CSA), un circuit de mise en forme (shaper) et un discriminateur pour une réponse digitale. Nous présentons une analyse théorique complète du circuit, les paramètres de dessin, ainsi que des tests électriques et des tests en sources de rayonnement. La sensibilité effective du système est au niveau de la particule unique (proton ou alpha), grâce à un très bon rapport signal à bruit. Une série complète de mesures en sources de photons, de neutrons et de particules chargées a permis de démontrer une bonne efficacité aux neutrons rapides et surtout une excellente réjection gamma grâce à l’application d’un seuil électronique approprié. / This thesis presents the development of CMOS sensors for a future neutron sensitive electronic individual dosemeter. Active dosemeters, exist but do not yet give results as satisfactory as passive devices, being however, mandatory for workers in addition to the passive dosimetry since 1995 (IEC 1323). The RaMsEs group in the laboratory IPHC is exploring a new compact device based on CMOS sensors for operational neutron dosimetry. In this thesis, a dedicated sensor, AlphaRad-2, with low noise and very low power consumption (314 μW), has been implemented in a commercial CMOS technology. The AlphaRad-2 integrates the sensing part made of a micro-diode array of 32×32 n-well/p-epi diodes on a sensitive area of 6.55 mm2 and the signal processing electronics on the same silicon substrate. Device physics simulations have been performed to study the charge collection mechanism in diode matrices, and to optimize the collection efficiency and its time properties. The sensor geometry is a compromise between the collection performance and the total capacitance of the detector. A charge sensitive amplifier (CSA), a shaper, and a discriminator are employed in the readout circuit. We present its theoretical analysis, circuit design, and electrical tests. Our device has a sensitivity at the level of one single secondary charge particle (proton or α) thanks to its excellent noise performance. Extensive measurements to radioactive sources of α-particles, photons, and fast neutrons, have demonstrated good detection efficiency to fast neutrons and excellent γ-rejection through applying an appropriate electronic threshold.