Superconductor-Insulator-Superconductor (SIS) tunnel junction mixers are now commonly used in astronomical receivers at (sub)millimeter wavelengths because of their superb sensitivity, high dynamic range and stability of operation. Niobium SIS mixers operating at frequencies well below the super- conducting gap (∼680 GHz) have already achieved quantum limited sensitivity. Therefore to further enhance the receiver sensitivity, increasing the Intermediate Frequency (IF) bandwidth of SIS mixers has became crucial. This thesis focuses on the theoretical modeling, design and experimental verifi- cation of Nb SIS mixers operating around 230 GHz with a wide IF bandwidth of 1–15 GHz. These mixers were designed for a single baseline heterodyne interferometer (GUBBINS), which is being built to observe the Sunyaev-Zel’dovich effect in the Cosmic Microwave Background. The combination of wide IF bandwidth SIS mixers and complex analogue correlators will allow GUBBINS to feature high surface brightness sensitivity, that helps to distinguish the weak SZ effect from the background noise. The SIS mixer detector system was assembled inside the GUBBINS cryostat together with the IF electronics and RF/LO optical systems. Low noise temperatures of around 71 K were then measured in the GUBBINS system. The Nb SIS mixer we have developed uses a unilateral finline and fully integrated planar circuits deposited on a silicon substrate, to couple the electromagnetic radiation from the waveguide into the SIS junction. The finline mixer allows a broad-band RF coupling, an easy integration of the on-chip planar circuits and an easy-to-fabricate mixer block. To achieve a wide IF bandwidth, the output impedance of the SIS mixer was well matched to the input impedance of the amplifier by a multi-stage microstrip circuit. Additionally, the planar circuit of the SIS mixer was also designed to have a small lumped inductance and capacitance. The SIS mixer chip was extensively simulated by rigorous electromagnetic software (HFSS) and the S-parameter was exported to a quantum mixing package SuperMix to produce a full-wave model of the mixer. Experimental testing yielded a best noise temperature of 50 K with an average noise temperature of 75 K over an RF bandwidth of 160 GHz– 260 GHz. We have performed thorough experimental and computational investigation of the IF system in particular the constraints on the bandwidth caused by the lumped element capacitance of the mixer chip and the matching of the output impedance of the mixer to the IF amplifier. Our conclusion is that a bandwidth of 1–15 GHz could be achieved using our mixer design, subject to the performance of the amplifier. Finally, a variable temperature load system was successfully developed and tested inside the cryostat, to avoid the losses from the room-temperature optics. We have showed that the noise temperature of the SIS detector could be reduced by as much as 15 K by testing the mixer using a variable temperature load inside the cryostat.

This thesis is based on a paper by V. Issakov, presented 2009, where a circuit of a merged power amplifier mixer solution was demonstrated. This work takes that solution and simplifies it for the use at a lower frequency. The implementation target is a Doppler radar application in CMOS that can detect humans in a range of 5 to 15 meters. This could be used as a burglar alarm or an automatic light switch. The report will present the background of Issakov’s work, basic theory used and the implementation of the final design. Simulations will show that the solution presented work, with a 15 dB conversion loss. This design performs well compared to reference mixers. With this report it will be shown that it is possible to make a simple and compact Doppler radar system in CMOS. / Denna avhandling bygger på en artikel av V. Issakov, presenterad 2009, där en lösning för att sammanslå en effektförstärkare med en mixer till en krets visades. Detta arbete tar denna lösning och förenklar det för användning vid en lägre frekvens. Målet är att implementera en dopplerradar i CMOS som kan detektera människor inom ett avstånd på 5 till 15 meter. Denna radar skulle kunna användas som ett inbrottslarm eller en automatisk strömbrytare. Rapporten kommer att presentera bakgrunden från Issakov’s arbete, grundläggande teori som används och genomförandet av det slutliga kretsschemat. Simuleringar visar att den presenterade lösningen fungerar, med en 15 dB konverteringsförlust. Denna konstruktion presterar väl jämfört med referens mixrar. Med denna rapport visas det att det är möjligt att göra ett enkelt och kompakt dopplerradarsystem i CMOS.

The development of the transistor and its continuous down-scaling has allowed during the last decades the appearance of cheap wireless communication systems targeting consumer products. The complexity of these systems has increased dramatically during the last years, mainly fueled by both the Moore law and improvements in communication theory. Originally, the radio transceivers were composed of only a few transistors, and supported simple analog modulation schemes. Currently, radio transceivers are composed of thousands of transistors including not only radio/analog blocks but also a huge amount of digital circuitry as well. These radios use advanced digital modulation schemes, channel coding, and multiple access schemes. Despite the fact that digital circuits currently offer an impressive performance, pure digital signal processing of radio signals remains limited for relatively low frequencies below a few hundred MHz. On the other hand, frequency bands used in current mobile applications span from around 800MHz up to 6 GHz and hence demand the use of analog circuits to down-convert the radio signals to lower frequencies that are suitable for digital processing. The group of circuits that form this part of the receiver is known as the radio receiver front-end. The design of modern radio receiver front-ends has many challenges. One requirement is support of a multitude of standards with bands that are scattered all along the mobile radio spectrum. Accordingly, the noise and linearity specifications for these front-ends are very stringent. Also, these specifications have to be accomplished using low-power, low-cost, highly integrated circuit solutions. This thesis presents the design of multi-band multi-standard receiver front-ends for fourth generation mobile communications. A novel methodology that speeds up the development of multi-band multi-standard RF blocks by automating some steps in the design is shown. Examples of submicron and nanometer CMOS wideband receiver front-ends targeting 4G mobile applications are presented. New techniques for inductorless wideband front-ends using current-mode technology are presented. Finally, novel RF calibration techniques to cope with process, voltage, and temperature variations in modern CMOS processes are demonstrated. / QC 20100806 / RaMSiS

The beginning of the 21st century sees great development and demands on wireless communication technologies. Wireless technologies, either based on a cable replacement or on a networked environment, penetrate our daily life more rapidly than ever. Low operational power, low cost, small form factor, and function diversity are the crucial requirements for a successful wireless product. The receiver??s front-end circuits play an important role in faithfully recovering the information transmitted through the wireless channel. Bluetooth is a short-range cable replacement wireless technology. A Bluetooth receiver architecture was proposed and designed using a pure CMOS process. The front-end of the receiver consists of a low noise amplifier (LNA) and mixer. The intermediate frequency was chosen to be 2MHz to save battery power and alleviate the low frequency noise problem. A conventional LNA architecture was used for reliability. The mixer is a modified Gilbert-cell using the current bleeding technique to further reduce the low frequency noise. The front-end draws 10 mA current from a 3 V power supply, has a 8.5 dB noise figure, and a voltage gain of 25 dB and -9 dBm IIP3. A front-end for dual-mode receiver is also designed to explore the capability of a multi-standard application. The two standards are IEEE 802.11b and Bluetooth. They work together making the wireless experience more exciting. The front-end is designed using BiCMOS technology and incorporating a direct conversion receiver architecture. A number of circuit techniques are used in the front-end design to achieve optimal results. It consumes 13.6 mA from a 2.5 V power supply with a 5.5 dB noise figure, 33 dB voltage gain and -13 dBm IIP3. Besides the system level contributions, intensive studies were carried out on the development of quality LNA circuits. Based on the multi-gated LNA structure, a CMOS LNA structure using bipolar transistors to provide linearization is proposed. This LNA configuration can achieve comparable linearity to its CMOS multi-gated counterpart and work at a higher frequency with less power consumption. A LNA using an on-chip transformer source degeneration is proposed to realize input impedance matching. The possibility of a dual-band cellular application is studied. Finally, a study on ultra-wide band (UWB) LNA implementation is performed to explore the possibility and capability of CMOS technology on the latest UWB standard for multimedia applications.

A series of sulfonate anionic lipids esters derived from 4-sulfobenzoic acid (single chain) or 5-sulfoisophthalic acid (double chain) with chain length from C14 to C18 were synthesized and characterized. The sodium salts were uniformly insoluble in ethanol; the tetramethylammonium salts of the single chain derivative from oleyl alcohol and the double chain derivative from 2-octyldodecan-1-ol were sufficiently soluble for subsequent experiments. Lipids in ethanol and aqueous buffers were mixed in a microfluidic system (NanoAssmblr ® microfluidic mixer) to prepare a lipid dispersion containing vesicles and/or nanoparticles. Initial studies on prediction and controlling vesicle size based on lipid geometric parameters showed that particle size could be successfully affected and controlled by altering lipid compositions consistent with the formation of vesicles. A survey using high resolution cryo-Scanning Transmission Electron microscopy of the sample made by the microfluidic mixer demonstrated that vesicles were formed but a majority of the sample reformed to other aggregates, which complicated the interpretation of the initial product distribution. Further investigation on the efficiency of incorporation of phospholipids into vesicles indicated that 55% of the initial phospholipid appeared in the vesicle fractions. Sulfonate anionic lipids are incorporated into vesicles with lower efficiency and reach a threshold beyond which the sulfonate lipid is not incorporated. Entrapment efficiency was studied with three dyes. Different concentrations of the hydrophobic neutral dye Nile red, the hydrophilic cationic dye neutral red and the hydrophilic anionic dye hydroxypyrene trisulfonate (HPTS) were prepared. The entrapment efficiency was quantitatively analyzed by HPLC, and electrospray mass spectrometry; up to 15% of the initial dye present could be entrapped. Vesicles permeability assays using the ion channel gramicidin and the ion carrier valinomycin with HPTS-loaded vesicle samples showed that vesicle samples made by the microfluidic mixer and made by a conventional extrusion method appeared to behave in the same manner. Addition of a sulfonate anionic lipid to the lipid mixture resulted in vesicle leakage. The unilamellar proportion of HPTS loaded vesicle samples was assessed using a mellitin assay. A vesicle sample made by the microfluidic mixer was 80% unilamellar; a vesicle sample made by the extrusion method on the same lipid mixture was 60% unilamellar. / Graduate / mengxiuzheng@gmail.com

This thesis examines the design of a QPSK demodulator frontend for GPON transceiver at end user's side. Since lowering the cost of the terminal transceivers in an access network like GPON is a key requirement, CMOS technology is used and several area-saving design techniques are applied. The designed frontend circuit saved more than 80% area of the key components like the mixers and the QVCO than some published designs which can also fit the application. A measurement in frequency domain and a simulation in time domain verified that this frontend is able to demodulate a QPSK signal with a data rate as high as 5 Gbit/s. Two structures of quadrature oscillators are firstly presented and compared. One is an LC QVCO centered at 5 GHz, which has a tuning range of 3 GHz, a phase noise of -100.8 dBc/Hz at 1 MHz offset, and an area of 0.15 mm2 excluding pads. The other is a ring QVCO which only takes an area of 0.019 mm2. But it has a higher phase noise of -81 dBc/Hz at 1 MHz offset. Then two broadband mixers are described separately. The first one provides a high conversion gain, but its input linearity is insufficient to meet the input power requirement. The second mixer obtains required input linearity but with a trade-off of conversion gain. Both mixers have a broadband input impedance match from 2 GHz to 8 GHz. The first mixer has a conversion gain of 8.5 dB and an input 1 dB compresion point at -17 dBm. The second mixer has a conversion gain of -7 dB with an on-chip buffer or -2.1 dB without buffer, but an input 1 dB compresion point at -5 dBm. A frontend circuit is lastly presented. It integrates the compact ring QVCO, two broadband mixers with high input linearity, and two second-order LC ladder low pass filters. A Frequency domain measurement shows the expected spectrum down conversion of a 2.5 Gsym/s QPSK signal centered at 5 GHz. The whole frontend circuit including pads takes 1 mm2 area, and consumed 157 mW power. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-06-29 10:59:45.312

In this thesis digital control techniques for two receiver front-end components i.e. the downconverter mixer and the modulator are presented. With decrease in size of CMOS-based geometries, decrease in performance and yield of analog components has become an issue. Using the digital components on a System-on-Chip to account for the shortcoming in analog circuitry and thereby developing 'self-calibrating' systems has become a reliable way to address this issue. In the telecommunications industry, this is directly correlated to lower post-fabrication testing times, quicker product development and lower overhead costs. The first design presented is a 0.13 um CMOS mixer with variable gain capability. A Digital Assist system was put in place to extend the 3-dB bandwidth of the system using a microcontroller. An interpolation routine was used to predict the bias voltages based on variations in frequency and desired input power. The digital-to-analog converter on the microcontroller was used to set the required bias voltages. The mixer's bandwidth was extended from 12GHz to 15GHz using digital assist. The gain of the mixer with the digital assist in place could be varied from 1.2-9.8dB. The second design presented is a 5.4GHz multi-scheme modulator fabricated in 0.13 um CMOS technology. The modulator is capable of carrying out quadrature amplitude modulation as well as phase-shift keying modulation. The modulator makes use of a novel OTA design to generate a set of orthogonal basis vectors which allows for facile mapping of the modulated data on the I-Q plane. The modulator carries out modulation in 4-PSK, 8-PSK, 4-QAM and 16-QAM modes with a maximum error vector magnitude of only 8.51%. A digital assist model to attain ubiquitous operation inside a system is also presented for this modulator. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2014-05-03 13:16:06.018

The Worldwide Interoperability for Microwave Access, or WiMax, is a wireless communication technique based on IEEE 802.16 standards. Its advantage of sending high data rates over long distances, while using a single base station to cover a large area, has made this technique a flexible and reliable solution for public wireless networks. WiMax has two main types of networks: Fixed and Mobile. The most popular transceiver used in WiMax applications is the “Direct-Conversion Architecture” due to its high level of integration and less component requirements, which leads to reduced power dissipation. In Direct Conversion Architecture, the mixer is a key block in the transceiver chain. Depending on design specifications and constraints, different types of mixers may be considered. However, the most appropriate down converter mixer for WiMax applications is the Gilbert-cell mixer. This thesis will then explore the design of a down converter Gilbert-Cell Mixer within the realm of Fixed WiMax technology. This design was achieved in the commercial circuit simulator Advanced Design System (ADS) using the 0.15mm InGaAs pHEMT technology process provided by Win Semiconductor Crop.

The Worldwide Interoperability for Microwave Access, or WiMax, is a wireless communication technique based on IEEE 802.16 standards. Its advantage of sending high data rates over long distances, while using a single base station to cover a large area, has made this technique a flexible and reliable solution for public wireless networks. WiMax has two main types of networks: Fixed and Mobile. The most popular transceiver used in WiMax applications is the “Direct-Conversion Architecture” due to its high level of integration and less component requirements, which leads to reduced power dissipation. In Direct Conversion Architecture, the mixer is a key block in the transceiver chain. Depending on design specifications and constraints, different types of mixers may be considered. However, the most appropriate down converter mixer for WiMax applications is the Gilbert-cell mixer. This thesis will then explore the design of a down converter Gilbert-Cell Mixer within the realm of Fixed WiMax technology. This design was achieved in the commercial circuit simulator Advanced Design System (ADS) using the 0.15mm InGaAs pHEMT technology process provided by Win Semiconductor Crop.

The diploma thesis is focused on the design of an industrial planetary mixer with a volume of 40 liters. The goal is to create a design that takes account of ergonomics and design and technology requirements.