In this thesis work, a design of RF down-conversion mixer for WLAN standard, such as Wi-Fi or Bluetooth is presented. The target technology is 0.35um CMOS process. Several mixer topologies are analyzed and simulated at the schematic level using the Cadence Spectre-RF software. The active double balanced mixer is chosen for the ultimate implementation. For this mixer simulation results from schematic level to layout level are presented and discussed in detail. To build an RF front-end, the complete mixer is integrated with an available LNA block. The performance of the front-end is evaluated as well. The obtained simulation results satisfy the specification for Wi-Fi standard. Since the RF front-end is designed for testability, the fault simulation is incorporated as well. So the performance of the front end is also evaluated for so called “spot defects”, typical of CMOS technology. They are modeled using resistive shorts or opens in the circuit.

The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). To meet high propagation rates, the communication devices used in IEEE 802.11a protocol usually present a high conversion gain and a high linearity (denoted as third order intercept point, IIP3). The IIP3 of conventional up- and down-conversion mixers are only about 0 dBm and -5 dBm, which fail to achieve a high propagation rate of data. This thesis utilizes the TSMC 0.18 £gm CMOS technology to design and fabrication up- and down-conversion mixers with very high linearity for IEEE 802.11a application. The proposed high-linearity up-conversion mixer with 1.01 mm ¡Ñ 0.85 mm chip size and its wide bandwidth (5~6 GHz) is well suited for IEEE 802.11a application. To enhance the linearity and bandwidth, a transconductor stage with gm-boosted structure, a switch stgae with LO-body grounded structure and a load stage with shunt peaking structure are adopted in this research. Under 5.2/5.4/5.8 GHz operating frequencies, the implemented up-conversion mixer demonstrates a high conversion gain of 6.8/7.1/6.3 dB and a high linearity of 8.9/9/13.2 dBm, respectivly. In addition, a moderate consuming power (6.86 mW) of such mixer can be achieved at 1.2 V supply voltage. On the other hand, this thesis also designed and fabricated a high-linearity down-conversion mixer with chip size of 1.02 mm ¡Ñ 0.86 mm and 5.2 GHz center frequency. To improve the linearity and isolation and reduce the high-order noise, a transconductor stage with dual-gate structure and a load stage with RC-tank structure are adopted in this research. According to the EM-simulation resutls, the proposed down-conversion mixer presents a moderate conversion gain of 6 dB and a high linearity of 0.8 dBm. Additionly, a moderate consuming power (6.75 mW) of such mixer can be achieved at 1.8 V supply voltage.

Experiments were investigated on passive mixing enhancements in different geometric microchannels with roughened surfaces and flow was driven by electroosmotic flow (0.027 ≤ Re ≤ 0.081). Experiments were perform using micro particle image velocimetry (MPIV) technology for velocity measurements and relative analysis. Iodine and DI water mixing experiments were captured by common optical microscope for flow visualization, and rhodamine B and buffers mixing experiments were measured by micro laser-induced fluorescence (µLIF) technology for concentration field measurements and analysis. The experimental results showed that the Twr and Tcdr micromixers can generate chaotic flow and enhance the mixing performance in the short channel length. Finally, the mixing length was developed in terms of within accuracy between the experimental data and prediction data.

This dissertation presents novel Harmonic Rejection (HR) Mixer architectures to obtain a high level of harmonic rejection. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. Consequently, the HR performance for this mixer architecture is primarily determined by resistor and capacitor matching at low intermediate frequencies (IF). Since large resistor areas can be used at relatively less power penalty in the low frequency IF section, superior HR performance is realized. A design fabricated in 110 nm CMOS process, rejects up to the fi rst 14 local oscillator (LO) harmonics and achieves 3rd, 5th and 7th HR ratios in excess of 52, 54 and 55 dB respectively, without any calibration or trimming. This mixer architecture also rejects flicker noise, has improved image rejection (IR) and second-order input-intercept-point (IIP2) performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in 55 nm standard CMOS process has a programmable number of 8, 10, 12 or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the 3rd harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm. The mixers presented in this dissertation set the state-of-the-art in HR performance for single-stage mixers with configurable number of phases without using any calibration or trimming. / text

The functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF. / text

The design, simulation, and measurement of two bulk-driven down-conversion mixers with on-chip transformer baluns in 0.18 μm CMOS is presented. Applying either the RF signal or the local oscillator (LO) signal to the bulk connection of the transistors allows the amplification and switching stages of a conventional mixer to be combined into a single stage, thus improving the voltage headroom of the mixer. The addition of a transformer balun to the mixers improves the input impedance match, provides passive voltage gain, and performs single-ended to balanced conversion. A semi-analytical power-series analysis of the mixers is also presented. The mixer in which the RF signal is applied to the gates of the mixing transistors achieves a measured input-referred 1-dB compression point (P1dB) of −14 dBm, an input-referred third-order intercept point (IIP3) of −5.2 dBm, a gain of 13.6 dB, a noise figure (NF) of 26 dB, and an LO-to-RF isolation of 50 dB. The overall performance of both mixers is found to be comparable with other CMOS mixers, but with a higher noise figure (which can be mitigated with a high gain low-noise amplifier (LNA)).

The pursuit of dense monolithic integration and higher operating speed continues to push the integrated circuit (IC) fabrication technologies to their limits. The increasing process variation, associated with aggressive technology scaling, is having a negative impact on circuit yield in current IC technologies, and the problem is likely to become worse in the future. Circuit solutions that are more tolerant of the process variations are needed to fully utilize the benefits of technology scaling. The primary goal of this research is to develop high-frequency circuits that can deliver consistent performance even under the threat of increasing process variation. These circuits can be used to build ``self-healing" systems, which can detect process imperfections and compensate accordingly to optimize performance. In addition to improving yield, such adaptive circuits and systems can provide more robust and efficient solutions for a wide range of applications under varying operational and environmental conditions.Silicon-germanium (SiGe) BiCMOS technology is an ideal platform for highly integrated systems requiring both high-performance analog and radio-frequency (RF) circuits as well as large-scale digital functionality. This research is focused on designing circuit components for a high-frequency wideband self-healing receiver in SiGe BiCMOS technology. An adaptive image-reject mixer, low insertion-loss switches, a wideband low-noise amplifier (LNA), and a SiGe complementary LC oscillator were designed. Healing algorithms were developed, and automated self-healing of multiple parameters of the mixer was demonstrated in measurement. A monte-carlo simulation based methodology was developed to verify the effectiveness of the healing procedure. In summary, this research developed circuits, algorithms, simulation tools, and methods that are useful for building "self-healing" systems.

The design, simulation, and measurement of two bulk-driven down-conversion mixers with on-chip transformer baluns in 0.18 μm CMOS is presented. Applying either the RF signal or the local oscillator (LO) signal to the bulk connection of the transistors allows the amplification and switching stages of a conventional mixer to be combined into a single stage, thus improving the voltage headroom of the mixer. The addition of a transformer balun to the mixers improves the input impedance match, provides passive voltage gain, and performs single-ended to balanced conversion. A semi-analytical power-series analysis of the mixers is also presented. The mixer in which the RF signal is applied to the gates of the mixing transistors achieves a measured input-referred 1-dB compression point (P1dB) of −14 dBm, an input-referred third-order intercept point (IIP3) of −5.2 dBm, a gain of 13.6 dB, a noise figure (NF) of 26 dB, and an LO-to-RF isolation of 50 dB. The overall performance of both mixers is found to be comparable with other CMOS mixers, but with a higher noise figure (which can be mitigated with a high gain low-noise amplifier (LNA)).

Made available in DSpace on 2014-06-11T19:24:44Z (GMT). No. of bitstreams: 0 Previous issue date: 2007-05-04Bitstream added on 2014-06-13T19:31:38Z : No. of bitstreams: 1 costa_fq_me_botfca.pdf: 515742 bytes, checksum: a30e1a1f53936669a5819763588c3bf2 (MD5) / O conhecimento das propriedades reológicas é de grande importância no processamento, manuseio, controle de qualidade e desenvolvimento de diversos produtos. Determinar as propriedades de fluxo de produtos alimentícios é necessário para avaliar os efeitos dos diferentes métodos de processos ou de fatores como a potência requerida durante uma mistura, fornecendo subsídios à projetos de engenharia para o dimensionamento adequado de motores e bombas, que efetuem operação de mistura ou agitação com o mínimo de consumo de energia elétrica e a perda de carga em tubos de escoamentos. A concepção de um misturador ou sistema de agitação para fluidos passa necessariamente por uma análise reológica. Sendo os parâmetros empíricos como o índice de escoamento, o índice de consistência e a curva reológica dos alimentos, informações importantes no processamento e armazenamento de produtos alimentícios, este trabalho teve por objetivos: avaliar o uso de um misturador ou sistema de agitação Ika LR-2.ST com um agitador modelo Eurostar Power control-visc P7 acoplado a um impelidor do tipo âncora plana modificada e pela unidade de medida Ika Viscovlick VK 600 - na determinação das propriedades reológicas do mel de abelhas, suco concentrado de pessego, suco concentrado de laranja (sem adicao de acucar) e suco concentrado de goiaba; verificar o modelo matematico mais adequado ao comportamento de fluxo dos produtos analisados; calcular a potencia requerida numa operacao de agitacao ou mistura. O equipamento utilizado para a obtencao dos resultados foi o Sistema de Agitacao, devido a sua versatilidade em relacao ao Viscosimetro Convencional, pois este permite a analise com amostras com um volume de ate 2 litros, com fluidos em processos de reacoes quimicas, a baixa pressao, entre outras caracteristicas. Os parametros reologicos obtidos atraves do viscosimetro de cilindros concentricos... / The knowledge of the rheological properties is of great importance in the processing, handling, quality control and development of several products. The determination of the properties of flow of nutritious products is necessary to evaluate the effects of the different methods of processes or of factors as the potency requested during a mixture, supplying subsidies to engineering projects for the appropriate dimensioning of motors and bombs, that make mixture operation or agitation with the electric minimum of energy consumption and the load loss in tubes of drainages. A mixer's conception or agitation system for fluids necessarily goes by an rheological analysis. Being the empiric parameters as the drainage index, the consistence index and the rheological curve of the foods, important information in the processing and storage of nutritive products, this work has had for objectives: the validation of a mixer's use or agitation system - Ika LR-2.ST with an agitator Eurostar Power control-visc coupled P7 to an impelidor of plain anchor modified type and for the unit of measure Ika Viscovlick VK 600 - in the determination of the rheological properties of the honey of bees, concentrated juice of peach, concentrated juice of orange (without addition of sugar) and concentrated juice of guava; the verification of the more appropriate mathematical model to the behavior of flow of the analyzed products; the calculation of the requested potency in an agitation operation or mixes. The System of Agitation was used because he is much more versatile than a conventional viscometer because it allows the work with a sample volume of up to two liters, with fluids in processes of chemical reactions, the low pressure, among other characteristics The rheological parameters obtained through the viscometer of concentric cylinders Brookfield with sensor LV - SC4-31, were used as pattern in the comparison with the data... (Complete abstract click electronic access)

The design, simulation, and measurement of two bulk-driven down-conversion mixers with on-chip transformer baluns in 0.18 μm CMOS is presented. Applying either the RF signal or the local oscillator (LO) signal to the bulk connection of the transistors allows the amplification and switching stages of a conventional mixer to be combined into a single stage, thus improving the voltage headroom of the mixer. The addition of a transformer balun to the mixers improves the input impedance match, provides passive voltage gain, and performs single-ended to balanced conversion. A semi-analytical power-series analysis of the mixers is also presented. The mixer in which the RF signal is applied to the gates of the mixing transistors achieves a measured input-referred 1-dB compression point (P1dB) of −14 dBm, an input-referred third-order intercept point (IIP3) of −5.2 dBm, a gain of 13.6 dB, a noise figure (NF) of 26 dB, and an LO-to-RF isolation of 50 dB. The overall performance of both mixers is found to be comparable with other CMOS mixers, but with a higher noise figure (which can be mitigated with a high gain low-noise amplifier (LNA)). / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate